source: rtems/c/src/lib/libbsp/powerpc/gen5200/irq/irq.h @ a877cc8e

Last change on this file since a877cc8e was a877cc8e, checked in by Ralf Corsepius <ralf.corsepius@…>, on Oct 17, 2006 at 2:46:07 AM

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1/*===============================================================*\
2| Project: RTEMS generic MPC5200 BSP                              |
3+-----------------------------------------------------------------+
4| Partially based on the code references which are named below.   |
5| Adaptions, modifications, enhancements and any recent parts of  |
6| the code are:                                                   |
7|                    Copyright (c) 2005                           |
8|                    Embedded Brains GmbH                         |
9|                    Obere Lagerstr. 30                           |
10|                    D-82178 Puchheim                             |
11|                    Germany                                      |
12|                    rtems@embedded-brains.de                     |
13+-----------------------------------------------------------------+
14| The license and distribution terms for this file may be         |
15| found in the file LICENSE in this distribution or at            |
16|                                                                 |
17| http://www.rtems.com/license/LICENSE.                           |
18|                                                                 |
19+-----------------------------------------------------------------+
20| this file contains declarations for the irq controller handler  |
21\*===============================================================*/
22/***********************************************************************/
23/*                                                                     */
24/*   Module:       irq.h                                               */
25/*   Date:         07/17/2003                                          */
26/*   Purpose:      RTEMS MPC5x00 CPU interrupt header file             */
27/*                                                                     */
28/*---------------------------------------------------------------------*/
29/*                                                                     */
30/*   Description:  This include file describe the data structure and   */
31/*                 the functions implemented by rtems to write         */
32/*                 interrupt handlers.                                 */
33/*                                                                     */
34/*---------------------------------------------------------------------*/
35/*                                                                     */
36/*   Code                                                              */
37/*   References:   MPC8260ads CPU interrupt header file                */
38/*   Module:       irq.h                                               */
39/*   Project:      RTEMS 4.6.0pre1 / MCF8260ads BSP                    */
40/*   Version       1.1                                                 */
41/*   Date:         10/10/2002                                          */
42/*                                                                     */
43/*   Author(s) / Copyright(s):                                         */
44/*                                                                     */
45/*   Copyright (C) 1999 valette@crf.canon.fr                           */
46/*                                                                     */
47/*   This code is heavilly inspired by the public specification of     */
48/*   STREAM V2 that can be found at:                                   */
49/*                                                                     */
50/*   <http://www.chorus.com/Documentation/index.html> by following     */
51/*   the STREAM API Specification Document link.                       */
52/*                                                                     */
53/*   Modified for mpc8260 by Andy Dachs <a.dachs@sstl.co.uk>           */
54/*   Surrey Satellite Technology Limited                               */
55/*   The interrupt handling on the mpc8260 seems quite different from  */
56/*   the 860 (I don't know the 860 well).  Although some interrupts    */
57/*   are routed via the CPM irq and some are direct to the SIU they    */
58/*   all appear logically the same.Therefore I removed the distinction */
59/*   between SIU and CPM interrupts.                                   */
60/*                                                                     */
61/*   The license and distribution terms for this file may be           */
62/*   found in found in the file LICENSE in this distribution or at     */
63/*   http://www.OARcorp.com/rtems/license.html.                        */
64/*                                                                     */
65/*---------------------------------------------------------------------*/
66/*                                                                     */
67/*   Partially based on the code references which are named above.     */
68/*   Adaptions, modifications, enhancements and any recent parts of    */
69/*   the code are under the right of                                   */
70/*                                                                     */
71/*         IPR Engineering, Dachauer Straße 38, D-80335 MÃŒnchen        */
72/*                        Copyright(C) 2003                            */
73/*                                                                     */
74/*---------------------------------------------------------------------*/
75/*                                                                     */
76/*   IPR Engineering makes no representation or warranties with        */
77/*   respect to the performance of this computer program, and          */
78/*   specifically disclaims any responsibility for any damages,        */
79/*   special or consequential, connected with the use of this program. */
80/*                                                                     */
81/*---------------------------------------------------------------------*/
82/*                                                                     */
83/*   Version history:  1.0                                             */
84/*                                                                     */
85/***********************************************************************/
86
87#ifndef LIBBSP_POWERPC_MPC5200_IRQ_IRQ_H
88#define LIBBSP_POWERPC_MPC5200_IRQ_IRQ_H
89
90#define CHK_CE_SHADOW(pmce)  ((pmce) & 0x00000001)
91#define CHK_CSE_STICKY(pmce) (((pmce) >> 10) & 0x00000001)
92#define CHK_MSE_STICKY(pmce) (((pmce) >> 21) & 0x00000001)
93#define CHK_PSE_STICKY(pmce) (((pmce) >> 29) & 0x00000001)
94#define CLR_CSE_STICKY(pmce) ((pmce) |= (1 << 29 ))
95#define CLR_MSE_STICKY(pmce) ((pmce) |= (1 << 21 ))
96#define CLR_PSE_STICKY(pmce) ((pmce) |= (1 << 10 ))
97#define CSE_SOURCE(source)       (((source) >> 8) & 0x00000003)
98#define MSE_SOURCE(source)       (((source) >> 16) & 0x0000001F)
99#define PSE_SOURCE(source)       (((source) >> 24) & 0x0000001F)
100
101/*
102 * Base index for the module specific irq handlers
103 */
104#define BSP_ASM_IRQ_VECTOR_BASE                         0
105#define BSP_PER_VECTOR_BASE                                     BSP_ASM_IRQ_VECTOR_BASE /* 0 */
106/*
107 * Peripheral IRQ handlers related definitions
108 */
109#define BSP_PER_IRQ_NUMBER                                      22
110#define BSP_PER_IRQ_LOWEST_OFFSET                       BSP_PER_VECTOR_BASE  /* 0 */
111#define BSP_PER_IRQ_MAX_OFFSET                          BSP_PER_IRQ_LOWEST_OFFSET + BSP_PER_IRQ_NUMBER - 1 /* 21 */
112/*
113 * Main IRQ handlers related definitions
114 */
115#define BSP_MAIN_IRQ_NUMBER                                     17
116#define BSP_MAIN_IRQ_LOWEST_OFFSET                      BSP_PER_IRQ_MAX_OFFSET + 1 /* 22 */
117#define BSP_MAIN_IRQ_MAX_OFFSET                         BSP_MAIN_IRQ_LOWEST_OFFSET + BSP_MAIN_IRQ_NUMBER - 1 /* 38 */
118/*
119 * Critical IRQ handlers related definitions
120 */
121#define BSP_CRIT_IRQ_NUMBER                                     4
122#define BSP_CRIT_IRQ_LOWEST_OFFSET                      BSP_MAIN_IRQ_MAX_OFFSET + 1 /* 39 */
123#define BSP_CRIT_IRQ_MAX_OFFSET                         BSP_CRIT_IRQ_LOWEST_OFFSET + BSP_CRIT_IRQ_NUMBER - 1 /* 42 */
124/*
125 * Summary of SIU interrupts
126 */
127#define BSP_SIU_IRQ_NUMBER                                      BSP_CRIT_IRQ_MAX_OFFSET + 1 /* 43 */
128#define BSP_SIU_IRQ_LOWEST_OFFSET                       BSP_PER_IRQ_LOWEST_OFFSET /* 0 */
129#define BSP_SIU_IRQ_MAX_OFFSET                          BSP_CRIT_IRQ_MAX_OFFSET  /* 42 */
130/*
131 * Processor IRQ handlers related definitions
132 */
133#define BSP_PROCESSOR_IRQ_NUMBER                        3
134#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET         BSP_CRIT_IRQ_MAX_OFFSET + 1 /* 44  */
135#define BSP_PROCESSOR_IRQ_MAX_OFFSET            BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER - 1 /* 46 */
136/*
137 * Summary
138 */
139#define BSP_IRQ_NUMBER                                          BSP_PROCESSOR_IRQ_MAX_OFFSET + 1 /* 47 */
140#define BSP_LOWEST_OFFSET                                       BSP_PER_IRQ_LOWEST_OFFSET /* 0 */
141#define BSP_MAX_OFFSET                                          BSP_PROCESSOR_IRQ_MAX_OFFSET /* 46 */
142
143#ifndef ASM
144
145/*
146extern volatile unsigned int ppc_cached_irq_mask;
147*/
148
149/*
150 * index table for the module specific handlers, a few entries are only placeholders
151 */
152typedef enum
153        {
154        BSP_SIU_IRQ_SMARTCOMM   =       BSP_PER_IRQ_LOWEST_OFFSET + 0,
155        BSP_SIU_IRQ_PSC1                =       BSP_PER_IRQ_LOWEST_OFFSET + 1,
156        BSP_SIU_IRQ_PSC2                =       BSP_PER_IRQ_LOWEST_OFFSET + 2,
157        BSP_SIU_IRQ_PSC3                =       BSP_PER_IRQ_LOWEST_OFFSET + 3,
158        BSP_SIU_IRQ_PSC6                =       BSP_PER_IRQ_LOWEST_OFFSET + 4,
159        BSP_SIU_IRQ_ETH                 =       BSP_PER_IRQ_LOWEST_OFFSET + 5,
160        BSP_SIU_IRQ_USB                 =       BSP_PER_IRQ_LOWEST_OFFSET + 6,
161        BSP_SIU_IRQ_ATA                 =       BSP_PER_IRQ_LOWEST_OFFSET + 7,
162        BSP_SIU_IRQ_PCI_CRT             =       BSP_PER_IRQ_LOWEST_OFFSET + 8,
163        BSP_SIU_IRQ_PCI_SC_RX           =       BSP_PER_IRQ_LOWEST_OFFSET + 9,
164        BSP_SIU_IRQ_PCI_SC_TX           =       BSP_PER_IRQ_LOWEST_OFFSET + 10,
165        BSP_SIU_IRQ_PSC4                =       BSP_PER_IRQ_LOWEST_OFFSET + 11,
166        BSP_SIU_IRQ_PSC5                =       BSP_PER_IRQ_LOWEST_OFFSET + 12,
167        BSP_SIU_IRQ_SPI_MODF            =       BSP_PER_IRQ_LOWEST_OFFSET + 13,
168        BSP_SIU_IRQ_SPI_SPIF            =       BSP_PER_IRQ_LOWEST_OFFSET + 14,
169        BSP_SIU_IRQ_I2C1                =       BSP_PER_IRQ_LOWEST_OFFSET + 15,
170        BSP_SIU_IRQ_I2C2                =       BSP_PER_IRQ_LOWEST_OFFSET + 16,
171        BSP_SIU_IRQ_MSCAN1              =       BSP_PER_IRQ_LOWEST_OFFSET + 17,
172        BSP_SIU_IRQ_MSCAN2              =       BSP_PER_IRQ_LOWEST_OFFSET + 18,
173        BSP_SIU_IRQ_IR_RX               =       BSP_PER_IRQ_LOWEST_OFFSET + 19,
174        BSP_SIU_IRQ_IR_TX               =       BSP_PER_IRQ_LOWEST_OFFSET + 20,
175        BSP_SIU_IRQ_XLB_ARB             =       BSP_PER_IRQ_LOWEST_OFFSET + 21,
176
177        BSP_SIU_IRQ_SL_TIMER1           =       BSP_MAIN_IRQ_LOWEST_OFFSET + 0, /* handler entry only used in case of SMI */
178        BSP_SIU_IRQ_IRQ1                =       BSP_MAIN_IRQ_LOWEST_OFFSET + 1,
179        BSP_SIU_IRQ_IRQ2                =       BSP_MAIN_IRQ_LOWEST_OFFSET + 2,
180        BSP_SIU_IRQ_IRQ3                =       BSP_MAIN_IRQ_LOWEST_OFFSET + 3,
181        BSP_SIU_IRQ_LO_INT              =       BSP_MAIN_IRQ_LOWEST_OFFSET + 4, /* handler entry never used (only placeholder) */
182        BSP_SIU_IRQ_RTC_PER         =   BSP_MAIN_IRQ_LOWEST_OFFSET + 5,
183        BSP_SIU_IRQ_RTC_STW         =   BSP_MAIN_IRQ_LOWEST_OFFSET + 6,
184        BSP_SIU_IRQ_GPIO_STD    =       BSP_MAIN_IRQ_LOWEST_OFFSET + 7,
185        BSP_SIU_IRQ_GPIO_WKUP   =       BSP_MAIN_IRQ_LOWEST_OFFSET + 8,
186        BSP_SIU_IRQ_TMR0                =       BSP_MAIN_IRQ_LOWEST_OFFSET + 9,
187        BSP_SIU_IRQ_TMR1                =       BSP_MAIN_IRQ_LOWEST_OFFSET + 10,
188        BSP_SIU_IRQ_TMR2                =       BSP_MAIN_IRQ_LOWEST_OFFSET + 1,
189        BSP_SIU_IRQ_TMR3                =       BSP_MAIN_IRQ_LOWEST_OFFSET + 12,
190        BSP_SIU_IRQ_TMR4                =       BSP_MAIN_IRQ_LOWEST_OFFSET + 13,
191        BSP_SIU_IRQ_TMR5                =       BSP_MAIN_IRQ_LOWEST_OFFSET + 14,
192        BSP_SIU_IRQ_TMR6                =       BSP_MAIN_IRQ_LOWEST_OFFSET + 15,
193        BSP_SIU_IRQ_TMR7                =       BSP_MAIN_IRQ_LOWEST_OFFSET + 16,
194
195        BSP_SIU_IRQ_IRQ0                =       BSP_CRIT_IRQ_LOWEST_OFFSET + 0,
196        BSP_SIU_IRQ_SL_TIMER0   =       BSP_CRIT_IRQ_LOWEST_OFFSET + 1,
197        BSP_SIU_IRQ_HI_INT              =       BSP_CRIT_IRQ_LOWEST_OFFSET + 2, /* handler entry never used (only placeholder) */
198        BSP_SIU_IRQ_CSS_WKUP    =       BSP_CRIT_IRQ_LOWEST_OFFSET + 3,
199
200        BSP_DECREMENTER             =   BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 0,
201        BSP_SYSMGMT                             =   BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 1,
202        BSP_EXT                 =   BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 2
203
204        }rtems_irq_symbolic_name;
205
206#define BSP_CRIT_IRQ_PRIO_LEVELS                          4
207/*#define BSP_PERIODIC_TIMER                  BSP_DECREMENTER*/
208#define BSP_PERIODIC_TIMER                    BSP_SIU_IRQ_TMR6
209/*#define CPM_INTERRUPT*/
210
211
212/*
213 * Type definition for RTEMS managed interrupts
214 */
215typedef unsigned char  rtems_irq_prio;
216struct  __rtems_irq_connect_data__;     /* forward declaratiuon */
217
218typedef unsigned int rtems_irq_number;
219typedef void *rtems_irq_hdl_param;
220typedef void (*rtems_irq_hdl)           (rtems_irq_hdl_param);
221typedef void (*rtems_irq_enable)            (const struct __rtems_irq_connect_data__*);
222typedef void (*rtems_irq_disable)           (const struct __rtems_irq_connect_data__*);
223typedef int  (*rtems_irq_is_enabled)    (const struct __rtems_irq_connect_data__*);
224
225typedef struct __rtems_irq_connect_data__ {
226  /*
227   * IRQ line
228   */
229  rtems_irq_number              name;
230  /*
231   * handler. See comment on handler properties below in function prototype.
232   */
233  rtems_irq_hdl                 hdl;
234  /*
235   * Handler handle to store private data
236   */
237  rtems_irq_hdl_param           handle;
238  /*
239   * function for enabling interrupts at device level (ONLY!).
240   * The BSP code will automatically enable it at i8259s level.
241   * RATIONALE : anyway such code has to exist in current driver code.
242   * It is usually called immediately AFTER connecting the interrupt handler.
243   * RTEMS may well need such a function when restoring normal interrupt
244   * processing after a debug session.
245   *
246   */
247  rtems_irq_enable            on;
248  /*
249   * function for disabling interrupts at device level (ONLY!).
250   * The code will disable it at i8259s level. RATIONALE : anyway
251   * such code has to exist for clean shutdown. It is usually called
252   * BEFORE disconnecting the interrupt. RTEMS may well need such
253   * a function when disabling normal interrupt processing for
254   * a debug session. May well be a NOP function.
255   */
256  rtems_irq_disable             off;
257  /*
258   * function enabling to know what interrupt may currently occur
259   * if someone manipulates the i8259s interrupt mask without care...
260   */
261  rtems_irq_is_enabled        isOn;
262
263#ifdef BSP_SHARED_HANDLER_SUPPORT
264  /*
265   *  Set to -1 for vectors forced to have only 1 handler
266   */
267  void *next_handler;
268#endif
269
270} rtems_irq_connect_data;
271
272typedef struct {
273  /*
274   * size of all the table fields (*Tbl) described below.
275   */
276  unsigned int                  irqNb;
277  /*
278   * Default handler used when disconnecting interrupts.
279   */
280  rtems_irq_connect_data        defaultEntry;
281  /*
282   * Table containing initials/current value.
283   */
284  rtems_irq_connect_data*       irqHdlTbl;
285  /*
286   * actual value of BSP_PER_IRQ_VECTOR_BASE...
287   */
288  rtems_irq_symbolic_name       irqBase;
289  /*
290   * software priorities associated with interrupts.
291   * if irqPrio  [i]  >  intrPrio  [j]  it  means  that
292   * interrupt handler hdl connected for interrupt name i
293   * will  not be interrupted by the handler connected for interrupt j
294   * The interrupt source  will be physically masked at i8259 level.
295   */
296    rtems_irq_prio*             irqPrioTbl;
297}rtems_irq_global_settings;
298
299
300
301/*-------------------------------------------------------------------------+
302| Function Prototypes.
303+--------------------------------------------------------------------------*/
304/*
305 * ------------------------ PPC CPM Mngt Routines -------
306 */
307
308/*
309 * function to disable a particular irq. After calling
310 * this function, even if the device asserts the interrupt line it will
311 * not be propagated further to the processor
312 */
313int BSP_irq_disable_at_siu        (const rtems_irq_symbolic_name irqLine);
314/*
315 * function to enable a particular irq. After calling
316 * this function, if the device asserts the interrupt line it will
317 * be propagated further to the processor
318 */
319int BSP_irq_enable_at_siu               (const rtems_irq_symbolic_name irqLine);
320/*
321 * function to acknoledge a particular irq. After calling
322 * this function, if a device asserts an enabled interrupt line it will
323 * be propagated further to the processor. Mainly usefull for people
324 * writting raw handlers as this is automagically done for rtems managed
325 * handlers.
326 */
327int BSP_irq_ack_at_siu                  (const rtems_irq_symbolic_name irqLine);
328/*
329 * function to check if a particular irq is enabled. After calling
330 */
331int BSP_irq_enabled_at_siu      (const rtems_irq_symbolic_name irqLine);
332
333
334
335/*
336 * ------------------------ RTEMS Single Irq Handler Mngt Routines ----------------
337 */
338/*
339 * function to connect a particular irq handler. This hanlder will NOT be called
340 * directly as the result of the corresponding interrupt. Instead, a RTEMS
341 * irq prologue will be called that will :
342 *
343 *      1) save the C scratch registers,
344 *      2) switch to a interrupt stack if the interrupt is not nested,
345 *      4) modify them to disable the current interrupt at  SIU level (and may
346 *      be others depending on software priorities)
347 *      5) aknowledge the SIU',
348 *      6) demask the processor,
349 *      7) call the application handler
350 *
351 * As a result the hdl function provided
352 *
353 *      a) can perfectly be written is C,
354 *      b) may also well directly call the part of the RTEMS API that can be used
355 *      from interrupt level,
356 *      c) It only responsible for handling the jobs that need to be done at
357 *      the device level including (aknowledging/re-enabling the interrupt at device,
358 *      level, getting the data,...)
359 *
360 *      When returning from the function, the following will be performed by
361 *      the RTEMS irq epilogue :
362 *
363 *      1) masks the interrupts again,
364 *      2) restore the original SIU interrupt masks
365 *      3) switch back on the orinal stack if needed,
366 *      4) perform rescheduling when necessary,
367 *      5) restore the C scratch registers...
368 *      6) restore initial execution flow
369 *
370 */
371int BSP_install_rtems_irq_handler       (const rtems_irq_connect_data*);
372/*
373 * function to get the current RTEMS irq handler for ptr->name. It enables to
374 * define hanlder chain...
375 */
376int BSP_get_current_rtems_irq_handler   (rtems_irq_connect_data* ptr);
377/*
378 * function to get disconnect the RTEMS irq handler for ptr->name.
379 * This function checks that the value given is the current one for safety reason.
380 * The user can use the previous function to get it.
381 */
382int BSP_remove_rtems_irq_handler        (const rtems_irq_connect_data*);
383
384
385void BSP_rtems_irq_mng_init(unsigned cpuId);
386
387int BSP_rtems_irq_mngt_set(rtems_irq_global_settings* config);
388
389#endif
390
391#endif
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