1 | /** |
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2 | * @file |
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3 | * |
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4 | * @ingroup m |
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5 | * |
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6 | * @brief MSCAN register definitions and support functions. |
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7 | */ |
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8 | |
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9 | /* |
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10 | * Copyright (c) 2008 |
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11 | * Embedded Brains GmbH |
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12 | * Obere Lagerstr. 30 |
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13 | * D-82178 Puchheim |
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14 | * Germany |
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15 | * rtems@embedded-brains.de |
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16 | * |
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17 | * The license and distribution terms for this file may be |
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18 | * found in the file LICENSE in this distribution or at |
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19 | * http://www.rtems.com/license/LICENSE. |
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20 | */ |
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21 | |
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22 | #ifndef LIBBSP_MSCAN_BASE_H |
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23 | #define LIBBSP_MSCAN_BASE_H |
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24 | |
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25 | #include <stdbool.h> |
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26 | |
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27 | #include <bsp/mpc5200.h> |
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28 | |
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29 | /** |
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30 | * @defgroup m MSCAN |
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31 | * |
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32 | * @{ |
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33 | */ |
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34 | |
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35 | #define MSCAN_BIT_RATE_MIN 10000 |
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36 | |
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37 | #define MSCAN_BIT_RATE_MAX 1000000 |
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38 | |
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39 | #define MSCAN_BIT_RATE_DEFAULT 125000 |
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40 | |
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41 | #define MSCAN_FILTER_NUMBER_MIN 0 |
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42 | |
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43 | #define MSCAN_FILTER_NUMBER_2 2 |
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44 | |
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45 | #define MSCAN_FILTER_NUMBER_4 4 |
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46 | |
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47 | #define MSCAN_FILTER_NUMBER_MAX 8 |
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48 | |
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49 | #define MSCAN_FILTER_ID_DEFAULT 0U |
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50 | |
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51 | #define MSCAN_FILTER_MASK_DEFAULT 0xffffffffU |
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52 | |
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53 | #define MSCAN_TRANSMIT_BUFFER_NUMBER 3 |
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54 | |
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55 | /** |
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56 | * @name MSCAN Control Register 0 (CANCTL0) |
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57 | * |
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58 | * @{ |
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59 | */ |
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60 | |
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61 | #define CTL0_RXFRM (1 << 7) |
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62 | #define CTL0_RXACT (1 << 6) |
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63 | #define CTL0_CSWAI (1 << 5) |
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64 | #define CTL0_SYNCH (1 << 4) |
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65 | #define CTL0_TIME (1 << 3) |
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66 | #define CTL0_WUPE (1 << 2) |
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67 | #define CTL0_SLPRQ (1 << 1) |
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68 | #define CTL0_INITRQ (1 << 0) |
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69 | |
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70 | /** @} */ |
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71 | |
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72 | /** |
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73 | * @name MSCAN Control Register 1 (CANCTL1) |
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74 | * |
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75 | * @{ |
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76 | */ |
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77 | |
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78 | #define CTL1_CANE (1 << 7) |
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79 | #define CTL1_CLKSRC (1 << 6) |
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80 | #define CTL1_LOOPB (1 << 5) |
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81 | #define CTL1_LISTEN (1 << 4) |
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82 | #define CTL1_WUPM (1 << 2) |
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83 | #define CTL1_SLPAK (1 << 1) |
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84 | #define CTL1_INITAK (1 << 0) |
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85 | |
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86 | /** @} */ |
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87 | |
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88 | /** |
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89 | * @name MSCAN Bus Timing Register 0 (CANBTR0) |
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90 | * |
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91 | * @{ |
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92 | */ |
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93 | |
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94 | #define BTR0_SJW_MASK 0xc0 |
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95 | #define BTR0_BRP_MASK 0x3f |
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96 | |
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97 | #define BTR0_SJW( btr0) ((btr0) << 6) |
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98 | #define BTR0_BRP( btr0) ((btr0) << 0) |
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99 | |
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100 | #define BTR0_GET_SJW( btr0) (((btr0) & BTR0_SJW_MASK) >> 6) |
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101 | #define BTR0_GET_BRP( btr0) (((btr0) & BTR0_BRP_MASK) >> 0) |
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102 | |
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103 | /** @} */ |
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104 | |
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105 | /** |
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106 | * @name MSCAN Bus Timing Register 1 (CANBTR1) |
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107 | * |
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108 | * @{ |
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109 | */ |
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110 | |
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111 | #define BTR1_SAMP_MASK 0x80 |
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112 | #define BTR1_TSEG1_MASK 0x0f |
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113 | #define BTR1_TSEG2_MASK 0x70 |
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114 | |
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115 | #define BTR1_SAMP (1 << 7) |
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116 | #define BTR1_TSEG1( btr1) ((btr1) << 0) |
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117 | #define BTR1_TSEG2( btr1) ((btr1) << 4) |
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118 | |
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119 | #define BTR1_GET_TSEG1( btr0) (((btr0) & BTR1_TSEG1_MASK) >> 0) |
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120 | #define BTR1_GET_TSEG2( btr0) (((btr0) & BTR1_TSEG2_MASK) >> 4) |
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121 | |
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122 | /** @} */ |
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123 | |
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124 | /** |
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125 | * @name MSCAN Receiver Flag Register (CANRFLG) |
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126 | * |
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127 | * @{ |
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128 | */ |
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129 | |
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130 | #define RFLG_WUPIF (1 << 7) |
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131 | #define RFLG_CSCIF (1 << 6) |
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132 | #define RFLG_RSTAT_MASK (3 << 4) |
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133 | #define RFLG_RSTAT_OK (0 << 4) |
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134 | #define RFLG_RSTAT_WRN (1 << 4) |
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135 | #define RFLG_RSTAT_ERR (2 << 4) |
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136 | #define RFLG_RSTAT_OFF (3 << 4) |
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137 | #define RFLG_TSTAT_MASK (3 << 2) |
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138 | #define RFLG_TSTAT_OK (0 << 2) |
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139 | #define RFLG_TSTAT_WRN (1 << 2) |
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140 | #define RFLG_TSTAT_ERR (2 << 2) |
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141 | #define RFLG_TSTAT_OFF (3 << 2) |
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142 | #define RFLG_OVRIF (1 << 1) |
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143 | #define RFLG_RXF (1 << 0) |
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144 | #define RFLG_GET_RX_STATE(rflg) (((rflg) >> 4) & 0x03) |
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145 | #define RFLG_GET_TX_STATE(rflg) (((rflg) >> 2) & 0x03) |
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146 | |
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147 | /** @} */ |
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148 | |
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149 | /** |
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150 | * @name MSCAN Receiver Interrupt Enable Register (CANRIER) |
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151 | * |
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152 | * @{ |
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153 | */ |
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154 | |
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155 | #define RIER_WUPIE (1 << 7) |
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156 | #define RIER_CSCIE (1 << 6) |
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157 | #define RIER_RSTAT(rier) ((rier) << 4) |
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158 | #define RIER_TSTAT(rier) ((rier) << 2) |
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159 | #define RIER_OVRIE (1 << 1) |
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160 | #define RIER_RXFIE (1 << 0) |
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161 | |
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162 | /** @} */ |
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163 | |
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164 | /** |
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165 | * @name MSCAN Transmitter Flag Register (CANTFLG) |
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166 | * |
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167 | * @{ |
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168 | */ |
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169 | |
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170 | #define TFLG_TXE2 (1 << 2) |
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171 | #define TFLG_TXE1 (1 << 1) |
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172 | #define TFLG_TXE0 (1 << 0) |
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173 | |
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174 | /** @} */ |
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175 | |
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176 | /** |
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177 | * @name MSCAN Transmitter Interrupt Enable Register (CANTIER) |
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178 | * |
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179 | * @{ |
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180 | */ |
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181 | |
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182 | #define TIER_TXEI2 (1 << 2) |
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183 | #define TIER_TXEI1 (1 << 1) |
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184 | #define TIER_TXEI0 (1 << 0) |
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185 | |
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186 | /** @} */ |
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187 | |
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188 | /** |
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189 | * @name MSCAN Transmitter Message Abort Request (CANTARQ) |
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190 | * |
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191 | * @{ |
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192 | */ |
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193 | |
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194 | #define TARQ_ABTRQ2 (1 << 2) |
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195 | #define TARQ_ABTRQ1 (1 << 1) |
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196 | #define TARQ_ABTRQ0 (1 << 0) |
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197 | |
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198 | /** @} */ |
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199 | |
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200 | /** |
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201 | * @name MSCAN Transmitter Message Abort Acknoledge (CANTAAK) |
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202 | * |
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203 | * @{ |
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204 | */ |
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205 | |
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206 | #define TAAK_ABTRQ2 (1 << 2) |
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207 | #define TAAK_ABTRQ1 (1 << 1) |
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208 | #define TAAK_ABTRQ0 (1 << 0) |
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209 | |
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210 | /** @} */ |
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211 | |
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212 | /** |
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213 | * @name MSCAN Transmit Buffer Selection (CANBSEL) |
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214 | * |
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215 | * @{ |
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216 | */ |
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217 | |
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218 | #define BSEL_TX2 (1 << 2) |
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219 | #define BSEL_TX1 (1 << 1) |
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220 | #define BSEL_TX0 (1 << 0) |
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221 | |
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222 | /** @} */ |
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223 | |
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224 | /** |
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225 | * @name MSCAN ID Acceptance Control Register (CANIDAC) |
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226 | * |
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227 | * @{ |
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228 | */ |
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229 | |
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230 | #define IDAC_IDAM1 (1 << 5) |
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231 | #define IDAC_IDAM0 (1 << 4) |
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232 | #define IDAC_IDAM (IDAC_IDAM1 | IDAC_IDAM0) |
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233 | #define IDAC_IDHIT( idac) ((idac) & 0x7) |
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234 | |
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235 | /** @} */ |
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236 | |
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237 | /** |
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238 | * @brief MSCAN registers. |
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239 | */ |
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240 | typedef struct mpc5200_mscan mscan; |
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241 | |
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242 | /** |
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243 | * @brief MSCAN context that has to be saved throughout the initialization |
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244 | * mode. |
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245 | */ |
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246 | typedef struct { |
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247 | uint8_t ctl0; |
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248 | uint8_t rier; |
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249 | uint8_t tier; |
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250 | } mscan_context; |
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251 | |
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252 | bool mscan_enable( volatile mscan *m, unsigned bit_rate); |
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253 | |
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254 | void mscan_disable( volatile mscan *m); |
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255 | |
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256 | void mscan_interrupts_disable( volatile mscan *m); |
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257 | |
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258 | bool mscan_set_bit_rate( volatile mscan *m, unsigned bit_rate); |
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259 | |
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260 | void mscan_initialization_mode_enter( volatile mscan *m, mscan_context *context); |
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261 | |
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262 | void mscan_initialization_mode_leave( volatile mscan *m, const mscan_context *context); |
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263 | |
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264 | void mscan_sleep_mode_enter( volatile mscan *m); |
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265 | |
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266 | void mscan_sleep_mode_leave( volatile mscan *m); |
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267 | |
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268 | volatile uint8_t *mscan_id_acceptance_register( volatile mscan *m, unsigned i); |
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269 | |
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270 | volatile uint8_t *mscan_id_mask_register( volatile mscan *m, unsigned i); |
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271 | |
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272 | unsigned mscan_filter_number( volatile mscan *m); |
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273 | |
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274 | bool mscan_set_filter_number( volatile mscan *m, unsigned number); |
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275 | |
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276 | bool mscan_filter_operation( volatile mscan *m, bool set, unsigned index, uint32_t *id, uint32_t *mask); |
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277 | |
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278 | void mscan_filter_clear( volatile mscan *m); |
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279 | |
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280 | void mscan_get_error_counters( volatile mscan *m, unsigned *rec, unsigned *tec); |
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281 | |
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282 | /** @} */ |
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283 | |
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284 | #endif /* LIBBSP_MSCAN_BASE_H */ |
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