source: rtems/c/src/lib/libbsp/powerpc/gen5200/include/mscan-base.h @ 4f5d1c9f

4.104.11
Last change on this file since 4f5d1c9f was 4f5d1c9f, checked in by Thomas Doerfler <Thomas.Doerfler@…>, on Mar 27, 2010 at 3:00:43 PM

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1/**
2 * @file
3 *
4 * @ingroup m
5 *
6 * @brief MSCAN register definitions and support functions.
7 */
8
9/*
10 * Copyright (c) 2008
11 * Embedded Brains GmbH
12 * Obere Lagerstr. 30
13 * D-82178 Puchheim
14 * Germany
15 * rtems@embedded-brains.de
16 *
17 * The license and distribution terms for this file may be found in the file
18 * LICENSE in this distribution or at http://www.rtems.com/license/LICENSE.
19 */
20
21#ifndef LIBBSP_MSCAN_BASE_H
22#define LIBBSP_MSCAN_BASE_H
23
24#include <stdbool.h>
25
26#include <bsp/mpc5200.h>
27
28/**
29 * @defgroup m MSCAN
30 *
31 * @{
32 */
33
34#define MSCAN_BIT_RATE_MIN 10000
35
36#define MSCAN_BIT_RATE_MAX 1000000
37
38#define MSCAN_BIT_RATE_DEFAULT 125000
39
40#define MSCAN_FILTER_NUMBER_MIN 0
41
42#define MSCAN_FILTER_NUMBER_2 2
43
44#define MSCAN_FILTER_NUMBER_4 4
45
46#define MSCAN_FILTER_NUMBER_MAX 8
47
48#define MSCAN_FILTER_ID_DEFAULT 0U
49
50#define MSCAN_FILTER_MASK_DEFAULT 0xffffffffU
51
52#define MSCAN_TRANSMIT_BUFFER_NUMBER 3
53
54/**
55 * @name MSCAN Control Register 0 (CANCTL0)
56 *
57 * @{
58 */
59
60#define CTL0_RXFRM               (1 << 7)
61#define CTL0_RXACT               (1 << 6)
62#define CTL0_CSWAI               (1 << 5)
63#define CTL0_SYNCH               (1 << 4)
64#define CTL0_TIME                (1 << 3)
65#define CTL0_WUPE                (1 << 2)
66#define CTL0_SLPRQ               (1 << 1)
67#define CTL0_INITRQ              (1 << 0)
68
69/** @} */
70
71/**
72 * @name MSCAN Control Register 1 (CANCTL1)
73 *
74 * @{
75 */
76
77#define CTL1_CANE                (1 << 7)
78#define CTL1_CLKSRC              (1 << 6)
79#define CTL1_LOOPB               (1 << 5)
80#define CTL1_LISTEN              (1 << 4)
81#define CTL1_WUPM                (1 << 2)
82#define CTL1_SLPAK               (1 << 1)
83#define CTL1_INITAK              (1 << 0)
84
85/** @} */
86
87/**
88 * @name MSCAN Bus Timing Register 0 (CANBTR0)
89 *
90 * @{
91 */
92
93#define BTR0_SJW_MASK            0xc0
94#define BTR0_BRP_MASK            0x3f
95
96#define BTR0_SJW( btr0)          ((btr0) << 6)
97#define BTR0_BRP( btr0)          ((btr0) << 0)
98
99#define BTR0_GET_SJW( btr0)      (((btr0) & BTR0_SJW_MASK) >> 6)
100#define BTR0_GET_BRP( btr0)      (((btr0) & BTR0_BRP_MASK) >> 0)
101
102/** @} */
103
104/**
105 * @name MSCAN Bus Timing Register 1 (CANBTR1)
106 *
107 * @{
108 */
109
110#define BTR1_SAMP_MASK           0x80
111#define BTR1_TSEG1_MASK          0x0f
112#define BTR1_TSEG2_MASK          0x70
113
114#define BTR1_SAMP                (1 << 7)
115#define BTR1_TSEG1( btr1)        ((btr1) << 0)
116#define BTR1_TSEG2( btr1)        ((btr1) << 4)
117
118#define BTR1_GET_TSEG1( btr0)    (((btr0) & BTR1_TSEG1_MASK) >> 0)
119#define BTR1_GET_TSEG2( btr0)    (((btr0) & BTR1_TSEG2_MASK) >> 4)
120
121/** @} */
122
123/**
124 * @name MSCAN Receiver Flag Register (CANRFLG)
125 *
126 * @{
127 */
128
129#define RFLG_WUPIF               (1 << 7)
130#define RFLG_CSCIF               (1 << 6)
131#define RFLG_RSTAT_MASK          (3 << 4)
132#define RFLG_RSTAT_OK            (0 << 4)
133#define RFLG_RSTAT_WRN           (1 << 4)
134#define RFLG_RSTAT_ERR           (2 << 4)
135#define RFLG_RSTAT_OFF           (3 << 4)
136#define RFLG_TSTAT_MASK          (3 << 2)
137#define RFLG_TSTAT_OK            (0 << 2)
138#define RFLG_TSTAT_WRN           (1 << 2)
139#define RFLG_TSTAT_ERR           (2 << 2)
140#define RFLG_TSTAT_OFF           (3 << 2)
141#define RFLG_OVRIF               (1 << 1)
142#define RFLG_RXF                 (1 << 0)
143#define RFLG_GET_RX_STATE(rflg)  (((rflg) >> 4) & 0x03)
144#define RFLG_GET_TX_STATE(rflg)  (((rflg) >> 2) & 0x03)
145
146/** @} */
147
148/**
149 * @name MSCAN Receiver Interrupt Enable Register (CANRIER)
150 *
151 * @{
152 */
153
154#define RIER_WUPIE               (1 << 7)
155#define RIER_CSCIE               (1 << 6)
156#define RIER_RSTAT(rier)         ((rier) << 4)
157#define RIER_TSTAT(rier)         ((rier) << 2)
158#define RIER_OVRIE               (1 << 1)
159#define RIER_RXFIE               (1 << 0)
160
161/** @} */
162
163/**
164 * @name MSCAN Transmitter Flag Register (CANTFLG)
165 *
166 * @{
167 */
168
169#define TFLG_TXE2                (1 << 2)
170#define TFLG_TXE1                (1 << 1)
171#define TFLG_TXE0                (1 << 0)
172
173/** @} */
174
175/**
176 * @name MSCAN Transmitter Interrupt Enable Register (CANTIER)
177 *
178 * @{
179 */
180
181#define TIER_TXEI2               (1 << 2)
182#define TIER_TXEI1               (1 << 1)
183#define TIER_TXEI0               (1 << 0)
184
185/** @} */
186
187/**
188 * @name MSCAN Transmitter Message Abort Request (CANTARQ)
189 *
190 * @{
191 */
192
193#define TARQ_ABTRQ2              (1 << 2)
194#define TARQ_ABTRQ1              (1 << 1)
195#define TARQ_ABTRQ0              (1 << 0)
196
197/** @} */
198
199/**
200 * @name MSCAN Transmitter Message Abort Acknoledge (CANTAAK)
201 *
202 * @{
203 */
204
205#define TAAK_ABTRQ2              (1 << 2)
206#define TAAK_ABTRQ1              (1 << 1)
207#define TAAK_ABTRQ0              (1 << 0)
208
209/** @} */
210
211/**
212 * @name MSCAN Transmit Buffer Selection (CANBSEL)
213 *
214 * @{
215 */
216
217#define BSEL_TX2                 (1 << 2)
218#define BSEL_TX1                 (1 << 1)
219#define BSEL_TX0                 (1 << 0)
220
221/** @} */
222
223/**
224 * @name MSCAN ID Acceptance Control Register (CANIDAC)
225 *
226 * @{
227 */
228
229#define IDAC_IDAM1               (1 << 5)
230#define IDAC_IDAM0               (1 << 4)
231#define IDAC_IDAM                (IDAC_IDAM1 | IDAC_IDAM0)
232#define IDAC_IDHIT( idac)        ((idac) & 0x7)
233
234/** @} */
235
236/**
237 * @brief MSCAN registers.
238 */
239typedef struct mpc5200_mscan mscan;
240
241/**
242 * @brief MSCAN context that has to be saved throughout the initialization
243 * mode.
244 */
245typedef struct {
246  uint8_t ctl0;
247  uint8_t rier;
248  uint8_t tier;
249} mscan_context;
250
251bool mscan_enable( mscan *m, unsigned bit_rate);
252
253void mscan_disable( mscan *m);
254
255void mscan_interrupts_disable( mscan *m);
256
257bool mscan_set_bit_rate( mscan *m, unsigned bit_rate);
258
259void mscan_initialization_mode_enter( mscan *m, mscan_context *context);
260
261void mscan_initialization_mode_leave( mscan *m, const mscan_context *context);
262
263void mscan_sleep_mode_enter( mscan *m);
264
265void mscan_sleep_mode_leave( mscan *m);
266
267volatile uint8_t *mscan_id_acceptance_register( mscan *m, unsigned i);
268
269volatile uint8_t *mscan_id_mask_register( mscan *m, unsigned i);
270
271unsigned mscan_filter_number( mscan *m);
272
273bool mscan_set_filter_number( mscan *m, unsigned number);
274
275bool mscan_filter_operation( mscan *m, bool set, unsigned index, uint32_t *id, uint32_t *mask);
276
277void mscan_filter_clear( mscan *m);
278
279void mscan_get_error_counters( mscan *m, unsigned *rec, unsigned *tec);
280
281/** @} */
282
283#endif /* LIBBSP_MSCAN_BASE_H */
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