source: rtems/c/src/lib/libbsp/powerpc/gen5200/include/mscan-base.h @ 0e27119

4.11
Last change on this file since 0e27119 was 0e27119, checked in by Joel Sherrill <joel.sherrill@…>, on Oct 11, 2012 at 8:52:18 PM

Use proper 3 line form of license text

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1/**
2 * @file
3 *
4 * @ingroup m
5 *
6 * @brief MSCAN register definitions and support functions.
7 */
8
9/*
10 * Copyright (c) 2008
11 * Embedded Brains GmbH
12 * Obere Lagerstr. 30
13 * D-82178 Puchheim
14 * Germany
15 * rtems@embedded-brains.de
16 *
17 * The license and distribution terms for this file may be
18 * found in the file LICENSE in this distribution or at
19 * http://www.rtems.com/license/LICENSE.
20 */
21
22#ifndef LIBBSP_MSCAN_BASE_H
23#define LIBBSP_MSCAN_BASE_H
24
25#include <stdbool.h>
26
27#include <bsp/mpc5200.h>
28
29/**
30 * @defgroup m MSCAN
31 *
32 * @{
33 */
34
35#define MSCAN_BIT_RATE_MIN 10000
36
37#define MSCAN_BIT_RATE_MAX 1000000
38
39#define MSCAN_BIT_RATE_DEFAULT 125000
40
41#define MSCAN_FILTER_NUMBER_MIN 0
42
43#define MSCAN_FILTER_NUMBER_2 2
44
45#define MSCAN_FILTER_NUMBER_4 4
46
47#define MSCAN_FILTER_NUMBER_MAX 8
48
49#define MSCAN_FILTER_ID_DEFAULT 0U
50
51#define MSCAN_FILTER_MASK_DEFAULT 0xffffffffU
52
53#define MSCAN_TRANSMIT_BUFFER_NUMBER 3
54
55/**
56 * @name MSCAN Control Register 0 (CANCTL0)
57 *
58 * @{
59 */
60
61#define CTL0_RXFRM               (1 << 7)
62#define CTL0_RXACT               (1 << 6)
63#define CTL0_CSWAI               (1 << 5)
64#define CTL0_SYNCH               (1 << 4)
65#define CTL0_TIME                (1 << 3)
66#define CTL0_WUPE                (1 << 2)
67#define CTL0_SLPRQ               (1 << 1)
68#define CTL0_INITRQ              (1 << 0)
69
70/** @} */
71
72/**
73 * @name MSCAN Control Register 1 (CANCTL1)
74 *
75 * @{
76 */
77
78#define CTL1_CANE                (1 << 7)
79#define CTL1_CLKSRC              (1 << 6)
80#define CTL1_LOOPB               (1 << 5)
81#define CTL1_LISTEN              (1 << 4)
82#define CTL1_WUPM                (1 << 2)
83#define CTL1_SLPAK               (1 << 1)
84#define CTL1_INITAK              (1 << 0)
85
86/** @} */
87
88/**
89 * @name MSCAN Bus Timing Register 0 (CANBTR0)
90 *
91 * @{
92 */
93
94#define BTR0_SJW_MASK            0xc0
95#define BTR0_BRP_MASK            0x3f
96
97#define BTR0_SJW( btr0)          ((btr0) << 6)
98#define BTR0_BRP( btr0)          ((btr0) << 0)
99
100#define BTR0_GET_SJW( btr0)      (((btr0) & BTR0_SJW_MASK) >> 6)
101#define BTR0_GET_BRP( btr0)      (((btr0) & BTR0_BRP_MASK) >> 0)
102
103/** @} */
104
105/**
106 * @name MSCAN Bus Timing Register 1 (CANBTR1)
107 *
108 * @{
109 */
110
111#define BTR1_SAMP_MASK           0x80
112#define BTR1_TSEG1_MASK          0x0f
113#define BTR1_TSEG2_MASK          0x70
114
115#define BTR1_SAMP                (1 << 7)
116#define BTR1_TSEG1( btr1)        ((btr1) << 0)
117#define BTR1_TSEG2( btr1)        ((btr1) << 4)
118
119#define BTR1_GET_TSEG1( btr0)    (((btr0) & BTR1_TSEG1_MASK) >> 0)
120#define BTR1_GET_TSEG2( btr0)    (((btr0) & BTR1_TSEG2_MASK) >> 4)
121
122/** @} */
123
124/**
125 * @name MSCAN Receiver Flag Register (CANRFLG)
126 *
127 * @{
128 */
129
130#define RFLG_WUPIF               (1 << 7)
131#define RFLG_CSCIF               (1 << 6)
132#define RFLG_RSTAT_MASK          (3 << 4)
133#define RFLG_RSTAT_OK            (0 << 4)
134#define RFLG_RSTAT_WRN           (1 << 4)
135#define RFLG_RSTAT_ERR           (2 << 4)
136#define RFLG_RSTAT_OFF           (3 << 4)
137#define RFLG_TSTAT_MASK          (3 << 2)
138#define RFLG_TSTAT_OK            (0 << 2)
139#define RFLG_TSTAT_WRN           (1 << 2)
140#define RFLG_TSTAT_ERR           (2 << 2)
141#define RFLG_TSTAT_OFF           (3 << 2)
142#define RFLG_OVRIF               (1 << 1)
143#define RFLG_RXF                 (1 << 0)
144#define RFLG_GET_RX_STATE(rflg)  (((rflg) >> 4) & 0x03)
145#define RFLG_GET_TX_STATE(rflg)  (((rflg) >> 2) & 0x03)
146
147/** @} */
148
149/**
150 * @name MSCAN Receiver Interrupt Enable Register (CANRIER)
151 *
152 * @{
153 */
154
155#define RIER_WUPIE               (1 << 7)
156#define RIER_CSCIE               (1 << 6)
157#define RIER_RSTAT(rier)         ((rier) << 4)
158#define RIER_TSTAT(rier)         ((rier) << 2)
159#define RIER_OVRIE               (1 << 1)
160#define RIER_RXFIE               (1 << 0)
161
162/** @} */
163
164/**
165 * @name MSCAN Transmitter Flag Register (CANTFLG)
166 *
167 * @{
168 */
169
170#define TFLG_TXE2                (1 << 2)
171#define TFLG_TXE1                (1 << 1)
172#define TFLG_TXE0                (1 << 0)
173
174/** @} */
175
176/**
177 * @name MSCAN Transmitter Interrupt Enable Register (CANTIER)
178 *
179 * @{
180 */
181
182#define TIER_TXEI2               (1 << 2)
183#define TIER_TXEI1               (1 << 1)
184#define TIER_TXEI0               (1 << 0)
185
186/** @} */
187
188/**
189 * @name MSCAN Transmitter Message Abort Request (CANTARQ)
190 *
191 * @{
192 */
193
194#define TARQ_ABTRQ2              (1 << 2)
195#define TARQ_ABTRQ1              (1 << 1)
196#define TARQ_ABTRQ0              (1 << 0)
197
198/** @} */
199
200/**
201 * @name MSCAN Transmitter Message Abort Acknoledge (CANTAAK)
202 *
203 * @{
204 */
205
206#define TAAK_ABTRQ2              (1 << 2)
207#define TAAK_ABTRQ1              (1 << 1)
208#define TAAK_ABTRQ0              (1 << 0)
209
210/** @} */
211
212/**
213 * @name MSCAN Transmit Buffer Selection (CANBSEL)
214 *
215 * @{
216 */
217
218#define BSEL_TX2                 (1 << 2)
219#define BSEL_TX1                 (1 << 1)
220#define BSEL_TX0                 (1 << 0)
221
222/** @} */
223
224/**
225 * @name MSCAN ID Acceptance Control Register (CANIDAC)
226 *
227 * @{
228 */
229
230#define IDAC_IDAM1               (1 << 5)
231#define IDAC_IDAM0               (1 << 4)
232#define IDAC_IDAM                (IDAC_IDAM1 | IDAC_IDAM0)
233#define IDAC_IDHIT( idac)        ((idac) & 0x7)
234
235/** @} */
236
237/**
238 * @brief MSCAN registers.
239 */
240typedef struct mpc5200_mscan mscan;
241
242/**
243 * @brief MSCAN context that has to be saved throughout the initialization
244 * mode.
245 */
246typedef struct {
247  uint8_t ctl0;
248  uint8_t rier;
249  uint8_t tier;
250} mscan_context;
251
252bool mscan_enable( volatile mscan *m, unsigned bit_rate);
253
254void mscan_disable( volatile mscan *m);
255
256void mscan_interrupts_disable( volatile mscan *m);
257
258bool mscan_set_bit_rate( volatile mscan *m, unsigned bit_rate);
259
260void mscan_initialization_mode_enter( volatile mscan *m, mscan_context *context);
261
262void mscan_initialization_mode_leave( volatile mscan *m, const mscan_context *context);
263
264void mscan_sleep_mode_enter( volatile mscan *m);
265
266void mscan_sleep_mode_leave( volatile mscan *m);
267
268volatile uint8_t *mscan_id_acceptance_register( volatile mscan *m, unsigned i);
269
270volatile uint8_t *mscan_id_mask_register( volatile mscan *m, unsigned i);
271
272unsigned mscan_filter_number( volatile mscan *m);
273
274bool mscan_set_filter_number( volatile mscan *m, unsigned number);
275
276bool mscan_filter_operation( volatile mscan *m, bool set, unsigned index, uint32_t *id, uint32_t *mask);
277
278void mscan_filter_clear( volatile mscan *m);
279
280void mscan_get_error_counters( volatile mscan *m, unsigned *rec, unsigned *tec);
281
282/** @} */
283
284#endif /* LIBBSP_MSCAN_BASE_H */
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