1 | /*===============================================================*\ |
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2 | | Project: RTEMS generic MPC5200 BSP | |
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3 | +-----------------------------------------------------------------+ |
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4 | | Partially based on the code references which are named below. | |
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5 | | Adaptions, modifications, enhancements and any recent parts of | |
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6 | | the code are: | |
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7 | | Copyright (c) 2005 | |
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8 | | Embedded Brains GmbH | |
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9 | | Obere Lagerstr. 30 | |
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10 | | D-82178 Puchheim | |
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11 | | Germany | |
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12 | | rtems@embedded-brains.de | |
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13 | +-----------------------------------------------------------------+ |
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14 | | The license and distribution terms for this file may be | |
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15 | | found in the file LICENSE in this distribution or at | |
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16 | | | |
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17 | | http://www.rtems.com/license/LICENSE. | |
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18 | | | |
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19 | +-----------------------------------------------------------------+ |
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20 | | this file contains definitions for the mpc5200 hw registers | |
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21 | \*===============================================================*/ |
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22 | |
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23 | #ifndef __MPC5200_h__ |
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24 | #define __MPC5200_h__ |
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25 | |
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26 | /* Additional Harpo Core SPR definitions (603le only) */ |
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27 | #define CSRR0 58 /* Critical Interrupt SRR0 */ |
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28 | #define CSRR1 59 /* Critical Interrupt SRR1 */ |
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29 | #define SPRG4 276 /* Special Purpose Register 4 */ |
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30 | #define SPRG5 277 /* Special Purpose Register 5 */ |
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31 | #define SPRG6 278 /* Special Purpose Register 6 */ |
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32 | #define SPRG7 279 /* Special Purpose Register 7 */ |
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33 | #define IBAT4U 560 /* Instruction BAT #0 Upper/Lower */ |
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34 | #define IBAT4L 561 |
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35 | #define IBAT5U 562 /* Instruction BAT #1 Upper/Lower */ |
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36 | #define IBAT5L 563 |
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37 | #define IBAT6U 564 /* Instruction BAT #2 Upper/Lower */ |
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38 | #define IBAT6L 565 |
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39 | #define IBAT7U 566 /* Instruction BAT #3 Upper/Lower */ |
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40 | #define IBAT7L 567 |
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41 | #define DBAT4U 568 /* Data BAT #0 Upper/Lower */ |
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42 | #define DBAT4L 569 |
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43 | #define DBAT5U 570 /* Data BAT #1 Upper/Lower */ |
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44 | #define DBAT5L 571 |
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45 | #define DBAT6U 572 /* Data BAT #2 Upper/Lower */ |
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46 | #define DBAT6L 573 |
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47 | #define DBAT7U 574 /* Data BAT #3 Upper/Lower */ |
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48 | #define DBAT7L 575 |
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49 | #define DABR2 1000 /* Data Address Breakpoint #2 */ |
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50 | #define DBCR 1001 /* Data Address Breakpoint Control */ |
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51 | #define IBCR 1002 /* Instruction Breakpoint Control */ |
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52 | #define HID1 1009 /* Hardware Implementation 1 */ |
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53 | #define HID2 1011 /* Hardware Implementation 2 */ |
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54 | #define DABR 1013 /* Data Address Breakpoint */ |
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55 | #define IABR2 1018 /* Instruction Breakpoint #2 */ |
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56 | |
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57 | /* |
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58 | * Initial post-reset location of MGT5100 module base address register (MBAR) |
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59 | */ |
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60 | #define MBAR_RESET 0x80000000 |
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61 | |
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62 | /* |
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63 | * Location and size of onchip SRAM (relative to MBAR) |
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64 | */ |
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65 | #define ONCHIP_SRAM_OFFSET 0x8000 |
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66 | #define ONCHIP_SRAM_SIZE 0x4000 |
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67 | |
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68 | #ifndef ASM |
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69 | #include <rtems.h> |
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70 | |
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71 | #ifdef __cplusplus |
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72 | extern "C" { |
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73 | #endif |
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74 | |
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75 | #define MPC5200_CAN_NO 2 |
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76 | #define MPC5200_PSC_NO 6 |
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77 | /* XXX: there are only 6 PSCs, but PSC6 has an extra register gap |
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78 | * from PSC5, therefore we instantiate seven(!) PSC register sets |
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79 | */ |
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80 | #define MPC5200_PSC_REG_SETS 7 |
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81 | |
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82 | #define MPC5200_GPT_NO 8 |
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83 | #define MPC5200_SLT_NO 2 |
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84 | |
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85 | /* |
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86 | * Bit fields for FEC interrupts, ievent and imask above. |
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87 | */ |
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88 | #define FEC_INTR_HBERR 0x80000000 /* heartbeat error */ |
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89 | #define FEC_INTR_BABR 0x40000000 /* babbling receive error */ |
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90 | #define FEC_INTR_BABT 0x20000000 /* babbling transmit error */ |
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91 | #define FEC_INTR_GRA 0x10000000 /* graceful stop complete */ |
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92 | #define FEC_INTR_TFINT 0x08000000 /* transmit frame interrupt */ |
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93 | /* 0x04000000 reserved */ |
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94 | /* 0x02000000 reserved */ |
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95 | /* 0x01000000 reserved */ |
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96 | #define FEC_INTR_MII 0x00800000 /* MII interrupt */ |
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97 | /* 0x00400000 reserved */ |
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98 | #define FEC_INTR_LATE_COL 0x00200000 /* late collision */ |
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99 | #define FEC_INTR_COL_RETRY 0x00100000 /* collision retry limit */ |
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100 | #define FEC_INTR_XFIFO_UN 0x00080000 /* transmit FIFO error */ |
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101 | #define FEC_INTR_XFIFO_ERR 0x00040000 /* transmit FIFO error */ |
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102 | #define FEC_INTR_RFIFO_ERR 0x00020000 /* receive FIFO error */ |
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103 | /* 0x00010000 reserved */ |
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104 | /* 0x0000ffff reserved */ |
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105 | #define FEC_INTR_HBEEN FEC_INTR_HBERR |
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106 | #define FEC_INTR_BREN FEC_INTR_BABR |
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107 | #define FEC_INTR_BTEN FEC_INTR_BABT |
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108 | #define FEC_INTR_GRAEN FEC_INTR_GRA |
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109 | #define FEC_INTR_TFINTEN FEC_INTR_TFINT |
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110 | #define FEC_INTR_MIIEN FEC_INTR_MII |
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111 | #define FEC_INTR_LCEN FEC_INTR_LATE_COL |
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112 | #define FEC_INTR_CRLEN FEC_INTR_COL_RETRY |
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113 | #define FEC_INTR_XFUNEN FEC_INTR_XFIFO_UN |
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114 | #define FEC_INTR_XFERREN FEC_INTR_XFIFO_ERR |
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115 | #define FEC_INTR_RFERREN FEC_INTR_RFIFO_ERR |
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116 | #define FEC_INTR_CLEAR_ALL 0xffffffff /* clear all interrupt events */ |
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117 | #define FEC_INTR_MASK_ALL 0x00000000 /* mask all interrupt events */ |
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118 | |
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119 | /* |
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120 | * Bit fields for FEC ethernet control, ecntrl above. |
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121 | */ |
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122 | #define FEC_ECNTRL_TAG 0xf0000000 /* TBUS tag bits */ |
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123 | /* 0x08000000 reserved */ |
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124 | #define FEC_ECNTRL_TESTMD 0x04000000 /* test mode */ |
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125 | /* 0x03fffff8 reserved */ |
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126 | #define FEC_ECNTRL_OE 0x00000004 /* FEC output enable */ |
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127 | #define FEC_ECNTRL_EN 0x00000002 /* ethernet enable */ |
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128 | #define FEC_ECNTRL_RESET 0x00000001 /* ethernet controller reset */ |
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129 | |
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130 | /* |
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131 | * Bit fields for FEC receive control, r_cntrl above. |
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132 | */ |
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133 | /* 0xf1000000 reserved */ |
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134 | #define FEC_RCNTRL_MAX_FL 0x07ff0000 /* maximum frame length */ |
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135 | #define FEC_RCNTRL_MAX_FL_SHIFT 16 |
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136 | /* 0x0000ffc0 reserved */ |
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137 | #define FEC_RCNTRL_FCE 0x00000020 /* flow control enable */ |
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138 | #define FEC_RCNTRL_BC_REJ 0x00000010 /* broadcast frame reject */ |
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139 | #define FEC_RCNTRL_PROM 0x00000008 /* promiscuous mode */ |
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140 | #define FEC_RCNTRL_MII_MODE 0x00000004 /* select 18-wire (MII) mode */ |
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141 | #define FEC_RCNTRL_DRT 0x00000002 /* disable receive on transmit */ |
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142 | #define FEC_RCNTRL_LOOP 0x00000001 /* internal loopback */ |
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143 | |
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144 | /* |
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145 | * Bit fields for FEC transmit control, x_cntrl above. |
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146 | */ |
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147 | /* 0xffffffe0 reserved */ |
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148 | #define FEC_XCNTRL_RFC_PAUS 0x00000010 /* FDX flow control pause rx */ |
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149 | #define FEC_XCNTRL_TFC_PAUS 0x00000008 /* assert a PAUSE frame */ |
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150 | #define FEC_XCNTRL_FDEN 0x00000004 /* full duplex enable */ |
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151 | #define FEC_XCNTRL_HBC 0x00000002 /* heartbeat control */ |
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152 | #define FEC_XCNTRL_GTS 0x00000001 /* graceful transmit stop */ |
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153 | |
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154 | /* |
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155 | * Bit fields for FEC transmit status, x_status above. |
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156 | */ |
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157 | /* 0xfc000000 reserved */ |
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158 | #define FEC_XSTAT_DEF 0x02000000 /* defer */ |
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159 | #define FEC_XSTAT_HB 0x01000000 /* heartbeat error */ |
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160 | #define FEC_XSTAT_LC 0x00800000 /* late collision */ |
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161 | #define FEC_XSTAT_RL 0x00400000 /* retry limit */ |
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162 | #define FEC_XSTAT_RC 0x003c0000 /* retry count */ |
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163 | #define FEC_XSTAT_UN 0x00020000 /* underrun */ |
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164 | #define FEX_XSTAT_CSL 0x00010000 /* carrier sense lost */ |
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165 | /* 0x0000ffff reserved */ |
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166 | |
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167 | /* |
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168 | * Bit fields for FEC transmit FIFO watermark, x_wmrk above. |
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169 | */ |
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170 | #define FEC_XWMRK_64 0x00000000 /* 64 bytes written to TxFIFO */ |
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171 | #define FEC_XWMRK_128 0x00000001 /* 128 bytes written to TxFIFO */ |
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172 | #define FEC_XWMRK_192 0x00000002 /* 192 bytes written to TxFIFO */ |
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173 | #define FEC_XWMRK_256 0x00000003 /* 256 bytes written to TxFIFO */ |
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174 | #define FEC_XWMRK_320 0x00000004 /* 320 bytes written to TxFIFO */ |
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175 | #define FEC_XWMRK_384 0x00000005 /* 384 bytes written to TxFIFO */ |
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176 | #define FEC_XWMRK_448 0x00000006 /* 448 bytes written to TxFIFO */ |
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177 | #define FEC_XWMRK_512 0x00000007 /* 512 bytes written to TxFIFO */ |
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178 | #define FEC_XWMRK_576 0x00000008 /* 576 bytes written to TxFIFO */ |
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179 | #define FEC_XWMRK_640 0x00000009 /* 640 bytes written to TxFIFO */ |
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180 | #define FEC_XWMRK_704 0x0000000a /* 704 bytes written to TxFIFO */ |
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181 | #define FEC_XWMRK_768 0x0000000b /* 768 bytes written to TxFIFO */ |
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182 | #define FEC_XWMRK_832 0x0000000c /* 832 bytes written to TxFIFO */ |
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183 | #define FEC_XWMRK_896 0x0000000d /* 896 bytes written to TxFIFO */ |
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184 | #define FEC_XWMRK_960 0x0000000e /* 960 bytes written to TxFIFO */ |
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185 | #define FEC_XWMRK_1024 0x0000000f /* 1024 bytes written to TxFIFO */ |
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186 | |
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187 | /* |
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188 | * Bit fields for FEC transmit finite state machine. |
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189 | */ |
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190 | /* 0xfc000000 reserved */ |
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191 | #define FEC_FSM_CRC 0x02000000 /* append CRC (typical use) */ |
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192 | #define FEC_FSM_ENFSM 0x01000000 /* enable CRC FSM (typical use) */ |
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193 | /* 0x00ffffff reserved */ |
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194 | |
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195 | /* |
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196 | * Bit fields for FEC FIFOs, rfifo_status, rfifo_cntrl, tfifo_status |
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197 | * and tfifo_cntrl. |
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198 | */ |
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199 | #define FEC_FIFO_STAT_IP 0x80000000 /* illegal pointer, sticky */ |
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200 | /* 0x70000000 reserved */ |
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201 | #define FEC_FIFO_STAT_FRAME 0x0f000000 /* frame indicator */ |
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202 | #define FEC_FIFO_STAT_FAE 0x00800000 /* frame accept error */ |
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203 | #define FEC_FIFO_STAT_RXW 0x00400000 /* receive wait condition */ |
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204 | #define FEC_FIFO_STAT_UF 0x00200000 /* underflow */ |
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205 | #define FEC_FIFO_STAT_OF 0x00100000 /* overflow */ |
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206 | #define FEC_FIFO_STAT_FR 0x00080000 /* frame ready, read-only */ |
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207 | #define FEC_FIFO_STAT_FULL 0x00040000 /* full alarm, read-only */ |
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208 | #define FEC_FIFO_STAT_ALARM 0x00020000 /* fifo alarm */ |
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209 | #define FEC_FIFO_STAT_EMPTY 0x00010000 /* empty, read-only */ |
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210 | /* 0x0000ffff reserved */ |
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211 | #define FEC_FIFO_STAT_ERROR ( FEC_FIFO_STAT_IP \ |
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212 | | FEC_FIFO_STAT_FAE \ |
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213 | | FEC_FIFO_STAT_RXW \ |
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214 | | FEC_FIFO_STAT_UF \ |
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215 | | FEC_FIFO_STAT_OF \ |
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216 | ) |
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217 | |
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218 | /* 0x80000000 reserved */ |
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219 | #define FEC_FIFO_CNTRL_WCTL 0x40000000 /* write control */ |
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220 | #define FEC_FIFO_CNTRL_WFR 0x20000000 /* write frame */ |
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221 | /* 0x10000000 reserved */ |
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222 | #define FEC_FIFO_CNTRL_FRAME 0x08000000 /* frame mode enable */ |
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223 | #define FEC_FIFO_CNTRL_GR 0x07000000 /* last transfer granularity */ |
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224 | #define FEC_FIFO_CNTRL_GR_SHIFT 24 |
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225 | #define FEC_FIFO_CNTRL_IP_MASK 0x00800000 /* illegal pointer mask */ |
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226 | #define FEC_FIFO_CNTRL_FAE_MASK 0x00400000 /* frame accept mask */ |
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227 | #define FEC_FIFO_CNTRL_RXW_MASK 0x00200000 /* receive wait mask */ |
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228 | #define FEC_FIFO_CNTRL_UF_MASK 0x00100000 /* underflow mask */ |
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229 | #define FEC_FIFO_CNTRL_OF_MASK 0x00080000 /* overflow mask */ |
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230 | /* 0x0007ffff reserved */ |
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231 | |
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232 | /* |
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233 | ************************************************************************* |
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234 | * MPC5x00 internal register memory map * |
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235 | ************************************************************************* |
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236 | */ |
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237 | typedef struct mpc5200_ |
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238 | { |
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239 | /* |
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240 | * memory map registers (MBAR + 0) |
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241 | */ |
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242 | volatile uint8_t mm[0x80]; |
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243 | |
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244 | /* |
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245 | * arbiter registers (processor bus) (MBAR + 0x80) |
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246 | */ |
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247 | volatile uint8_t arb[0x80]; |
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248 | |
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249 | /* |
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250 | * SDRAM memory controller registers (MBAR + 0x100) |
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251 | */ |
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252 | volatile uint8_t mc[0x100]; |
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253 | |
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254 | /* |
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255 | * clock distribution module registers (MBAR + 0x200) |
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256 | */ |
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257 | volatile uint8_t cdm[0x100]; |
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258 | |
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259 | /* |
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260 | * chip selct controller registers(MBAR + 0x300) |
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261 | */ |
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262 | volatile uint8_t csc[0x100]; |
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263 | |
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264 | /* |
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265 | * SmartComm timer registers (MBAR + 0x400) |
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266 | */ |
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267 | volatile uint8_t sct[0x100]; |
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268 | |
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269 | /* |
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270 | * interrupt controller registers (MBAR + 0x500) |
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271 | */ |
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272 | volatile uint32_t per_mask; /* + 0x00 */ |
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273 | volatile uint32_t per_pri_1; /* + 0x04 */ |
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274 | volatile uint32_t per_pri_2; /* + 0x08 */ |
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275 | volatile uint32_t per_pri_3; /* + 0x0C */ |
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276 | volatile uint32_t ext_en_type; /* + 0x10 */ |
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277 | volatile uint32_t crit_pri_main_mask;/* + 0x14 */ |
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278 | volatile uint32_t main_pri_1; /* + 0x18 */ |
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279 | volatile uint32_t main_pri_2; /* + 0x1C */ |
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280 | volatile uint32_t res1; /* + 0x20 */ |
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281 | volatile uint32_t pmce; /* + 0x24 */ |
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282 | volatile uint32_t csa; /* + 0x28 */ |
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283 | volatile uint32_t msa; /* + 0x2C */ |
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284 | volatile uint32_t psa; /* + 0x30 */ |
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285 | volatile uint32_t res2; /* + 0x34 */ |
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286 | volatile uint32_t psa_be; /* + 0x38 */ |
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287 | volatile uint8_t res3[0xC4]; /* + 0x3C */ |
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288 | |
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289 | /* |
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290 | * general pupose timer registers (MBAR + 0x600/+0x610/+0x620/+0x630/+0x640/+0x650/+0x660/+0x670) |
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291 | */ |
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292 | struct mpc5200_gpt |
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293 | { |
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294 | volatile uint32_t emsel; /* + 0x00 */ |
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295 | volatile uint32_t count_in; /* + 0x04 */ |
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296 | volatile uint32_t pwm_conf; /* + 0x08 */ |
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297 | volatile uint32_t status; /* + 0x0C */ |
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298 | } gpt[MPC5200_GPT_NO]; |
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299 | |
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300 | #define GPT_STATUS_RESET 0x0000000F |
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301 | #define GPT_STATUS_TEXP (1 << 3) |
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302 | #define GPT_STATUS_PIN (1 << 8) |
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303 | #define GPT_EMSEL_GPIO_DIR (2 << 4) |
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304 | #define GPT_EMSEL_GPIO_OUT (1 << 4) |
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305 | #define GPT_EMSEL_GPIO_OUT_HIGH (3 << 4) |
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306 | #define GPT_EMSEL_TIMER_MS_GPIO (4 << 0) |
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307 | #define GPT_EMSEL_GPIO_IN (0 << 0) |
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308 | #define GPT_EMSEL_CE (1 << 12) |
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309 | #define GPT_EMSEL_ST_CONT (1 << 10) |
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310 | #define GPT_EMSEL_INTEN (1 << 8) |
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311 | #define GPT_EMSEL_WDEN (1 << 15) |
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312 | |
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313 | #define GPT0 0 |
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314 | #define GPT1 1 |
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315 | #define GPT2 2 |
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316 | #define GPT3 3 |
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317 | #define GPT4 4 |
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318 | #define GPT5 5 |
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319 | #define GPT6 6 |
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320 | #define GPT7 7 |
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321 | |
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322 | volatile uint8_t gpt_res[0x80]; |
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323 | |
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324 | /* |
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325 | * slice time registers (MBAR + 0x700/+0x710) |
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326 | */ |
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327 | struct mpc5200_slt |
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328 | { |
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329 | volatile uint32_t tcr; /* + 0x00 */ |
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330 | volatile uint32_t cntrl; /* + 0x04 */ |
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331 | volatile uint32_t cvr; /* + 0x08 */ |
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332 | volatile uint32_t tsr; /* + 0x0C */ |
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333 | } slt[MPC5200_SLT_NO]; |
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334 | |
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335 | volatile uint8_t slt_res[0xE0]; |
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336 | |
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337 | /* |
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338 | * real time clock registers (MBAR + 0x800) |
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339 | */ |
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340 | volatile uint8_t rtc[0x100]; |
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341 | |
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342 | |
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343 | /* |
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344 | * MSCAN registers (MBAR + 0x900 /+0x980) |
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345 | */ |
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346 | struct mpc5200_mscan |
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347 | { |
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348 | volatile uint8_t ctl0; /* + 0x0 */ |
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349 | volatile uint8_t ctl1; /* + 0x1 */ |
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350 | volatile uint8_t res1; /* + 0x2 */ |
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351 | volatile uint8_t res2; /* + 0x3 */ |
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352 | volatile uint8_t btr0; /* + 0x4 */ |
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353 | volatile uint8_t btr1; /* + 0x5 */ |
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354 | volatile uint8_t res3; /* + 0x6 */ |
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355 | volatile uint8_t res4; /* + 0x7 */ |
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356 | volatile uint8_t rflg; /* + 0x8 */ |
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357 | volatile uint8_t rier; /* + 0x9 */ |
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358 | volatile uint8_t res5; /* + 0xA */ |
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359 | volatile uint8_t res6; /* + 0xB */ |
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360 | volatile uint8_t tflg; /* + 0xC */ |
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361 | volatile uint8_t tier; /* + 0xD */ |
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362 | volatile uint8_t res7; /* + 0xE */ |
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363 | volatile uint8_t res8; /* + 0xF */ |
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364 | volatile uint8_t tarq; /* + 0x10 */ |
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365 | volatile uint8_t taak; /* + 0x11 */ |
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366 | volatile uint8_t res9; /* + 0x12 */ |
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367 | volatile uint8_t res10; /* + 0x13 */ |
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368 | volatile uint8_t bsel; /* + 0x14 */ |
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369 | volatile uint8_t idac; /* + 0x15 */ |
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370 | volatile uint8_t res11; /* + 0x16 */ |
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371 | volatile uint8_t res12; /* + 0x17 */ |
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372 | volatile uint8_t res13; /* + 0x18 */ |
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373 | volatile uint8_t res14; /* + 0x19 */ |
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374 | volatile uint8_t res15; /* + 0x1A */ |
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375 | volatile uint8_t res16; /* + 0x1B */ |
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376 | volatile uint8_t rxerr; /* + 0x1C */ |
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377 | volatile uint8_t txerr; /* + 0x1D */ |
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378 | volatile uint8_t res17; /* + 0x1E */ |
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379 | volatile uint8_t res18; /* + 0x1F */ |
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380 | volatile uint8_t idar0; /* + 0x20 */ |
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381 | volatile uint8_t idar1; /* + 0x21 */ |
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382 | volatile uint8_t res19; /* + 0x22 */ |
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383 | volatile uint8_t res20; /* + 0x23 */ |
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384 | volatile uint8_t idar2; /* + 0x24 */ |
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385 | volatile uint8_t idar3; /* + 0x25 */ |
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386 | volatile uint8_t res21; /* + 0x26 */ |
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387 | volatile uint8_t res22; /* + 0x27 */ |
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388 | volatile uint8_t idmr0; /* + 0x28 */ |
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389 | volatile uint8_t idmr1; /* + 0x29 */ |
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390 | volatile uint8_t res23; /* + 0x2A */ |
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391 | volatile uint8_t res24; /* + 0x2B */ |
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392 | volatile uint8_t idmr2; /* + 0x2C */ |
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393 | volatile uint8_t idmr3; /* + 0x2D */ |
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394 | volatile uint8_t res25; /* + 0x2E */ |
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395 | volatile uint8_t res26; /* + 0x2F */ |
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396 | volatile uint8_t idar4; /* + 0x30 */ |
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397 | volatile uint8_t idar5; /* + 0x31 */ |
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398 | volatile uint8_t res27; /* + 0x32 */ |
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399 | volatile uint8_t res28; /* + 0x33 */ |
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400 | volatile uint8_t idar6; /* + 0x34 */ |
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401 | volatile uint8_t idar7; /* + 0x35 */ |
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402 | volatile uint8_t res29; /* + 0x36 */ |
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403 | volatile uint8_t res30; /* + 0x37 */ |
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404 | volatile uint8_t idmr4; /* + 0x38 */ |
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405 | volatile uint8_t idmr5; /* + 0x39 */ |
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406 | volatile uint8_t res31; /* + 0x3A */ |
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407 | volatile uint8_t res32; /* + 0x3B */ |
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408 | volatile uint8_t idmr6; /* + 0x3C */ |
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409 | volatile uint8_t idmr7; /* + 0x3D */ |
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410 | volatile uint8_t res33; /* + 0x3E */ |
---|
411 | volatile uint8_t res34; /* + 0x3F */ |
---|
412 | volatile uint8_t rxidr0; /* + 0x40 */ |
---|
413 | volatile uint8_t rxidr1; /* + 0x41 */ |
---|
414 | volatile uint8_t res35; /* + 0x42 */ |
---|
415 | volatile uint8_t res36; /* + 0x43 */ |
---|
416 | volatile uint8_t rxidr2; /* + 0x44 */ |
---|
417 | volatile uint8_t rxidr3; /* + 0x45 */ |
---|
418 | volatile uint8_t res37; /* + 0x46 */ |
---|
419 | volatile uint8_t res38; /* + 0x47 */ |
---|
420 | volatile uint8_t rxdsr0; /* + 0x48 */ |
---|
421 | volatile uint8_t rxdsr1; /* + 0x49 */ |
---|
422 | volatile uint8_t res39; /* + 0x4A */ |
---|
423 | volatile uint8_t res40; /* + 0x4B */ |
---|
424 | volatile uint8_t rxdsr2; /* + 0x4C */ |
---|
425 | volatile uint8_t rxdsr3; /* + 0x4D */ |
---|
426 | volatile uint8_t res41; /* + 0x4E */ |
---|
427 | volatile uint8_t res42; /* + 0x4F */ |
---|
428 | volatile uint8_t rxdsr4; /* + 0x50 */ |
---|
429 | volatile uint8_t rxdsr5; /* + 0x51 */ |
---|
430 | volatile uint8_t res43; /* + 0x52 */ |
---|
431 | volatile uint8_t res44; /* + 0x53 */ |
---|
432 | volatile uint8_t rxdsr6; /* + 0x54 */ |
---|
433 | volatile uint8_t rxdsr7; /* + 0x55 */ |
---|
434 | volatile uint8_t res45; /* + 0x56 */ |
---|
435 | volatile uint8_t res46; /* + 0x57 */ |
---|
436 | volatile uint8_t rxdlr; /* + 0x58 */ |
---|
437 | volatile uint8_t res47; /* + 0x59 */ |
---|
438 | volatile uint8_t res48; /* + 0x5A */ |
---|
439 | volatile uint8_t res49; /* + 0x5B */ |
---|
440 | volatile uint8_t rxtimh; /* + 0x5C */ |
---|
441 | volatile uint8_t rxtiml; /* + 0x5D */ |
---|
442 | volatile uint8_t res50; /* + 0x5E */ |
---|
443 | volatile uint8_t res51; /* + 0x5F */ |
---|
444 | volatile uint8_t txidr0; /* + 0x60 */ |
---|
445 | volatile uint8_t txidr1; /* + 0x61 */ |
---|
446 | volatile uint8_t res52; /* + 0x62 */ |
---|
447 | volatile uint8_t res53; /* + 0x63 */ |
---|
448 | volatile uint8_t txidr2; /* + 0x64 */ |
---|
449 | volatile uint8_t txidr3; /* + 0x65 */ |
---|
450 | volatile uint8_t res54; /* + 0x66 */ |
---|
451 | volatile uint8_t res55; /* + 0x67 */ |
---|
452 | volatile uint8_t txdsr0; /* + 0x68 */ |
---|
453 | volatile uint8_t txdsr1; /* + 0x69 */ |
---|
454 | volatile uint8_t res56; /* + 0x6A */ |
---|
455 | volatile uint8_t res57; /* + 0x6B */ |
---|
456 | volatile uint8_t txdsr2; /* + 0x6C */ |
---|
457 | volatile uint8_t txdsr3; /* + 0x6D */ |
---|
458 | volatile uint8_t res58; /* + 0x6E */ |
---|
459 | volatile uint8_t res59; /* + 0x6F */ |
---|
460 | volatile uint8_t txdsr4; /* + 0x70 */ |
---|
461 | volatile uint8_t txdsr5; /* + 0x71 */ |
---|
462 | volatile uint8_t res60; /* + 0x72 */ |
---|
463 | volatile uint8_t res61; /* + 0x73 */ |
---|
464 | volatile uint8_t txdsr6; /* + 0x74 */ |
---|
465 | volatile uint8_t txdsr7; /* + 0x75 */ |
---|
466 | volatile uint8_t res62; /* + 0x76 */ |
---|
467 | volatile uint8_t res63; /* + 0x77 */ |
---|
468 | volatile uint8_t txdlr; /* + 0x78 */ |
---|
469 | volatile uint8_t txtbpr; /* + 0x79 */ |
---|
470 | volatile uint8_t res64; /* + 0x7A */ |
---|
471 | volatile uint8_t res65; /* + 0x7B */ |
---|
472 | volatile uint8_t txtimh; /* + 0x7C */ |
---|
473 | volatile uint8_t txtiml; /* + 0x7D */ |
---|
474 | volatile uint8_t res66; /* + 0x7E */ |
---|
475 | volatile uint8_t res67; /* + 0x7F */ |
---|
476 | } mscan[MPC5200_CAN_NO]; |
---|
477 | |
---|
478 | volatile uint8_t res[0x100]; |
---|
479 | |
---|
480 | /* |
---|
481 | * GPIO standard registers (MBAR + 0xB00) |
---|
482 | */ |
---|
483 | volatile uint32_t gpiopcr; /* + 0x00 */ |
---|
484 | #define GPIO_PCR_CHIP_SELECT_1 0x80000000 |
---|
485 | #define GPIO_PCR_CHIP_ALTS 0x30000000 |
---|
486 | #define GPIO_PCR_CHIP_ALTS_NONE 0x00000000 |
---|
487 | #define GPIO_PCR_CHIP_ALTS_CAN 0x10000000 |
---|
488 | #define GPIO_PCR_CHIP_ALTS_SPI 0x20000000 |
---|
489 | #define GPIO_PCR_CHIP_ALTS_BOTH 0x30000000 |
---|
490 | #define GPIO_PCR_CHIP_SELECT_7 0x08000000 |
---|
491 | #define GPIO_PCR_CHIP_SELECT_6 0x04000000 |
---|
492 | #define GPIO_PCR_CHIP_SELECT_ATA 0x03000000 |
---|
493 | #define GPIO_PCR_CHIP_SELECT_IR_USB_CLK 0x00800000 |
---|
494 | #define GPIO_PCR_IRDA 0x00700000 |
---|
495 | #define GPIO_PCR_ETHERNET 0x000F0000 |
---|
496 | #define GPIO_PCR_PCI_DIS 0x00008000 |
---|
497 | #define GPIO_PCR_USB_SE 0x00004000 |
---|
498 | #define GPIO_PCR_USB_GPIO 0x00003000 |
---|
499 | #define GPIO_PCR_PSC3 0x00000F00 |
---|
500 | #define GPIO_PCR_PSC2 0x00000070 |
---|
501 | #define GPIO_PCR_PSC1 0x00000007 |
---|
502 | |
---|
503 | volatile uint32_t gpiosen; /* + 0x04 */ |
---|
504 | volatile uint32_t gpiosod; /* + 0x08 */ |
---|
505 | volatile uint32_t gpiosdd; /* + 0x0C */ |
---|
506 | volatile uint32_t gpiosdo; /* + 0x10 */ |
---|
507 | volatile uint32_t gpiosdi; /* + 0x14 */ |
---|
508 | volatile uint32_t gpiooe; /* + 0x18 */ |
---|
509 | volatile uint32_t gpioodo; /* + 0x1C */ |
---|
510 | |
---|
511 | volatile uint32_t gpiosie; /* + 0x20 */ |
---|
512 | #define GPIO_SIE_SINT_7_ETH_16_PIN 0x80000000 |
---|
513 | #define GPIO_SIE_SINT_6_ETH_15_PIN 0x40000000 |
---|
514 | #define GPIO_SIE_SINT_5_ETH_14_PIN 0x20000000 |
---|
515 | #define GPIO_SIE_SINT_4_ETH_13_PIN 0x10000000 |
---|
516 | #define GPIO_SIE_SINT_3_USB1_9_PIN 0x08000000 |
---|
517 | #define GPIO_SIE_SINT_2_PSC3_8_PIN 0x04000000 |
---|
518 | #define GPIO_SIE_SINT_1_PSC3_5_PIN 0x02000000 |
---|
519 | #define GPIO_SIE_SINT_0_PSC3_4_PIN 0x01000000 |
---|
520 | |
---|
521 | volatile uint32_t gpiosiod; /* + 0x24 */ |
---|
522 | |
---|
523 | volatile uint32_t gpiosidd; /* + 0x28 */ |
---|
524 | #define GPIO_SIDD_SINT_7_ETH_16_PIN 0x80000000 |
---|
525 | #define GPIO_SIDD_SINT_6_ETH_15_PIN 0x40000000 |
---|
526 | #define GPIO_SIDD_SINT_5_ETH_14_PIN 0x20000000 |
---|
527 | #define GPIO_SIDD_SINT_4_ETH_13_PIN 0x10000000 |
---|
528 | #define GPIO_SIDD_SINT_3_USB1_9_PIN 0x08000000 |
---|
529 | #define GPIO_SIDD_SINT_2_PSC3_8_PIN 0x04000000 |
---|
530 | #define GPIO_SIDD_SINT_1_PSC3_5_PIN 0x02000000 |
---|
531 | #define GPIO_SIDD_SINT_0_PSC3_4_PIN 0x01000000 |
---|
532 | |
---|
533 | volatile uint32_t gpiosido; /* + 0x2C */ |
---|
534 | |
---|
535 | volatile uint32_t gpiosiie; /* + 0x30 */ |
---|
536 | #define GPIO_SIIE_SINT_7_ETH_16_PIN 0x80000000 |
---|
537 | #define GPIO_SIIE_SINT_6_ETH_15_PIN 0x40000000 |
---|
538 | #define GPIO_SIIE_SINT_5_ETH_14_PIN 0x20000000 |
---|
539 | #define GPIO_SIIE_SINT_4_ETH_13_PIN 0x10000000 |
---|
540 | #define GPIO_SIIE_SINT_3_USB1_9_PIN 0x08000000 |
---|
541 | #define GPIO_SIIE_SINT_2_PSC3_8_PIN 0x04000000 |
---|
542 | #define GPIO_SIIE_SINT_1_PSC3_5_PIN 0x02000000 |
---|
543 | #define GPIO_SIIE_SINT_0_PSC3_4_PIN 0x01000000 |
---|
544 | |
---|
545 | volatile uint32_t gpiosiit; /* + 0x34 */ |
---|
546 | #define GPIO_SIIT_SINT_7_ETH_16_PIN_MASK 0xc0000000 |
---|
547 | #define GPIO_SIIT_SINT_6_ETH_15_PIN_MASK 0x30000000 |
---|
548 | #define GPIO_SIIT_SINT_5_ETH_14_PIN_MASK 0x0c000000 |
---|
549 | #define GPIO_SIIT_SINT_4_ETH_13_PIN_MASK 0x03000000 |
---|
550 | #define GPIO_SIIT_SINT_3_USB1_9_PIN_MASK 0x00c00000 |
---|
551 | #define GPIO_SIIT_SINT_2_PSC3_8_PIN_MASK 0x00300000 |
---|
552 | #define GPIO_SIIT_SINT_1_PSC3_5_PIN_MASK 0x000c0000 |
---|
553 | #define GPIO_SIIT_SINT_0_PSC3_4_PIN_MASK 0x00030000 |
---|
554 | |
---|
555 | #define GPIO_SIIT_ON_ANY_TRANSITION 0x00000000 |
---|
556 | #define GPIO_SIIT_ON_RISING_EDGE 0x00000001 |
---|
557 | #define GPIO_SIIT_ON_FALLING_EDGE 0x00000002 |
---|
558 | #define GPIO_SIIT_ON_PULSE 0x00000003 |
---|
559 | |
---|
560 | #define GPIO_SIIT_SINT_7_ETH_16_PIN_SHIFT 16 |
---|
561 | #define GPIO_SIIT_SINT_6_ETH_15_PIN_SHIFT 18 |
---|
562 | #define GPIO_SIIT_SINT_5_ETH_14_PIN_SHIFT 20 |
---|
563 | #define GPIO_SIIT_SINT_4_ETH_13_PIN_SHIFT 22 |
---|
564 | #define GPIO_SIIT_SINT_3_USB1_9_PIN_SHIFT 24 |
---|
565 | #define GPIO_SIIT_SINT_2_PSC3_8_PIN_SHIFT 26 |
---|
566 | #define GPIO_SIIT_SINT_1_PSC3_5_PIN_SHIFT 28 |
---|
567 | #define GPIO_SIIT_SINT_0_PSC3_4_PIN_SHIFT 30 |
---|
568 | |
---|
569 | volatile uint32_t gpiosime; /* + 0x38 */ |
---|
570 | #define GPIO_SIME_MASTER_ENABLE 0x10000000 |
---|
571 | |
---|
572 | volatile uint32_t gpiosist; /* + 0x3C */ |
---|
573 | #define GPIO_SIST_SINT_7_ETH_16_PIN_STATUS 0x80000000 |
---|
574 | #define GPIO_SIST_SINT_6_ETH_15_PIN_STATUS 0x40000000 |
---|
575 | #define GPIO_SIST_SINT_5_ETH_14_PIN_STATUS 0x20000000 |
---|
576 | #define GPIO_SIST_SINT_4_ETH_13_PIN_STATUS 0x10000000 |
---|
577 | #define GPIO_SIST_SINT_3_USB1_9_PIN_STATUS 0x08000000 |
---|
578 | #define GPIO_SIST_SINT_2_PSC3_8_PIN_STATUS 0x04000000 |
---|
579 | #define GPIO_SIST_SINT_1_PSC3_5_PIN_STATUS 0x02000000 |
---|
580 | #define GPIO_SIST_SINT_0_PSC3_4_PIN_STATUS 0x01000000 |
---|
581 | #define GPIO_SIST_SINT_7_ETH_16_PIN_VALUE 0x008000000 |
---|
582 | #define GPIO_SIST_SINT_6_ETH_15_PIN_VALUE 0x00400000 |
---|
583 | #define GPIO_SIST_SINT_5_ETH_14_PIN_VALUE 0x00200000 |
---|
584 | #define GPIO_SIST_SINT_4_ETH_13_PIN_VALUE 0x00100000 |
---|
585 | #define GPIO_SIST_SINT_3_USB1_9_PIN_VALUE 0x00080000 |
---|
586 | #define GPIO_SIST_SINT_2_PSC3_8_PIN_VALUE 0x00040000 |
---|
587 | #define GPIO_SIST_SINT_1_PSC3_5_PIN_VALUE 0x00020000 |
---|
588 | #define GPIO_SIST_SINT_0_PSC3_4_PIN_VALUE 0x00010000 |
---|
589 | |
---|
590 | #define GPIO_SIST_SINT_CLEAR_ALL 0xff000000 |
---|
591 | |
---|
592 | volatile uint8_t res4[0xC0]; |
---|
593 | |
---|
594 | /* |
---|
595 | * GPIO wakeup registers (MBAR + 0xC00) |
---|
596 | */ |
---|
597 | volatile uint32_t gpiowe; /* + 0x00 */ |
---|
598 | volatile uint32_t gpiowod; /* + 0x04 */ |
---|
599 | volatile uint32_t gpiowdd; /* + 0x08 */ |
---|
600 | volatile uint32_t gpiowdo; /* + 0x0C */ |
---|
601 | volatile uint32_t gpiowue; /* + 0x10 */ |
---|
602 | volatile uint32_t gpiowsie; /* + 0x14 */ |
---|
603 | volatile uint32_t gpiowt; /* + 0x18 */ |
---|
604 | volatile uint32_t gpiowme; /* + 0x1C */ |
---|
605 | volatile uint32_t gpiowi; /* + 0x20 */ |
---|
606 | volatile uint32_t gpiows; /* + 0x24 */ |
---|
607 | volatile uint8_t gpiow_res[0xD8]; |
---|
608 | |
---|
609 | /* |
---|
610 | * PPC PCI registers (MBAR + 0xD00) |
---|
611 | */ |
---|
612 | volatile uint8_t ppci[0x100]; |
---|
613 | |
---|
614 | /* |
---|
615 | * consumer infrared registers (MBAR + 0xE00) |
---|
616 | */ |
---|
617 | volatile uint8_t ir[0x100]; |
---|
618 | |
---|
619 | /* |
---|
620 | * serial peripheral interface registers (MBAR + 0xF00) |
---|
621 | */ |
---|
622 | volatile uint8_t spi[0x100]; |
---|
623 | |
---|
624 | /* |
---|
625 | * universal serial bus registers (MBAR + 0x1000) |
---|
626 | */ |
---|
627 | volatile uint8_t usb[0x200]; |
---|
628 | |
---|
629 | /* |
---|
630 | * SmartComm DMA registers (MBAR + 0x1200) |
---|
631 | */ |
---|
632 | volatile uint32_t taskBar; /* + 0x00 sdTpb */ |
---|
633 | volatile uint32_t currentPointer; /* + 0x04 sdMdeComplex */ |
---|
634 | volatile uint32_t endPointer; /* + 0x08 sdMdeComplex */ |
---|
635 | volatile uint32_t variablePointer; /* + 0x0c sdMdeComplex */ |
---|
636 | |
---|
637 | /* |
---|
638 | * The following are Priority Task Decoder (ptd) regs in sdma/rtl_v/sdPtd.v. |
---|
639 | * The ptd register map below is from the smartcomm spec, table 3-2, page 3-54. |
---|
640 | * The spec shows the ptd map as 20 words, but sdPtd.v has only implemented 19. |
---|
641 | * The word commented out below is the one which is not implemented. |
---|
642 | */ |
---|
643 | |
---|
644 | /* volatile uint8_t IntVect; */ /* |
---|
645 | * + 0xXX sdPtd read only |
---|
646 | */ |
---|
647 | |
---|
648 | /* volatile uint8_t res0[3]; */ /* |
---|
649 | * + 0xXX sdPtd read only |
---|
650 | */ |
---|
651 | volatile uint8_t IntVect1; /* + 0x10 sdPtd */ |
---|
652 | volatile uint8_t IntVect2; /* + 0x11 sdPtd */ |
---|
653 | volatile uint16_t PtdCntrl; /* + 0x12 sdPtd */ |
---|
654 | |
---|
655 | volatile uint32_t IntPend; /* + 0x14 sdPtd */ |
---|
656 | volatile uint32_t IntMask; /* + 0x18 sdPtd */ |
---|
657 | |
---|
658 | volatile uint32_t TCR01; /* + 0x1c sdPtd */ |
---|
659 | volatile uint32_t TCR23; /* + 0x20 sdPtd */ |
---|
660 | volatile uint32_t TCR45; /* + 0x24 sdPtd */ |
---|
661 | volatile uint32_t TCR67; /* + 0x28 sdPtd */ |
---|
662 | volatile uint32_t TCR89; /* + 0x2c sdPtd */ |
---|
663 | volatile uint32_t TCRAB; /* + 0x30 sdPtd */ |
---|
664 | volatile uint32_t TCRCD; /* + 0x34 sdPtd */ |
---|
665 | volatile uint32_t TCREF; /* + 0x38 sdPtd */ |
---|
666 | |
---|
667 | volatile uint8_t IPR0; /* + 0x3c sdPtd */ |
---|
668 | volatile uint8_t IPR1; /* + 0x3d sdPtd */ |
---|
669 | volatile uint8_t IPR2; /* + 0x3e sdPtd */ |
---|
670 | volatile uint8_t IPR3; /* + 0x3f sdPtd */ |
---|
671 | volatile uint8_t IPR4; /* + 0x40 sdPtd */ |
---|
672 | volatile uint8_t IPR5; /* + 0x41 sdPtd */ |
---|
673 | volatile uint8_t IPR6; /* + 0x42 sdPtd */ |
---|
674 | volatile uint8_t IPR7; /* + 0x43 sdPtd */ |
---|
675 | volatile uint8_t IPR8; /* + 0x44 sdPtd */ |
---|
676 | volatile uint8_t IPR9; /* + 0x45 sdPtd */ |
---|
677 | volatile uint8_t IPR10; /* + 0x46 sdPtd */ |
---|
678 | volatile uint8_t IPR11; /* + 0x47 sdPtd */ |
---|
679 | volatile uint8_t IPR12; /* + 0x48 sdPtd */ |
---|
680 | volatile uint8_t IPR13; /* + 0x49 sdPtd */ |
---|
681 | volatile uint8_t IPR14; /* + 0x4a sdPtd */ |
---|
682 | volatile uint8_t IPR15; /* + 0x4b sdPtd */ |
---|
683 | volatile uint8_t IPR16; /* + 0x4c sdPtd */ |
---|
684 | volatile uint8_t IPR17; /* + 0x4d sdPtd */ |
---|
685 | volatile uint8_t IPR18; /* + 0x4e sdPtd */ |
---|
686 | volatile uint8_t IPR19; /* + 0x4f sdPtd */ |
---|
687 | volatile uint8_t IPR20; /* + 0x50 sdPtd */ |
---|
688 | volatile uint8_t IPR21; /* + 0x51 sdPtd */ |
---|
689 | volatile uint8_t IPR22; /* + 0x52 sdPtd */ |
---|
690 | volatile uint8_t IPR23; /* + 0x53 sdPtd */ |
---|
691 | volatile uint8_t IPR24; /* + 0x54 sdPtd */ |
---|
692 | volatile uint8_t IPR25; /* + 0x55 sdPtd */ |
---|
693 | volatile uint8_t IPR26; /* + 0x56 sdPtd */ |
---|
694 | volatile uint8_t IPR27; /* + 0x57 sdPtd */ |
---|
695 | volatile uint8_t IPR28; /* + 0x58 sdPtd */ |
---|
696 | volatile uint8_t IPR29; /* + 0x59 sdPtd */ |
---|
697 | volatile uint8_t IPR30; /* + 0x5a sdPtd */ |
---|
698 | volatile uint8_t IPR31; /* + 0x5b sdPtd */ |
---|
699 | |
---|
700 | volatile uint32_t res5; /* reserved */ |
---|
701 | volatile uint32_t res6; /* reserved */ |
---|
702 | volatile uint32_t res7; /* reserved */ |
---|
703 | volatile uint32_t MDEDebug; /* + 0x68 sdMdeComplex */ |
---|
704 | volatile uint32_t ADSDebug; /* + 0x6c sdAdsTop */ |
---|
705 | volatile uint32_t Value1; /* + 0x70 sdDbg */ |
---|
706 | volatile uint32_t Value2; /* + 0x74 sdDbg */ |
---|
707 | volatile uint32_t Control; /* + 0x78 sdDbg */ |
---|
708 | volatile uint32_t Status; /* + 0x7c sdDbg */ |
---|
709 | volatile uint32_t EU00; /* + 0x80 sdMac macer reg */ |
---|
710 | volatile uint32_t EU01; /* + 0x84 sdMac macemr reg */ |
---|
711 | volatile uint32_t EU02; /* + 0x88 unused */ |
---|
712 | volatile uint32_t EU03; /* + 0x8c unused */ |
---|
713 | volatile uint32_t EU04; /* + 0x90 unused */ |
---|
714 | volatile uint32_t EU05; /* + 0x94 unused */ |
---|
715 | volatile uint32_t EU06; /* + 0x98 unused */ |
---|
716 | volatile uint32_t EU07; /* + 0x9c unused */ |
---|
717 | volatile uint32_t EU10; /* + 0xa0 unused */ |
---|
718 | volatile uint32_t EU11; /* + 0xa4 unused */ |
---|
719 | volatile uint32_t EU12; /* + 0xa8 unused */ |
---|
720 | volatile uint32_t EU13; /* + 0xac unused */ |
---|
721 | volatile uint32_t EU14; /* + 0xb0 unused */ |
---|
722 | volatile uint32_t EU15; /* + 0xb4 unused */ |
---|
723 | volatile uint32_t EU16; /* + 0xb8 unused */ |
---|
724 | volatile uint32_t EU17; /* + 0xbc unused */ |
---|
725 | volatile uint32_t EU20; /* + 0xc0 unused */ |
---|
726 | volatile uint32_t EU21; /* + 0xc4 unused */ |
---|
727 | volatile uint32_t EU22; /* + 0xc8 unused */ |
---|
728 | volatile uint32_t EU23; /* + 0xcc unused */ |
---|
729 | volatile uint32_t EU24; /* + 0xd0 unused */ |
---|
730 | volatile uint32_t EU25; /* + 0xd4 unused */ |
---|
731 | volatile uint32_t EU26; /* + 0xd8 unused */ |
---|
732 | volatile uint32_t EU27; /* + 0xdc unused */ |
---|
733 | volatile uint32_t EU30; /* + 0xe0 unused */ |
---|
734 | volatile uint32_t EU31; /* + 0xe4 unused */ |
---|
735 | volatile uint32_t EU32; /* + 0xe8 unused */ |
---|
736 | volatile uint32_t EU33; /* + 0xec unused */ |
---|
737 | volatile uint32_t EU34; /* + 0xf0 unused */ |
---|
738 | volatile uint32_t EU35; /* + 0xf4 unused */ |
---|
739 | volatile uint32_t EU36; /* + 0xf8 unused */ |
---|
740 | volatile uint32_t EU37; /* + 0xfc unused */ |
---|
741 | #if 0 |
---|
742 | volatile uint32_t res8[0x340]; |
---|
743 | #else |
---|
744 | volatile uint8_t res_1300[0xc00]; |
---|
745 | |
---|
746 | volatile uint32_t reserved0; /* MBAR_XLB_ARB + 0x0000 reserved */ |
---|
747 | volatile uint32_t reserved1; /* MBAR_XLB_ARB + 0x0004 reserved */ |
---|
748 | volatile uint32_t reserved2; /* MBAR_XLB_ARB + 0x0008 reserved */ |
---|
749 | volatile uint32_t reserved3; /* MBAR_XLB_ARB + 0x000c reserved */ |
---|
750 | volatile uint32_t reserved4; /* MBAR_XLB_ARB + 0x0010 reserved */ |
---|
751 | volatile uint32_t reserved5; /* MBAR_XLB_ARB + 0x0014 reserved */ |
---|
752 | volatile uint32_t reserved6; /* MBAR_XLB_ARB + 0x0018 reserved */ |
---|
753 | volatile uint32_t reserved7; /* MBAR_XLB_ARB + 0x001c reserved */ |
---|
754 | volatile uint32_t reserved8; /* MBAR_XLB_ARB + 0x0020 reserved */ |
---|
755 | volatile uint32_t reserved9; /* MBAR_XLB_ARB + 0x0024 reserved */ |
---|
756 | volatile uint32_t reserved10; /* MBAR_XLB_ARB + 0x0028 reserved */ |
---|
757 | volatile uint32_t reserved11; /* MBAR_XLB_ARB + 0x002c reserved */ |
---|
758 | volatile uint32_t reserved12; /* MBAR_XLB_ARB + 0x0030 reserved */ |
---|
759 | volatile uint32_t reserved13; /* MBAR_XLB_ARB + 0x0034 reserved */ |
---|
760 | volatile uint32_t reserved14; /* MBAR_XLB_ARB + 0x0038 reserved */ |
---|
761 | volatile uint32_t reserved15; /* MBAR_XLB_ARB + 0x003c reserved */ |
---|
762 | |
---|
763 | volatile uint32_t config; /* MBAR_XLB_ARB + 0x0040 */ |
---|
764 | volatile uint32_t version; /* MBAR_XLB_ARB + 0x0044 read only = 0x0001 */ |
---|
765 | volatile uint32_t xlb_status; /* MBAR_XLB_ARB + 0x0048 */ |
---|
766 | volatile uint32_t int_enable; /* MBAR_XLB_ARB + 0x004c */ |
---|
767 | volatile uint32_t add_capture; /* MBAR_XLB_ARB + 0x0050 read only */ |
---|
768 | volatile uint32_t bus_sig_capture; /* MBAR_XLB_ARB + 0x0054 read only */ |
---|
769 | volatile uint32_t add_time_out; /* MBAR_XLB_ARB + 0x0058 */ |
---|
770 | volatile uint32_t data_time_out; /* MBAR_XLB_ARB + 0x005c */ |
---|
771 | volatile uint32_t bus_time_out; /* MBAR_XLB_ARB + 0x0060 */ |
---|
772 | volatile uint32_t priority_enable; /* MBAR_XLB_ARB + 0x0064 */ |
---|
773 | volatile uint32_t priority; /* MBAR_XLB_ARB + 0x0068 */ |
---|
774 | volatile uint32_t arb_base_addr2; /* MBAR_XLB_ARB + 0x006c */ |
---|
775 | volatile uint32_t snoop_window; /* MBAR_XLB_ARB + 0x0070 */ |
---|
776 | |
---|
777 | volatile uint32_t reserved16; /* MBAR_XLB_ARB + 0x0074 reserved */ |
---|
778 | volatile uint32_t reserved17; /* MBAR_XLB_ARB + 0x0078 reserved */ |
---|
779 | volatile uint32_t reserved18; /* MBAR_XLB_ARB + 0x007c reserved */ |
---|
780 | |
---|
781 | volatile uint32_t control; /* MBAR_XLB_ARB + 0x0080 */ |
---|
782 | volatile uint32_t init_total_count; /* MBAR_XLB_ARB + 0x0084 */ |
---|
783 | volatile uint32_t int_total_count; /* MBAR_XLB_ARB + 0x0088 */ |
---|
784 | |
---|
785 | volatile uint32_t reserved19; /* MBAR_XLB_ARB + 0x008c reserved */ |
---|
786 | |
---|
787 | volatile uint32_t lower_address; /* MBAR_XLB_ARB + 0x0090 */ |
---|
788 | volatile uint32_t higher_address; /* MBAR_XLB_ARB + 0x0094 */ |
---|
789 | volatile uint32_t int_window_count; /* MBAR_XLB_ARB + 0x0098 */ |
---|
790 | volatile uint32_t window_ter_count; /* MBAR_XLB_ARB + 0x009c */ |
---|
791 | volatile uint8_t res_0x1fa0[0x60]; |
---|
792 | |
---|
793 | |
---|
794 | #endif |
---|
795 | /* |
---|
796 | * programmable serial controller 1 (MBAR + 0x2000) |
---|
797 | */ |
---|
798 | |
---|
799 | struct mpc5200_psc |
---|
800 | { |
---|
801 | volatile uint8_t mr; /* +0x00 */ |
---|
802 | volatile uint8_t res1[3]; |
---|
803 | volatile uint16_t sr_csr; /* +0x04 */ |
---|
804 | volatile uint16_t res2[1]; |
---|
805 | volatile uint16_t cr; /* +0x08 */ |
---|
806 | volatile uint16_t res3[1]; |
---|
807 | volatile uint32_t rb_tb; /* +0x0c */ |
---|
808 | volatile uint16_t ipcr_acr; /* +0x10 */ |
---|
809 | volatile uint16_t res4[1]; |
---|
810 | volatile uint16_t isr_imr; /* +0x14 */ |
---|
811 | #define ISR_TX_RDY (1 << 8) |
---|
812 | #define ISR_RX_RDY_FULL (1 << 9) |
---|
813 | #define ISR_RB (1 << 15) |
---|
814 | #define ISR_FE (1 << 14) |
---|
815 | #define ISR_PE (1 << 13) |
---|
816 | #define ISR_OE (1 << 12) |
---|
817 | #define ISR_ERROR (ISR_FE | ISR_PE | ISR_OE) |
---|
818 | |
---|
819 | #define IMR_TX_RDY (1 << 8) |
---|
820 | #define IMR_RX_RDY_FULL (1 << 9) |
---|
821 | volatile uint16_t res5[1]; |
---|
822 | volatile uint8_t ctur; /* +0x18 */ |
---|
823 | volatile uint8_t res6[3]; |
---|
824 | volatile uint8_t ctlr; /* +0x1C */ |
---|
825 | volatile uint8_t res7[0x13]; |
---|
826 | volatile uint8_t ivr; /* +0x30 */ |
---|
827 | volatile uint8_t res8[3]; |
---|
828 | volatile uint8_t ip; /* +0x34 */ |
---|
829 | volatile uint8_t res9[3]; |
---|
830 | volatile uint8_t op1; /* +0x38 */ |
---|
831 | volatile uint8_t res10[3]; |
---|
832 | volatile uint8_t op0; /* +0x3C */ |
---|
833 | volatile uint8_t res11[3]; |
---|
834 | volatile uint8_t sicr; /* +0x40 */ |
---|
835 | volatile uint8_t res12[0x17]; |
---|
836 | volatile uint16_t rfnum; /* +0x58 */ |
---|
837 | volatile uint16_t res13[1]; |
---|
838 | volatile uint16_t tfnum; /* +0x5C */ |
---|
839 | volatile uint16_t res14[1]; |
---|
840 | volatile uint16_t rfdata; /* +0x60 */ |
---|
841 | volatile uint16_t res15[1]; |
---|
842 | volatile uint16_t rfstat; /* +0x64 */ |
---|
843 | volatile uint16_t res16[1]; |
---|
844 | volatile uint8_t rfcntl; /* +0x68 */ |
---|
845 | volatile uint8_t res17[5]; |
---|
846 | volatile uint16_t rfalarm; /* +0x6E */ |
---|
847 | volatile uint8_t res18[2]; |
---|
848 | volatile uint16_t rfrptr; /* +0x72 */ |
---|
849 | volatile uint16_t res19[1]; |
---|
850 | volatile uint16_t rfwptr; /* +0x76 */ |
---|
851 | volatile uint16_t res20[1]; |
---|
852 | volatile uint16_t rflrfptr; /* +0x7A */ |
---|
853 | volatile uint16_t rflwfptr; /* +0x7C */ |
---|
854 | volatile uint16_t res21[1]; |
---|
855 | volatile uint16_t tfdata; /* +0x80 */ |
---|
856 | volatile uint16_t res22[1]; |
---|
857 | volatile uint16_t tfstat; /* +0x84 */ |
---|
858 | volatile uint16_t res23[1]; |
---|
859 | volatile uint8_t tfcntl; /* +0x88 */ |
---|
860 | volatile uint8_t res24[5]; |
---|
861 | volatile uint16_t tfalarm; /* +0x8E */ |
---|
862 | volatile uint8_t res25[2]; |
---|
863 | volatile uint16_t tfrptr; /* +0x92 */ |
---|
864 | volatile uint16_t res26[1]; |
---|
865 | volatile uint16_t tfwptr; /* +0x96 */ |
---|
866 | volatile uint16_t res27[1]; |
---|
867 | volatile uint16_t tflrfptr; /* +0x96 */ |
---|
868 | volatile uint16_t tflwfptr; /* +0x9C */ |
---|
869 | volatile uint16_t res28[1]; /* end at offset 0x9F */ |
---|
870 | volatile uint8_t res29[0x160]; |
---|
871 | } psc[MPC5200_PSC_REG_SETS]; |
---|
872 | /* XXX: there are only 6 PSCs, but PSC6 has an extra register gap |
---|
873 | * from PSC5, therefore we instantiate seven(!) PSC register sets |
---|
874 | */ |
---|
875 | |
---|
876 | #define TX_FIFO_SIZE 256 |
---|
877 | #define RX_FIFO_SIZE 512 |
---|
878 | |
---|
879 | |
---|
880 | volatile uint8_t irda[0x200]; |
---|
881 | |
---|
882 | /* |
---|
883 | * ethernet registers (MBAR + 0x3000) |
---|
884 | */ |
---|
885 | |
---|
886 | /* Control and status Registers (offset 000-1FF) */ |
---|
887 | |
---|
888 | volatile uint32_t fec_id; /* + 0x000 */ |
---|
889 | volatile uint32_t ievent; /* + 0x004 */ |
---|
890 | volatile uint32_t imask; /* + 0x008 */ |
---|
891 | |
---|
892 | volatile uint32_t res9[1]; /* + 0x00C */ |
---|
893 | volatile uint32_t r_des_active; /* + 0x010 */ |
---|
894 | volatile uint32_t x_des_active; /* + 0x014 */ |
---|
895 | volatile uint32_t r_des_active_cl; /* + 0x018 */ |
---|
896 | volatile uint32_t x_des_active_cl; /* + 0x01C */ |
---|
897 | volatile uint32_t ivent_set; /* + 0x020 */ |
---|
898 | volatile uint32_t ecntrl; /* + 0x024 */ |
---|
899 | |
---|
900 | volatile uint32_t res10[6]; /* + 0x028-03C */ |
---|
901 | volatile uint32_t mii_data; /* + 0x040 */ |
---|
902 | volatile uint32_t mii_speed; /* + 0x044 */ |
---|
903 | volatile uint32_t mii_status; /* + 0x048 */ |
---|
904 | |
---|
905 | volatile uint32_t res11[5]; /* + 0x04C-05C */ |
---|
906 | volatile uint32_t mib_data; /* + 0x060 */ |
---|
907 | volatile uint32_t mib_control; /* + 0x064 */ |
---|
908 | |
---|
909 | volatile uint32_t res12[6]; /* + 0x068-7C */ |
---|
910 | volatile uint32_t r_activate; /* + 0x080 */ |
---|
911 | volatile uint32_t r_cntrl; /* + 0x084 */ |
---|
912 | volatile uint32_t r_hash; /* + 0x088 */ |
---|
913 | volatile uint32_t r_data; /* + 0x08C */ |
---|
914 | volatile uint32_t ar_done; /* + 0x090 */ |
---|
915 | volatile uint32_t r_test; /* + 0x094 */ |
---|
916 | volatile uint32_t r_mib; /* + 0x098 */ |
---|
917 | volatile uint32_t r_da_low; /* + 0x09C */ |
---|
918 | volatile uint32_t r_da_high; /* + 0x0A0 */ |
---|
919 | |
---|
920 | volatile uint32_t res13[7]; /* + 0x0A4-0BC */ |
---|
921 | volatile uint32_t x_activate; /* + 0x0C0 */ |
---|
922 | volatile uint32_t x_cntrl; /* + 0x0C4 */ |
---|
923 | volatile uint32_t backoff; /* + 0x0C8 */ |
---|
924 | volatile uint32_t x_data; /* + 0x0CC */ |
---|
925 | volatile uint32_t x_status; /* + 0x0D0 */ |
---|
926 | volatile uint32_t x_mib; /* + 0x0D4 */ |
---|
927 | volatile uint32_t x_test; /* + 0x0D8 */ |
---|
928 | volatile uint32_t fdxfc_da1; /* + 0x0DC */ |
---|
929 | volatile uint32_t fdxfc_da2; /* + 0x0E0 */ |
---|
930 | volatile uint32_t paddr1; /* + 0x0E4 */ |
---|
931 | volatile uint32_t paddr2; /* + 0x0E8 */ |
---|
932 | volatile uint32_t op_pause; /* + 0x0EC */ |
---|
933 | |
---|
934 | volatile uint32_t res14[4]; /* + 0x0F0-0FC */ |
---|
935 | volatile uint32_t instr_reg; /* + 0x100 */ |
---|
936 | volatile uint32_t context_reg; /* + 0x104 */ |
---|
937 | volatile uint32_t test_cntrl; /* + 0x108 */ |
---|
938 | volatile uint32_t acc_reg; /* + 0x10C */ |
---|
939 | volatile uint32_t ones; /* + 0x110 */ |
---|
940 | volatile uint32_t zeros; /* + 0x114 */ |
---|
941 | volatile uint32_t iaddr1; /* + 0x118 */ |
---|
942 | volatile uint32_t iaddr2; /* + 0x11C */ |
---|
943 | volatile uint32_t gaddr1; /* + 0x120 */ |
---|
944 | volatile uint32_t gaddr2; /* + 0x124 */ |
---|
945 | volatile uint32_t random; /* + 0x128 */ |
---|
946 | volatile uint32_t rand1; /* + 0x12C */ |
---|
947 | volatile uint32_t tmp; /* + 0x130 */ |
---|
948 | |
---|
949 | volatile uint32_t res15[3]; /* + 0x134-13C */ |
---|
950 | volatile uint32_t fifo_id; /* + 0x140 */ |
---|
951 | volatile uint32_t x_wmrk; /* + 0x144 */ |
---|
952 | volatile uint32_t fcntrl; /* + 0x148 */ |
---|
953 | volatile uint32_t r_bound; /* + 0x14C */ |
---|
954 | volatile uint32_t r_fstart; /* + 0x150 */ |
---|
955 | volatile uint32_t r_count; /* + 0x154 */ |
---|
956 | volatile uint32_t r_lag; /* + 0x158 */ |
---|
957 | volatile uint32_t r_read; /* + 0x15C */ |
---|
958 | volatile uint32_t r_write; /* + 0x160 */ |
---|
959 | volatile uint32_t x_count; /* + 0x164 */ |
---|
960 | volatile uint32_t x_lag; /* + 0x168 */ |
---|
961 | volatile uint32_t x_retry; /* + 0x16C */ |
---|
962 | volatile uint32_t x_write; /* + 0x170 */ |
---|
963 | volatile uint32_t x_read; /* + 0x174 */ |
---|
964 | |
---|
965 | volatile uint32_t res16[2]; /* + 0x178-17C */ |
---|
966 | volatile uint32_t fm_cntrl; /* + 0x180 */ |
---|
967 | volatile uint32_t rfifo_data; /* + 0x184 */ |
---|
968 | volatile uint32_t rfifo_status; /* + 0x188 */ |
---|
969 | volatile uint32_t rfifo_cntrl; /* + 0x18C */ |
---|
970 | volatile uint32_t rfifo_lrf_ptr; /* + 0x190 */ |
---|
971 | volatile uint32_t rfifo_lwf_ptr; /* + 0x194 */ |
---|
972 | volatile uint32_t rfifo_alarm; /* + 0x198 */ |
---|
973 | volatile uint32_t rfifo_rdptr; /* + 0x19C */ |
---|
974 | volatile uint32_t rfifo_wrptr; /* + 0x1A0 */ |
---|
975 | volatile uint32_t tfifo_data; /* + 0x1A4 */ |
---|
976 | volatile uint32_t tfifo_status; /* + 0x1A8 */ |
---|
977 | volatile uint32_t tfifo_cntrl; /* + 0x1AC */ |
---|
978 | volatile uint32_t tfifo_lrf_ptr; /* + 0x1B0 */ |
---|
979 | volatile uint32_t tfifo_lwf_ptr; /* + 0x1B4 */ |
---|
980 | volatile uint32_t tfifo_alarm; /* + 0x1B8 */ |
---|
981 | volatile uint32_t tfifo_rdptr; /* + 0x1BC */ |
---|
982 | volatile uint32_t tfifo_wrptr; /* + 0x1C0 */ |
---|
983 | |
---|
984 | volatile uint32_t reset_cntrl; /* + 0x1C4 */ |
---|
985 | volatile uint32_t xmit_fsm; /* + 0x1C8 */ |
---|
986 | |
---|
987 | volatile uint32_t res17[3]; /* + 0x1CC-1D4 */ |
---|
988 | volatile uint32_t rdes_data0; /* + 0x1D8 */ |
---|
989 | volatile uint32_t rdes_data1; /* + 0x1DC */ |
---|
990 | volatile uint32_t r_length; /* + 0x1E0 */ |
---|
991 | volatile uint32_t x_length; /* + 0x1E4 */ |
---|
992 | volatile uint32_t x_addr; /* + 0x1E8 */ |
---|
993 | volatile uint32_t cdes_data; /* + 0x1EC */ |
---|
994 | volatile uint32_t status; /* + 0x1F0 */ |
---|
995 | volatile uint32_t dma_control; /* + 0x1F4 */ |
---|
996 | volatile uint32_t des_cmnd; /* + 0x1F8 */ |
---|
997 | volatile uint32_t data; /* + 0x1FC */ |
---|
998 | |
---|
999 | volatile uint8_t RES[0x600]; |
---|
1000 | |
---|
1001 | |
---|
1002 | #if 0 |
---|
1003 | /* MIB COUNTERS (Offset 200-2FF) */ |
---|
1004 | |
---|
1005 | volatile uint32_t rmon_t_drop; /* + 0x200 */ |
---|
1006 | volatile uint32_t rmon_t_packets; /* + 0x204 */ |
---|
1007 | volatile uint32_t rmon_t_bc_pkt; /* + 0x208 */ |
---|
1008 | volatile uint32_t rmon_t_mc_pkt; /* + 0x20C */ |
---|
1009 | volatile uint32_t rmon_t_crc_align; /* + 0x210 */ |
---|
1010 | volatile uint32_t rmon_t_undersize; /* + 0x214 */ |
---|
1011 | volatile uint32_t rmon_t_oversize; /* + 0x218 */ |
---|
1012 | volatile uint32_t rmon_t_frag; /* + 0x21C */ |
---|
1013 | volatile uint32_t rmon_t_jab; /* + 0x220 */ |
---|
1014 | volatile uint32_t rmon_t_col; /* + 0x224 */ |
---|
1015 | volatile uint32_t rmon_t_p64; /* + 0x228 */ |
---|
1016 | volatile uint32_t rmon_t_p65to127; /* + 0x22C */ |
---|
1017 | volatile uint32_t rmon_t_p128to255; /* + 0x230 */ |
---|
1018 | volatile uint32_t rmon_t_p256to511; /* + 0x234 */ |
---|
1019 | volatile uint32_t rmon_t_p512to1023; /* + 0x238 */ |
---|
1020 | volatile uint32_t rmon_t_p1024to2047;/* + 0x23C */ |
---|
1021 | volatile uint32_t rmon_t_p_gte2048; /* + 0x240 */ |
---|
1022 | volatile uint32_t rmon_t_octets; /* + 0x244 */ |
---|
1023 | volatile uint32_t ieee_t_drop; /* + 0x248 */ |
---|
1024 | volatile uint32_t ieee_t_frame_ok; /* + 0x24C */ |
---|
1025 | volatile uint32_t ieee_t_1col; /* + 0x250 */ |
---|
1026 | volatile uint32_t ieee_t_mcol; /* + 0x254 */ |
---|
1027 | volatile uint32_t ieee_t_def; /* + 0x258 */ |
---|
1028 | volatile uint32_t ieee_t_lcol; /* + 0x25C */ |
---|
1029 | volatile uint32_t ieee_t_excol; /* + 0x260 */ |
---|
1030 | volatile uint32_t ieee_t_macerr; /* + 0x264 */ |
---|
1031 | volatile uint32_t ieee_t_cserr; /* + 0x268 */ |
---|
1032 | volatile uint32_t ieee_t_sqe; /* + 0x26C */ |
---|
1033 | volatile uint32_t t_fdxfc; /* + 0x270 */ |
---|
1034 | volatile uint32_t ieee_t_octets_ok; /* + 0x274 */ |
---|
1035 | |
---|
1036 | volatile uint32_t res18[2]; /* + 0x278-27C */ |
---|
1037 | volatile uint32_t rmon_r_drop; /* + 0x280 */ |
---|
1038 | volatile uint32_t rmon_r_packets; /* + 0x284 */ |
---|
1039 | volatile uint32_t rmon_r_bc_pkt; /* + 0x288 */ |
---|
1040 | volatile uint32_t rmon_r_mc_pkt; /* + 0x28C */ |
---|
1041 | volatile uint32_t rmon_r_crc_align; /* + 0x290 */ |
---|
1042 | volatile uint32_t rmon_r_undersize; /* + 0x294 */ |
---|
1043 | volatile uint32_t rmon_r_oversize; /* + 0x298 */ |
---|
1044 | volatile uint32_t rmon_r_frag; /* + 0x29C */ |
---|
1045 | volatile uint32_t rmon_r_jab; /* + 0x2A0 */ |
---|
1046 | |
---|
1047 | volatile uint32_t rmon_r_resvd_0; /* + 0x2A4 */ |
---|
1048 | |
---|
1049 | volatile uint32_t rmon_r_p64; /* + 0x2A8 */ |
---|
1050 | volatile uint32_t rmon_r_p65to127; /* + 0x2AC */ |
---|
1051 | volatile uint32_t rmon_r_p128to255; /* + 0x2B0 */ |
---|
1052 | volatile uint32_t rmon_r_p256to511; /* + 0x2B4 */ |
---|
1053 | volatile uint32_t rmon_r_p512to1023; /* + 0x2B8 */ |
---|
1054 | volatile uint32_t rmon_r_p1024to2047;/* + 0x2BC */ |
---|
1055 | volatile uint32_t rmon_r_p_gte2048; /* + 0x2C0 */ |
---|
1056 | volatile uint32_t rmon_r_octets; /* + 0x2C4 */ |
---|
1057 | volatile uint32_t ieee_r_drop; /* + 0x2C8 */ |
---|
1058 | volatile uint32_t ieee_r_frame_ok; /* + 0x2CC */ |
---|
1059 | volatile uint32_t ieee_r_crc; /* + 0x2D0 */ |
---|
1060 | volatile uint32_t ieee_r_align; /* + 0x2D4 */ |
---|
1061 | volatile uint32_t r_macerr; /* + 0x2D8 */ |
---|
1062 | volatile uint32_t r_fdxfc; /* + 0x2DC */ |
---|
1063 | volatile uint32_t ieee_r_octets_ok; /* + 0x2E0 */ |
---|
1064 | |
---|
1065 | volatile uint32_t res19[6]; /* + 0x2E4-2FC */ |
---|
1066 | |
---|
1067 | volatile uint32_t res20[64]; /* + 0x300-3FF */ |
---|
1068 | |
---|
1069 | volatile uint32_t res21[256]; /* + 0x400-800 */ |
---|
1070 | #endif |
---|
1071 | |
---|
1072 | /* |
---|
1073 | * SmartComm DMA PCI registers (MBAR + 0x3800) |
---|
1074 | */ |
---|
1075 | volatile uint8_t pci[0x200]; |
---|
1076 | |
---|
1077 | /* |
---|
1078 | * advanced technology attachment registers (MBAR + 0x3A00) |
---|
1079 | */ |
---|
1080 | |
---|
1081 | /* ATA host registers (offset 0x00-0x28) */ |
---|
1082 | volatile uint32_t ata_hcfg; /* + 0x00 */ |
---|
1083 | volatile uint32_t ata_hsr; /* + 0x04 */ |
---|
1084 | volatile uint32_t ata_pio1; /* + 0x08 */ |
---|
1085 | volatile uint32_t ata_pio2; /* + 0x0C */ |
---|
1086 | volatile uint32_t ata_dma1; /* + 0x10 */ |
---|
1087 | volatile uint32_t ata_dma2; /* + 0x14 */ |
---|
1088 | volatile uint32_t ata_udma1; /* + 0x18 */ |
---|
1089 | volatile uint32_t ata_udma2; /* + 0x1C */ |
---|
1090 | volatile uint32_t ata_udma3; /* + 0x20 */ |
---|
1091 | volatile uint32_t ata_udma4; /* + 0x24 */ |
---|
1092 | volatile uint32_t ata_udma5; /* + 0x28 */ |
---|
1093 | volatile uint32_t ata_res1[4]; /* + 0x2C-0x3C */ |
---|
1094 | |
---|
1095 | /* ATA FIFO registers (offset 0x3C-0x50) */ |
---|
1096 | volatile uint32_t ata_rtfdwr; /* + 0x3C */ |
---|
1097 | volatile uint32_t ata_rtfsr; /* + 0x40 */ |
---|
1098 | volatile uint32_t ata_rtfcr; /* + 0x44 */ |
---|
1099 | volatile uint32_t ata_rtfar; /* + 0x48 */ |
---|
1100 | volatile uint32_t ata_rtfrpr; /* + 0x4C */ |
---|
1101 | volatile uint32_t ata_rtfwpr; /* + 0x50 */ |
---|
1102 | volatile uint32_t ata_res2[2]; /* + 0x54-0x5C */ |
---|
1103 | |
---|
1104 | /* ATA drive registers (offset 0x5C-0x80) */ |
---|
1105 | volatile uint32_t ata_dctr_dasr; /* + 0x5C */ |
---|
1106 | volatile uint32_t ata_ddr; /* + 0x60 */ |
---|
1107 | volatile uint32_t ata_dfr_der; /* + 0x64 */ |
---|
1108 | volatile uint32_t ata_dscr; /* + 0x68 */ |
---|
1109 | volatile uint32_t ata_dsnr; /* + 0x6C */ |
---|
1110 | volatile uint32_t ata_dclr; /* + 0x70 */ |
---|
1111 | volatile uint32_t ata_dchr; /* + 0x74 */ |
---|
1112 | volatile uint32_t ata_ddhr; /* + 0x78 */ |
---|
1113 | volatile uint32_t ata_dcr_dsr; /* + 0x7C */ |
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1114 | volatile uint32_t ata_res3[0xA0]; /* + 0x80-0x200 */ |
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1115 | |
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1116 | /* |
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1117 | * inter-integrated circuit registers (MBAR + 0x3D00) |
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1118 | */ |
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1119 | struct mpc5200_i2c_regs_s { |
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1120 | volatile uint8_t madr; /* i2c address reg. +0x00 */ |
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1121 | volatile uint8_t res_1[3]; |
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1122 | volatile uint8_t mfdr; /* i2c freq. divider reg. +0x04 */ |
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1123 | volatile uint8_t res_5[3]; |
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1124 | volatile uint8_t mcr; /* i2c control reg. +0x08 */ |
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1125 | volatile uint8_t res_9[3]; |
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1126 | |
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1127 | #define MPC5200_I2C_MCR_MEN (1 << (7-0)) |
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1128 | #define MPC5200_I2C_MCR_MIEN (1 << (7-1)) |
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1129 | #define MPC5200_I2C_MCR_MSTA (1 << (7-2)) |
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1130 | #define MPC5200_I2C_MCR_MTX (1 << (7-3)) |
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1131 | #define MPC5200_I2C_MCR_TXAK (1 << (7-4)) |
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1132 | #define MPC5200_I2C_MCR_RSTA (1 << (7-5)) |
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1133 | |
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1134 | volatile uint8_t msr; /* i2c status reg. +0x0C */ |
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1135 | volatile uint8_t res_d[3]; |
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1136 | #define MPC5200_I2C_MSR_CF (1 << (7-0)) |
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1137 | #define MPC5200_I2C_MSR_MAAS (1 << (7-1)) |
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1138 | #define MPC5200_I2C_MSR_BB (1 << (7-2)) |
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1139 | #define MPC5200_I2C_MSR_MAL (1 << (7-3)) |
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1140 | #define MPC5200_I2C_MSR_SRW (1 << (7-5)) |
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1141 | #define MPC5200_I2C_MSR_MIF (1 << (7-6)) |
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1142 | #define MPC5200_I2C_MSR_RXAK (1 << (7-7)) |
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1143 | volatile uint8_t mdr; /* i2c data I/O reg. +0x10 */ |
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1144 | volatile uint8_t res_11[3]; |
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1145 | volatile uint8_t res_14[12]; /* reserved +0x14 */ |
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1146 | volatile uint8_t icr; /* i2c irq ctrl reg. +0x20 */ |
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1147 | #define MPC5200_I2C_ICR_BNBE2 (1 << (7-0)) |
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1148 | #define MPC5200_I2C_ICR_TE2 (1 << (7-1)) |
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1149 | #define MPC5200_I2C_ICR_RE2 (1 << (7-2)) |
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1150 | #define MPC5200_I2C_ICR_IE2 (1 << (7-3)) |
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1151 | #define MPC5200_I2C_ICR_MASK2 (MPC5200_I2C_ICR_BNBE2|MPC5200_I2C_ICR_TE2\ |
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1152 | |MPC5200_I2C_ICR_RE2|MPC5200_I2C_ICR_IE2) |
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1153 | #define MPC5200_I2C_ICR_BNBE1 (1 << (7-4)) |
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1154 | #define MPC5200_I2C_ICR_TE1 (1 << (7-5)) |
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1155 | #define MPC5200_I2C_ICR_RE1 (1 << (7-6)) |
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1156 | #define MPC5200_I2C_ICR_IE1 (1 << (7-7)) |
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1157 | #define MPC5200_I2C_ICR_MASK1 (MPC5200_I2C_ICR_BNBE1|MPC5200_I2C_ICR_TE1\ |
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1158 | |MPC5200_I2C_ICR_RE1|MPC5200_I2C_ICR_IE1) |
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1159 | volatile uint8_t res_21[3]; |
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1160 | volatile uint32_t res_24[7]; /* reserved +0x24 */ |
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1161 | } i2c_regs[2]; |
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1162 | volatile uint8_t res_3d80[0x280]; |
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1163 | |
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1164 | /* |
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1165 | * on-chip static RAM memory locations (MBAR + 0x4000) |
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1166 | */ |
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1167 | volatile uint8_t sram_res0x4000[0x4000]; |
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1168 | volatile uint8_t sram[0x4000]; |
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1169 | |
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1170 | } mpc5200_t; |
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1171 | |
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1172 | extern volatile mpc5200_t mpc5200; |
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1173 | |
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1174 | #ifdef __cplusplus |
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1175 | } |
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1176 | #endif |
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1177 | |
---|
1178 | #endif /*ASM*/ |
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1179 | |
---|
1180 | #endif /* __MPC5200_h__ */ |
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