[ca680bc5] | 1 | /*===============================================================*\ |
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| 2 | | Project: RTEMS generic MPC5200 BSP | |
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| 3 | +-----------------------------------------------------------------+ |
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| 4 | | Partially based on the code references which are named below. | |
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| 5 | | Adaptions, modifications, enhancements and any recent parts of | |
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| 6 | | the code are: | |
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| 7 | | Copyright (c) 2005 | |
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| 8 | | Embedded Brains GmbH | |
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| 9 | | Obere Lagerstr. 30 | |
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| 10 | | D-82178 Puchheim | |
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| 11 | | Germany | |
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| 12 | | rtems@embedded-brains.de | |
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| 13 | +-----------------------------------------------------------------+ |
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| 14 | | The license and distribution terms for this file may be | |
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| 15 | | found in the file LICENSE in this distribution or at | |
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| 16 | | | |
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| 17 | | http://www.rtems.com/license/LICENSE. | |
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| 18 | | | |
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| 19 | +-----------------------------------------------------------------+ |
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| 20 | | this file contains definitions for the mpc5200 hw registers | |
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| 21 | \*===============================================================*/ |
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| 22 | |
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| 23 | #ifndef __MPC5200_h__ |
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| 24 | #define __MPC5200_h__ |
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| 25 | |
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| 26 | /* Additional Harpo Core SPR definitions (603le only) */ |
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| 27 | #define CSRR0 58 /* Critical Interrupt SRR0 */ |
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| 28 | #define CSRR1 59 /* Critical Interrupt SRR1 */ |
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| 29 | #define SPRG4 276 /* Special Purpose Register 4 */ |
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| 30 | #define SPRG5 277 /* Special Purpose Register 5 */ |
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| 31 | #define SPRG6 278 /* Special Purpose Register 6 */ |
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| 32 | #define SPRG7 279 /* Special Purpose Register 7 */ |
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| 33 | #define IBAT4U 560 /* Instruction BAT #0 Upper/Lower */ |
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| 34 | #define IBAT4L 561 |
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| 35 | #define IBAT5U 562 /* Instruction BAT #1 Upper/Lower */ |
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| 36 | #define IBAT5L 563 |
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| 37 | #define IBAT6U 564 /* Instruction BAT #2 Upper/Lower */ |
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| 38 | #define IBAT6L 565 |
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| 39 | #define IBAT7U 566 /* Instruction BAT #3 Upper/Lower */ |
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| 40 | #define IBAT7L 567 |
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| 41 | #define DBAT4U 568 /* Data BAT #0 Upper/Lower */ |
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| 42 | #define DBAT4L 569 |
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| 43 | #define DBAT5U 570 /* Data BAT #1 Upper/Lower */ |
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| 44 | #define DBAT5L 571 |
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| 45 | #define DBAT6U 572 /* Data BAT #2 Upper/Lower */ |
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| 46 | #define DBAT6L 573 |
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| 47 | #define DBAT7U 574 /* Data BAT #3 Upper/Lower */ |
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| 48 | #define DBAT7L 575 |
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| 49 | #define DABR2 1000 /* Data Address Breakpoint #2 */ |
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| 50 | #define DBCR 1001 /* Data Address Breakpoint Control */ |
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| 51 | #define IBCR 1002 /* Instruction Breakpoint Control */ |
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| 52 | #define HID1 1009 /* Hardware Implementation 1 */ |
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| 53 | #define HID2 1011 /* Hardware Implementation 2 */ |
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| 54 | #define DABR 1013 /* Data Address Breakpoint */ |
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| 55 | #define IABR2 1018 /* Instruction Breakpoint #2 */ |
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| 56 | |
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| 57 | /* |
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| 58 | * Initial post-reset location of MGT5100 module base address register (MBAR) |
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| 59 | */ |
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| 60 | #define MBAR_RESET 0x80000000 |
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| 61 | |
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| 62 | /* |
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| 63 | * Location and size of onchip SRAM (relative to MBAR) |
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| 64 | */ |
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| 65 | #define ONCHIP_SRAM_OFFSET 0x8000 |
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| 66 | #define ONCHIP_SRAM_SIZE 0x4000 |
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| 67 | |
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| 68 | #ifndef ASM |
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| 69 | #include <rtems.h> |
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| 70 | |
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| 71 | #ifdef __cplusplus |
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| 72 | extern "C" { |
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| 73 | #endif |
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| 74 | |
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| 75 | #define MPC5200_CAN_NO 2 |
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| 76 | #define MPC5200_PSC_NO 6 |
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| 77 | /* XXX: there are only 6 PSCs, but PSC6 has an extra register gap |
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| 78 | * from PSC5, therefore we instantiate seven(!) PSC register sets |
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| 79 | */ |
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| 80 | #define MPC5200_PSC_REG_SETS 7 |
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| 81 | |
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| 82 | #define MPC5200_GPT_NO 8 |
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| 83 | #define MPC5200_SLT_NO 2 |
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| 84 | |
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| 85 | /* |
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| 86 | * Bit fields for FEC interrupts, ievent and imask above. |
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| 87 | */ |
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| 88 | #define FEC_INTR_HBERR 0x80000000 /* heartbeat error */ |
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| 89 | #define FEC_INTR_BABR 0x40000000 /* babbling receive error */ |
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| 90 | #define FEC_INTR_BABT 0x20000000 /* babbling transmit error */ |
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| 91 | #define FEC_INTR_GRA 0x10000000 /* graceful stop complete */ |
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| 92 | #define FEC_INTR_TFINT 0x08000000 /* transmit frame interrupt */ |
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| 93 | /* 0x04000000 reserved */ |
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| 94 | /* 0x02000000 reserved */ |
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| 95 | /* 0x01000000 reserved */ |
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| 96 | #define FEC_INTR_MII 0x00800000 /* MII interrupt */ |
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| 97 | /* 0x00400000 reserved */ |
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| 98 | #define FEC_INTR_LATE_COL 0x00200000 /* late collision */ |
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| 99 | #define FEC_INTR_COL_RETRY 0x00100000 /* collision retry limit */ |
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| 100 | #define FEC_INTR_XFIFO_UN 0x00080000 /* transmit FIFO error */ |
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| 101 | #define FEC_INTR_XFIFO_ERR 0x00040000 /* transmit FIFO error */ |
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| 102 | #define FEC_INTR_RFIFO_ERR 0x00020000 /* receive FIFO error */ |
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| 103 | /* 0x00010000 reserved */ |
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| 104 | /* 0x0000ffff reserved */ |
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| 105 | #define FEC_INTR_HBEEN FEC_INTR_HBERR |
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| 106 | #define FEC_INTR_BREN FEC_INTR_BABR |
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| 107 | #define FEC_INTR_BTEN FEC_INTR_BABT |
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| 108 | #define FEC_INTR_GRAEN FEC_INTR_GRA |
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| 109 | #define FEC_INTR_TFINTEN FEC_INTR_TFINT |
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| 110 | #define FEC_INTR_MIIEN FEC_INTR_MII |
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| 111 | #define FEC_INTR_LCEN FEC_INTR_LATE_COL |
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| 112 | #define FEC_INTR_CRLEN FEC_INTR_COL_RETRY |
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| 113 | #define FEC_INTR_XFUNEN FEC_INTR_XFIFO_UN |
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| 114 | #define FEC_INTR_XFERREN FEC_INTR_XFIFO_ERR |
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| 115 | #define FEC_INTR_RFERREN FEC_INTR_RFIFO_ERR |
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| 116 | #define FEC_INTR_CLEAR_ALL 0xffffffff /* clear all interrupt events */ |
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| 117 | #define FEC_INTR_MASK_ALL 0x00000000 /* mask all interrupt events */ |
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| 118 | |
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| 119 | /* |
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| 120 | * Bit fields for FEC ethernet control, ecntrl above. |
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| 121 | */ |
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| 122 | #define FEC_ECNTRL_TAG 0xf0000000 /* TBUS tag bits */ |
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| 123 | /* 0x08000000 reserved */ |
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| 124 | #define FEC_ECNTRL_TESTMD 0x04000000 /* test mode */ |
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| 125 | /* 0x03fffff8 reserved */ |
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| 126 | #define FEC_ECNTRL_OE 0x00000004 /* FEC output enable */ |
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| 127 | #define FEC_ECNTRL_EN 0x00000002 /* ethernet enable */ |
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| 128 | #define FEC_ECNTRL_RESET 0x00000001 /* ethernet controller reset */ |
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| 129 | |
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| 130 | /* |
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| 131 | * Bit fields for FEC receive control, r_cntrl above. |
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| 132 | */ |
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| 133 | /* 0xf1000000 reserved */ |
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| 134 | #define FEC_RCNTRL_MAX_FL 0x07ff0000 /* maximum frame length */ |
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| 135 | #define FEC_RCNTRL_MAX_FL_SHIFT 16 |
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| 136 | /* 0x0000ffc0 reserved */ |
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| 137 | #define FEC_RCNTRL_FCE 0x00000020 /* flow control enable */ |
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| 138 | #define FEC_RCNTRL_BC_REJ 0x00000010 /* broadcast frame reject */ |
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| 139 | #define FEC_RCNTRL_PROM 0x00000008 /* promiscuous mode */ |
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| 140 | #define FEC_RCNTRL_MII_MODE 0x00000004 /* select 18-wire (MII) mode */ |
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| 141 | #define FEC_RCNTRL_DRT 0x00000002 /* disable receive on transmit */ |
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| 142 | #define FEC_RCNTRL_LOOP 0x00000001 /* internal loopback */ |
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| 143 | |
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| 144 | /* |
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| 145 | * Bit fields for FEC transmit control, x_cntrl above. |
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| 146 | */ |
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| 147 | /* 0xffffffe0 reserved */ |
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| 148 | #define FEC_XCNTRL_RFC_PAUS 0x00000010 /* FDX flow control pause rx */ |
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| 149 | #define FEC_XCNTRL_TFC_PAUS 0x00000008 /* assert a PAUSE frame */ |
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| 150 | #define FEC_XCNTRL_FDEN 0x00000004 /* full duplex enable */ |
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| 151 | #define FEC_XCNTRL_HBC 0x00000002 /* heartbeat control */ |
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| 152 | #define FEC_XCNTRL_GTS 0x00000001 /* graceful transmit stop */ |
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| 153 | |
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| 154 | /* |
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| 155 | * Bit fields for FEC transmit status, x_status above. |
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| 156 | */ |
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| 157 | /* 0xfc000000 reserved */ |
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| 158 | #define FEC_XSTAT_DEF 0x02000000 /* defer */ |
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| 159 | #define FEC_XSTAT_HB 0x01000000 /* heartbeat error */ |
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| 160 | #define FEC_XSTAT_LC 0x00800000 /* late collision */ |
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| 161 | #define FEC_XSTAT_RL 0x00400000 /* retry limit */ |
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| 162 | #define FEC_XSTAT_RC 0x003c0000 /* retry count */ |
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| 163 | #define FEC_XSTAT_UN 0x00020000 /* underrun */ |
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| 164 | #define FEX_XSTAT_CSL 0x00010000 /* carrier sense lost */ |
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| 165 | /* 0x0000ffff reserved */ |
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| 166 | |
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| 167 | /* |
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| 168 | * Bit fields for FEC transmit FIFO watermark, x_wmrk above. |
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| 169 | */ |
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| 170 | #define FEC_XWMRK_64 0x00000000 /* 64 bytes written to TxFIFO */ |
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| 171 | #define FEC_XWMRK_128 0x00000001 /* 128 bytes written to TxFIFO */ |
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| 172 | #define FEC_XWMRK_192 0x00000002 /* 192 bytes written to TxFIFO */ |
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| 173 | #define FEC_XWMRK_256 0x00000003 /* 256 bytes written to TxFIFO */ |
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| 174 | #define FEC_XWMRK_320 0x00000004 /* 320 bytes written to TxFIFO */ |
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| 175 | #define FEC_XWMRK_384 0x00000005 /* 384 bytes written to TxFIFO */ |
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| 176 | #define FEC_XWMRK_448 0x00000006 /* 448 bytes written to TxFIFO */ |
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| 177 | #define FEC_XWMRK_512 0x00000007 /* 512 bytes written to TxFIFO */ |
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| 178 | #define FEC_XWMRK_576 0x00000008 /* 576 bytes written to TxFIFO */ |
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| 179 | #define FEC_XWMRK_640 0x00000009 /* 640 bytes written to TxFIFO */ |
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| 180 | #define FEC_XWMRK_704 0x0000000a /* 704 bytes written to TxFIFO */ |
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| 181 | #define FEC_XWMRK_768 0x0000000b /* 768 bytes written to TxFIFO */ |
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| 182 | #define FEC_XWMRK_832 0x0000000c /* 832 bytes written to TxFIFO */ |
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| 183 | #define FEC_XWMRK_896 0x0000000d /* 896 bytes written to TxFIFO */ |
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| 184 | #define FEC_XWMRK_960 0x0000000e /* 960 bytes written to TxFIFO */ |
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| 185 | #define FEC_XWMRK_1024 0x0000000f /* 1024 bytes written to TxFIFO */ |
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| 186 | |
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| 187 | /* |
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| 188 | * Bit fields for FEC transmit finite state machine. |
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| 189 | */ |
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| 190 | /* 0xfc000000 reserved */ |
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| 191 | #define FEC_FSM_CRC 0x02000000 /* append CRC (typical use) */ |
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| 192 | #define FEC_FSM_ENFSM 0x01000000 /* enable CRC FSM (typical use) */ |
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| 193 | /* 0x00ffffff reserved */ |
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| 194 | |
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| 195 | /* |
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| 196 | * Bit fields for FEC FIFOs, rfifo_status, rfifo_cntrl, tfifo_status |
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| 197 | * and tfifo_cntrl. |
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| 198 | */ |
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| 199 | #define FEC_FIFO_STAT_IP 0x80000000 /* illegal pointer, sticky */ |
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| 200 | /* 0x70000000 reserved */ |
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| 201 | #define FEC_FIFO_STAT_FRAME 0x0f000000 /* frame indicator */ |
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| 202 | #define FEC_FIFO_STAT_FAE 0x00800000 /* frame accept error */ |
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| 203 | #define FEC_FIFO_STAT_RXW 0x00400000 /* receive wait condition */ |
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| 204 | #define FEC_FIFO_STAT_UF 0x00200000 /* underflow */ |
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| 205 | #define FEC_FIFO_STAT_OF 0x00100000 /* overflow */ |
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| 206 | #define FEC_FIFO_STAT_FR 0x00080000 /* frame ready, read-only */ |
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| 207 | #define FEC_FIFO_STAT_FULL 0x00040000 /* full alarm, read-only */ |
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| 208 | #define FEC_FIFO_STAT_ALARM 0x00020000 /* fifo alarm */ |
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| 209 | #define FEC_FIFO_STAT_EMPTY 0x00010000 /* empty, read-only */ |
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| 210 | /* 0x0000ffff reserved */ |
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| 211 | #define FEC_FIFO_STAT_ERROR ( FEC_FIFO_STAT_IP \ |
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| 212 | | FEC_FIFO_STAT_FAE \ |
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| 213 | | FEC_FIFO_STAT_RXW \ |
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| 214 | | FEC_FIFO_STAT_UF \ |
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| 215 | | FEC_FIFO_STAT_OF \ |
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| 216 | ) |
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| 217 | |
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| 218 | /* 0x80000000 reserved */ |
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| 219 | #define FEC_FIFO_CNTRL_WCTL 0x40000000 /* write control */ |
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| 220 | #define FEC_FIFO_CNTRL_WFR 0x20000000 /* write frame */ |
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| 221 | /* 0x10000000 reserved */ |
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| 222 | #define FEC_FIFO_CNTRL_FRAME 0x08000000 /* frame mode enable */ |
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| 223 | #define FEC_FIFO_CNTRL_GR 0x07000000 /* last transfer granularity */ |
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| 224 | #define FEC_FIFO_CNTRL_GR_SHIFT 24 |
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| 225 | #define FEC_FIFO_CNTRL_IP_MASK 0x00800000 /* illegal pointer mask */ |
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| 226 | #define FEC_FIFO_CNTRL_FAE_MASK 0x00400000 /* frame accept mask */ |
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| 227 | #define FEC_FIFO_CNTRL_RXW_MASK 0x00200000 /* receive wait mask */ |
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| 228 | #define FEC_FIFO_CNTRL_UF_MASK 0x00100000 /* underflow mask */ |
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| 229 | #define FEC_FIFO_CNTRL_OF_MASK 0x00080000 /* overflow mask */ |
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| 230 | /* 0x0007ffff reserved */ |
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| 231 | |
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| 232 | /* |
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| 233 | ************************************************************************* |
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| 234 | * MPC5x00 internal register memory map * |
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| 235 | ************************************************************************* |
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| 236 | */ |
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| 237 | typedef struct mpc5200_ |
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| 238 | { |
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| 239 | /* |
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| 240 | * memory map registers (MBAR + 0) |
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| 241 | */ |
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| 242 | volatile uint8_t mm[0x80]; |
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| 243 | |
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| 244 | /* |
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| 245 | * arbiter registers (processor bus) (MBAR + 0x80) |
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| 246 | */ |
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| 247 | volatile uint8_t arb[0x80]; |
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| 248 | |
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| 249 | /* |
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| 250 | * SDRAM memory controller registers (MBAR + 0x100) |
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| 251 | */ |
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| 252 | volatile uint8_t mc[0x100]; |
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| 253 | |
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| 254 | /* |
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| 255 | * clock distribution module registers (MBAR + 0x200) |
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| 256 | */ |
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| 257 | volatile uint8_t cdm[0x100]; |
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| 258 | |
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| 259 | /* |
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| 260 | * chip selct controller registers(MBAR + 0x300) |
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| 261 | */ |
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| 262 | volatile uint8_t csc[0x100]; |
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| 263 | |
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| 264 | /* |
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| 265 | * SmartComm timer registers (MBAR + 0x400) |
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| 266 | */ |
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| 267 | volatile uint8_t sct[0x100]; |
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| 268 | |
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| 269 | /* |
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| 270 | * interrupt controller registers (MBAR + 0x500) |
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| 271 | */ |
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| 272 | volatile uint32_t per_mask; /* + 0x00 */ |
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| 273 | volatile uint32_t per_pri_1; /* + 0x04 */ |
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| 274 | volatile uint32_t per_pri_2; /* + 0x08 */ |
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| 275 | volatile uint32_t per_pri_3; /* + 0x0C */ |
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| 276 | volatile uint32_t ext_en_type; /* + 0x10 */ |
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| 277 | volatile uint32_t crit_pri_main_mask;/* + 0x14 */ |
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| 278 | volatile uint32_t main_pri_1; /* + 0x18 */ |
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| 279 | volatile uint32_t main_pri_2; /* + 0x1C */ |
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| 280 | volatile uint32_t res1; /* + 0x20 */ |
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| 281 | volatile uint32_t pmce; /* + 0x24 */ |
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| 282 | volatile uint32_t csa; /* + 0x28 */ |
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| 283 | volatile uint32_t msa; /* + 0x2C */ |
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| 284 | volatile uint32_t psa; /* + 0x30 */ |
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| 285 | volatile uint32_t res2; /* + 0x34 */ |
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| 286 | volatile uint32_t psa_be; /* + 0x38 */ |
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| 287 | volatile uint8_t res3[0xC4]; /* + 0x3C */ |
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| 288 | |
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| 289 | /* |
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| 290 | * general pupose timer registers (MBAR + 0x600/+0x610/+0x620/+0x630/+0x640/+0x650/+0x660/+0x670) |
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| 291 | */ |
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| 292 | struct mpc5200_gpt |
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| 293 | { |
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| 294 | volatile uint32_t emsel; /* + 0x00 */ |
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| 295 | volatile uint32_t count_in; /* + 0x04 */ |
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| 296 | volatile uint32_t pwm_conf; /* + 0x08 */ |
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| 297 | volatile uint32_t status; /* + 0x0C */ |
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| 298 | } gpt[MPC5200_GPT_NO]; |
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| 299 | |
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| 300 | #define GPT_STATUS_RESET 0x0000000F |
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| 301 | #define GPT_STATUS_TEXP (1 << 3) |
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| 302 | #define GPT_STATUS_PIN (1 << 8) |
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[c9b005a9] | 303 | #define GPT_EMSEL_GPIO_DIR (2 << 4) |
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| 304 | #define GPT_EMSEL_GPIO_OUT (1 << 4) |
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[ca680bc5] | 305 | #define GPT_EMSEL_GPIO_OUT_HIGH (3 << 4) |
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| 306 | #define GPT_EMSEL_TIMER_MS_GPIO (4 << 0) |
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| 307 | #define GPT_EMSEL_GPIO_IN (0 << 0) |
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| 308 | #define GPT_EMSEL_CE (1 << 12) |
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| 309 | #define GPT_EMSEL_ST_CONT (1 << 10) |
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| 310 | #define GPT_EMSEL_INTEN (1 << 8) |
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[c9b005a9] | 311 | #define GPT_EMSEL_WDEN (1 << 15) |
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[ca680bc5] | 312 | |
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| 313 | #define GPT0 0 |
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| 314 | #define GPT1 1 |
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| 315 | #define GPT2 2 |
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| 316 | #define GPT3 3 |
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| 317 | #define GPT4 4 |
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| 318 | #define GPT5 5 |
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| 319 | #define GPT6 6 |
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| 320 | #define GPT7 7 |
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| 321 | |
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| 322 | volatile uint8_t gpt_res[0x80]; |
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| 323 | |
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| 324 | /* |
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| 325 | * slice time registers (MBAR + 0x700/+0x710) |
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| 326 | */ |
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| 327 | struct mpc5200_slt |
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| 328 | { |
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| 329 | volatile uint32_t tcr; /* + 0x00 */ |
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| 330 | volatile uint32_t cntrl; /* + 0x04 */ |
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| 331 | volatile uint32_t cvr; /* + 0x08 */ |
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| 332 | volatile uint32_t tsr; /* + 0x0C */ |
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| 333 | } slt[MPC5200_SLT_NO]; |
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| 334 | |
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| 335 | volatile uint8_t slt_res[0xE0]; |
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| 336 | |
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| 337 | /* |
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| 338 | * real time clock registers (MBAR + 0x800) |
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| 339 | */ |
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| 340 | volatile uint8_t rtc[0x100]; |
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| 341 | |
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| 342 | |
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| 343 | /* |
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| 344 | * MSCAN registers (MBAR + 0x900 /+0x980) |
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| 345 | */ |
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| 346 | struct mpc5200_mscan |
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| 347 | { |
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| 348 | volatile uint8_t ctl0; /* + 0x0 */ |
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| 349 | volatile uint8_t ctl1; /* + 0x1 */ |
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| 350 | volatile uint8_t res1; /* + 0x2 */ |
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| 351 | volatile uint8_t res2; /* + 0x3 */ |
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| 352 | volatile uint8_t btr0; /* + 0x4 */ |
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| 353 | volatile uint8_t btr1; /* + 0x5 */ |
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| 354 | volatile uint8_t res3; /* + 0x6 */ |
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| 355 | volatile uint8_t res4; /* + 0x7 */ |
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| 356 | volatile uint8_t rflg; /* + 0x8 */ |
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| 357 | volatile uint8_t rier; /* + 0x9 */ |
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| 358 | volatile uint8_t res5; /* + 0xA */ |
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| 359 | volatile uint8_t res6; /* + 0xB */ |
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| 360 | volatile uint8_t tflg; /* + 0xC */ |
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| 361 | volatile uint8_t tier; /* + 0xD */ |
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| 362 | volatile uint8_t res7; /* + 0xE */ |
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| 363 | volatile uint8_t res8; /* + 0xF */ |
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| 364 | volatile uint8_t tarq; /* + 0x10 */ |
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| 365 | volatile uint8_t taak; /* + 0x11 */ |
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| 366 | volatile uint8_t res9; /* + 0x12 */ |
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| 367 | volatile uint8_t res10; /* + 0x13 */ |
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| 368 | volatile uint8_t bsel; /* + 0x14 */ |
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| 369 | volatile uint8_t idac; /* + 0x15 */ |
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| 370 | volatile uint8_t res11; /* + 0x16 */ |
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| 371 | volatile uint8_t res12; /* + 0x17 */ |
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| 372 | volatile uint8_t res13; /* + 0x18 */ |
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| 373 | volatile uint8_t res14; /* + 0x19 */ |
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| 374 | volatile uint8_t res15; /* + 0x1A */ |
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| 375 | volatile uint8_t res16; /* + 0x1B */ |
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| 376 | volatile uint8_t rxerr; /* + 0x1C */ |
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| 377 | volatile uint8_t txerr; /* + 0x1D */ |
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| 378 | volatile uint8_t res17; /* + 0x1E */ |
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| 379 | volatile uint8_t res18; /* + 0x1F */ |
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| 380 | volatile uint8_t idar0; /* + 0x20 */ |
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| 381 | volatile uint8_t idar1; /* + 0x21 */ |
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| 382 | volatile uint8_t res19; /* + 0x22 */ |
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| 383 | volatile uint8_t res20; /* + 0x23 */ |
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| 384 | volatile uint8_t idar2; /* + 0x24 */ |
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| 385 | volatile uint8_t idar3; /* + 0x25 */ |
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| 386 | volatile uint8_t res21; /* + 0x26 */ |
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| 387 | volatile uint8_t res22; /* + 0x27 */ |
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| 388 | volatile uint8_t idmr0; /* + 0x28 */ |
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| 389 | volatile uint8_t idmr1; /* + 0x29 */ |
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| 390 | volatile uint8_t res23; /* + 0x2A */ |
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| 391 | volatile uint8_t res24; /* + 0x2B */ |
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| 392 | volatile uint8_t idmr2; /* + 0x2C */ |
---|
| 393 | volatile uint8_t idmr3; /* + 0x2D */ |
---|
| 394 | volatile uint8_t res25; /* + 0x2E */ |
---|
| 395 | volatile uint8_t res26; /* + 0x2F */ |
---|
| 396 | volatile uint8_t idar4; /* + 0x30 */ |
---|
| 397 | volatile uint8_t idar5; /* + 0x31 */ |
---|
| 398 | volatile uint8_t res27; /* + 0x32 */ |
---|
| 399 | volatile uint8_t res28; /* + 0x33 */ |
---|
| 400 | volatile uint8_t idar6; /* + 0x34 */ |
---|
| 401 | volatile uint8_t idar7; /* + 0x35 */ |
---|
| 402 | volatile uint8_t res29; /* + 0x36 */ |
---|
| 403 | volatile uint8_t res30; /* + 0x37 */ |
---|
| 404 | volatile uint8_t idmr4; /* + 0x38 */ |
---|
| 405 | volatile uint8_t idmr5; /* + 0x39 */ |
---|
| 406 | volatile uint8_t res31; /* + 0x3A */ |
---|
| 407 | volatile uint8_t res32; /* + 0x3B */ |
---|
| 408 | volatile uint8_t idmr6; /* + 0x3C */ |
---|
| 409 | volatile uint8_t idmr7; /* + 0x3D */ |
---|
| 410 | volatile uint8_t res33; /* + 0x3E */ |
---|
| 411 | volatile uint8_t res34; /* + 0x3F */ |
---|
| 412 | volatile uint8_t rxidr0; /* + 0x40 */ |
---|
| 413 | volatile uint8_t rxidr1; /* + 0x41 */ |
---|
| 414 | volatile uint8_t res35; /* + 0x42 */ |
---|
| 415 | volatile uint8_t res36; /* + 0x43 */ |
---|
| 416 | volatile uint8_t rxidr2; /* + 0x44 */ |
---|
| 417 | volatile uint8_t rxidr3; /* + 0x45 */ |
---|
| 418 | volatile uint8_t res37; /* + 0x46 */ |
---|
| 419 | volatile uint8_t res38; /* + 0x47 */ |
---|
| 420 | volatile uint8_t rxdsr0; /* + 0x48 */ |
---|
| 421 | volatile uint8_t rxdsr1; /* + 0x49 */ |
---|
| 422 | volatile uint8_t res39; /* + 0x4A */ |
---|
| 423 | volatile uint8_t res40; /* + 0x4B */ |
---|
| 424 | volatile uint8_t rxdsr2; /* + 0x4C */ |
---|
| 425 | volatile uint8_t rxdsr3; /* + 0x4D */ |
---|
| 426 | volatile uint8_t res41; /* + 0x4E */ |
---|
| 427 | volatile uint8_t res42; /* + 0x4F */ |
---|
| 428 | volatile uint8_t rxdsr4; /* + 0x50 */ |
---|
| 429 | volatile uint8_t rxdsr5; /* + 0x51 */ |
---|
| 430 | volatile uint8_t res43; /* + 0x52 */ |
---|
| 431 | volatile uint8_t res44; /* + 0x53 */ |
---|
| 432 | volatile uint8_t rxdsr6; /* + 0x54 */ |
---|
| 433 | volatile uint8_t rxdsr7; /* + 0x55 */ |
---|
| 434 | volatile uint8_t res45; /* + 0x56 */ |
---|
| 435 | volatile uint8_t res46; /* + 0x57 */ |
---|
| 436 | volatile uint8_t rxdlr; /* + 0x58 */ |
---|
| 437 | volatile uint8_t res47; /* + 0x59 */ |
---|
| 438 | volatile uint8_t res48; /* + 0x5A */ |
---|
| 439 | volatile uint8_t res49; /* + 0x5B */ |
---|
| 440 | volatile uint8_t rxtimh; /* + 0x5C */ |
---|
| 441 | volatile uint8_t rxtiml; /* + 0x5D */ |
---|
| 442 | volatile uint8_t res50; /* + 0x5E */ |
---|
| 443 | volatile uint8_t res51; /* + 0x5F */ |
---|
| 444 | volatile uint8_t txidr0; /* + 0x60 */ |
---|
| 445 | volatile uint8_t txidr1; /* + 0x61 */ |
---|
| 446 | volatile uint8_t res52; /* + 0x62 */ |
---|
| 447 | volatile uint8_t res53; /* + 0x63 */ |
---|
| 448 | volatile uint8_t txidr2; /* + 0x64 */ |
---|
| 449 | volatile uint8_t txidr3; /* + 0x65 */ |
---|
| 450 | volatile uint8_t res54; /* + 0x66 */ |
---|
| 451 | volatile uint8_t res55; /* + 0x67 */ |
---|
| 452 | volatile uint8_t txdsr0; /* + 0x68 */ |
---|
| 453 | volatile uint8_t txdsr1; /* + 0x69 */ |
---|
| 454 | volatile uint8_t res56; /* + 0x6A */ |
---|
| 455 | volatile uint8_t res57; /* + 0x6B */ |
---|
| 456 | volatile uint8_t txdsr2; /* + 0x6C */ |
---|
| 457 | volatile uint8_t txdsr3; /* + 0x6D */ |
---|
| 458 | volatile uint8_t res58; /* + 0x6E */ |
---|
| 459 | volatile uint8_t res59; /* + 0x6F */ |
---|
| 460 | volatile uint8_t txdsr4; /* + 0x70 */ |
---|
| 461 | volatile uint8_t txdsr5; /* + 0x71 */ |
---|
| 462 | volatile uint8_t res60; /* + 0x72 */ |
---|
| 463 | volatile uint8_t res61; /* + 0x73 */ |
---|
| 464 | volatile uint8_t txdsr6; /* + 0x74 */ |
---|
| 465 | volatile uint8_t txdsr7; /* + 0x75 */ |
---|
| 466 | volatile uint8_t res62; /* + 0x76 */ |
---|
| 467 | volatile uint8_t res63; /* + 0x77 */ |
---|
| 468 | volatile uint8_t txdlr; /* + 0x78 */ |
---|
| 469 | volatile uint8_t txtbpr; /* + 0x79 */ |
---|
| 470 | volatile uint8_t res64; /* + 0x7A */ |
---|
| 471 | volatile uint8_t res65; /* + 0x7B */ |
---|
| 472 | volatile uint8_t txtimh; /* + 0x7C */ |
---|
| 473 | volatile uint8_t txtiml; /* + 0x7D */ |
---|
| 474 | volatile uint8_t res66; /* + 0x7E */ |
---|
| 475 | volatile uint8_t res67; /* + 0x7F */ |
---|
| 476 | } mscan[MPC5200_CAN_NO]; |
---|
| 477 | |
---|
| 478 | volatile uint8_t res[0x100]; |
---|
| 479 | |
---|
| 480 | /* |
---|
| 481 | * GPIO standard registers (MBAR + 0xB00) |
---|
| 482 | */ |
---|
| 483 | volatile uint32_t gpiopcr; /* + 0x00 */ |
---|
| 484 | volatile uint32_t gpiosen; /* + 0x04 */ |
---|
| 485 | volatile uint32_t gpiosod; /* + 0x08 */ |
---|
| 486 | volatile uint32_t gpiosdd; /* + 0x0C */ |
---|
| 487 | volatile uint32_t gpiosdo; /* + 0x10 */ |
---|
| 488 | volatile uint32_t gpiosdi; /* + 0x14 */ |
---|
| 489 | volatile uint32_t gpiooe; /* + 0x18 */ |
---|
| 490 | volatile uint32_t gpioodo; /* + 0x1C */ |
---|
| 491 | volatile uint32_t gpiosie; /* + 0x20 */ |
---|
| 492 | volatile uint32_t gpiosiod; /* + 0x24 */ |
---|
| 493 | volatile uint32_t gpiosidd; /* + 0x28 */ |
---|
| 494 | volatile uint32_t gpiosido; /* + 0x2C */ |
---|
| 495 | volatile uint32_t gpiosiie; /* + 0x30 */ |
---|
| 496 | volatile uint32_t gpiosiit; /* + 0x34 */ |
---|
| 497 | volatile uint32_t gpiosime; /* + 0x38 */ |
---|
| 498 | volatile uint32_t gpiosist; /* + 0x3C */ |
---|
| 499 | volatile uint8_t res4[0xC0]; |
---|
| 500 | |
---|
| 501 | /* |
---|
| 502 | * GPIO wakeup registers (MBAR + 0xC00) |
---|
| 503 | */ |
---|
| 504 | volatile uint32_t gpiowe; /* + 0x00 */ |
---|
| 505 | volatile uint32_t gpiowod; /* + 0x04 */ |
---|
| 506 | volatile uint32_t gpiowdd; /* + 0x08 */ |
---|
| 507 | volatile uint32_t gpiowdo; /* + 0x0C */ |
---|
| 508 | volatile uint32_t gpiowue; /* + 0x10 */ |
---|
| 509 | volatile uint32_t gpiowsie; /* + 0x14 */ |
---|
| 510 | volatile uint32_t gpiowt; /* + 0x18 */ |
---|
| 511 | volatile uint32_t gpiowme; /* + 0x1C */ |
---|
| 512 | volatile uint32_t gpiowi; /* + 0x20 */ |
---|
| 513 | volatile uint32_t gpiows; /* + 0x24 */ |
---|
| 514 | volatile uint8_t gpiow_res[0xD8]; |
---|
| 515 | |
---|
| 516 | /* |
---|
| 517 | * PPC PCI registers (MBAR + 0xD00) |
---|
| 518 | */ |
---|
| 519 | volatile uint8_t ppci[0x100]; |
---|
| 520 | |
---|
| 521 | /* |
---|
| 522 | * consumer infrared registers (MBAR + 0xE00) |
---|
| 523 | */ |
---|
| 524 | volatile uint8_t ir[0x100]; |
---|
| 525 | |
---|
| 526 | /* |
---|
| 527 | * serial peripheral interface registers (MBAR + 0xF00) |
---|
| 528 | */ |
---|
| 529 | volatile uint8_t spi[0x100]; |
---|
| 530 | |
---|
| 531 | /* |
---|
| 532 | * universal serial bus registers (MBAR + 0x1000) |
---|
| 533 | */ |
---|
| 534 | volatile uint8_t usb[0x200]; |
---|
| 535 | |
---|
| 536 | /* |
---|
| 537 | * SmartComm DMA registers (MBAR + 0x1200) |
---|
| 538 | */ |
---|
| 539 | volatile uint32_t taskBar; /* + 0x00 sdTpb */ |
---|
| 540 | volatile uint32_t currentPointer; /* + 0x04 sdMdeComplex */ |
---|
| 541 | volatile uint32_t endPointer; /* + 0x08 sdMdeComplex */ |
---|
| 542 | volatile uint32_t variablePointer; /* + 0x0c sdMdeComplex */ |
---|
| 543 | |
---|
| 544 | /* |
---|
| 545 | * The following are Priority Task Decoder (ptd) regs in sdma/rtl_v/sdPtd.v. |
---|
| 546 | * The ptd register map below is from the smartcomm spec, table 3-2, page 3-54. |
---|
| 547 | * The spec shows the ptd map as 20 words, but sdPtd.v has only implemented 19. |
---|
| 548 | * The word commented out below is the one which is not implemented. |
---|
| 549 | */ |
---|
| 550 | |
---|
[c5feb602] | 551 | /* volatile uint8_t IntVect; */ /* |
---|
[ca680bc5] | 552 | * + 0xXX sdPtd read only |
---|
| 553 | */ |
---|
| 554 | |
---|
[c5feb602] | 555 | /* volatile uint8_t res0[3]; */ /* |
---|
[ca680bc5] | 556 | * + 0xXX sdPtd read only |
---|
| 557 | */ |
---|
| 558 | volatile uint8_t IntVect1; /* + 0x10 sdPtd */ |
---|
| 559 | volatile uint8_t IntVect2; /* + 0x11 sdPtd */ |
---|
| 560 | volatile uint16_t PtdCntrl; /* + 0x12 sdPtd */ |
---|
| 561 | |
---|
| 562 | volatile uint32_t IntPend; /* + 0x14 sdPtd */ |
---|
| 563 | volatile uint32_t IntMask; /* + 0x18 sdPtd */ |
---|
| 564 | |
---|
| 565 | volatile uint32_t TCR01; /* + 0x1c sdPtd */ |
---|
| 566 | volatile uint32_t TCR23; /* + 0x20 sdPtd */ |
---|
| 567 | volatile uint32_t TCR45; /* + 0x24 sdPtd */ |
---|
| 568 | volatile uint32_t TCR67; /* + 0x28 sdPtd */ |
---|
| 569 | volatile uint32_t TCR89; /* + 0x2c sdPtd */ |
---|
| 570 | volatile uint32_t TCRAB; /* + 0x30 sdPtd */ |
---|
| 571 | volatile uint32_t TCRCD; /* + 0x34 sdPtd */ |
---|
| 572 | volatile uint32_t TCREF; /* + 0x38 sdPtd */ |
---|
| 573 | |
---|
| 574 | volatile uint8_t IPR0; /* + 0x3c sdPtd */ |
---|
| 575 | volatile uint8_t IPR1; /* + 0x3d sdPtd */ |
---|
| 576 | volatile uint8_t IPR2; /* + 0x3e sdPtd */ |
---|
| 577 | volatile uint8_t IPR3; /* + 0x3f sdPtd */ |
---|
| 578 | volatile uint8_t IPR4; /* + 0x40 sdPtd */ |
---|
| 579 | volatile uint8_t IPR5; /* + 0x41 sdPtd */ |
---|
| 580 | volatile uint8_t IPR6; /* + 0x42 sdPtd */ |
---|
| 581 | volatile uint8_t IPR7; /* + 0x43 sdPtd */ |
---|
| 582 | volatile uint8_t IPR8; /* + 0x44 sdPtd */ |
---|
| 583 | volatile uint8_t IPR9; /* + 0x45 sdPtd */ |
---|
| 584 | volatile uint8_t IPR10; /* + 0x46 sdPtd */ |
---|
| 585 | volatile uint8_t IPR11; /* + 0x47 sdPtd */ |
---|
| 586 | volatile uint8_t IPR12; /* + 0x48 sdPtd */ |
---|
| 587 | volatile uint8_t IPR13; /* + 0x49 sdPtd */ |
---|
| 588 | volatile uint8_t IPR14; /* + 0x4a sdPtd */ |
---|
| 589 | volatile uint8_t IPR15; /* + 0x4b sdPtd */ |
---|
| 590 | volatile uint8_t IPR16; /* + 0x4c sdPtd */ |
---|
| 591 | volatile uint8_t IPR17; /* + 0x4d sdPtd */ |
---|
| 592 | volatile uint8_t IPR18; /* + 0x4e sdPtd */ |
---|
| 593 | volatile uint8_t IPR19; /* + 0x4f sdPtd */ |
---|
| 594 | volatile uint8_t IPR20; /* + 0x50 sdPtd */ |
---|
| 595 | volatile uint8_t IPR21; /* + 0x51 sdPtd */ |
---|
| 596 | volatile uint8_t IPR22; /* + 0x52 sdPtd */ |
---|
| 597 | volatile uint8_t IPR23; /* + 0x53 sdPtd */ |
---|
| 598 | volatile uint8_t IPR24; /* + 0x54 sdPtd */ |
---|
| 599 | volatile uint8_t IPR25; /* + 0x55 sdPtd */ |
---|
| 600 | volatile uint8_t IPR26; /* + 0x56 sdPtd */ |
---|
| 601 | volatile uint8_t IPR27; /* + 0x57 sdPtd */ |
---|
| 602 | volatile uint8_t IPR28; /* + 0x58 sdPtd */ |
---|
| 603 | volatile uint8_t IPR29; /* + 0x59 sdPtd */ |
---|
| 604 | volatile uint8_t IPR30; /* + 0x5a sdPtd */ |
---|
| 605 | volatile uint8_t IPR31; /* + 0x5b sdPtd */ |
---|
| 606 | |
---|
| 607 | volatile uint32_t res5; /* reserved */ |
---|
| 608 | volatile uint32_t res6; /* reserved */ |
---|
| 609 | volatile uint32_t res7; /* reserved */ |
---|
| 610 | volatile uint32_t MDEDebug; /* + 0x68 sdMdeComplex */ |
---|
| 611 | volatile uint32_t ADSDebug; /* + 0x6c sdAdsTop */ |
---|
| 612 | volatile uint32_t Value1; /* + 0x70 sdDbg */ |
---|
| 613 | volatile uint32_t Value2; /* + 0x74 sdDbg */ |
---|
| 614 | volatile uint32_t Control; /* + 0x78 sdDbg */ |
---|
| 615 | volatile uint32_t Status; /* + 0x7c sdDbg */ |
---|
| 616 | volatile uint32_t EU00; /* + 0x80 sdMac macer reg */ |
---|
| 617 | volatile uint32_t EU01; /* + 0x84 sdMac macemr reg */ |
---|
| 618 | volatile uint32_t EU02; /* + 0x88 unused */ |
---|
| 619 | volatile uint32_t EU03; /* + 0x8c unused */ |
---|
| 620 | volatile uint32_t EU04; /* + 0x90 unused */ |
---|
| 621 | volatile uint32_t EU05; /* + 0x94 unused */ |
---|
| 622 | volatile uint32_t EU06; /* + 0x98 unused */ |
---|
| 623 | volatile uint32_t EU07; /* + 0x9c unused */ |
---|
| 624 | volatile uint32_t EU10; /* + 0xa0 unused */ |
---|
| 625 | volatile uint32_t EU11; /* + 0xa4 unused */ |
---|
| 626 | volatile uint32_t EU12; /* + 0xa8 unused */ |
---|
| 627 | volatile uint32_t EU13; /* + 0xac unused */ |
---|
| 628 | volatile uint32_t EU14; /* + 0xb0 unused */ |
---|
| 629 | volatile uint32_t EU15; /* + 0xb4 unused */ |
---|
| 630 | volatile uint32_t EU16; /* + 0xb8 unused */ |
---|
| 631 | volatile uint32_t EU17; /* + 0xbc unused */ |
---|
| 632 | volatile uint32_t EU20; /* + 0xc0 unused */ |
---|
| 633 | volatile uint32_t EU21; /* + 0xc4 unused */ |
---|
| 634 | volatile uint32_t EU22; /* + 0xc8 unused */ |
---|
| 635 | volatile uint32_t EU23; /* + 0xcc unused */ |
---|
| 636 | volatile uint32_t EU24; /* + 0xd0 unused */ |
---|
| 637 | volatile uint32_t EU25; /* + 0xd4 unused */ |
---|
| 638 | volatile uint32_t EU26; /* + 0xd8 unused */ |
---|
| 639 | volatile uint32_t EU27; /* + 0xdc unused */ |
---|
| 640 | volatile uint32_t EU30; /* + 0xe0 unused */ |
---|
| 641 | volatile uint32_t EU31; /* + 0xe4 unused */ |
---|
| 642 | volatile uint32_t EU32; /* + 0xe8 unused */ |
---|
| 643 | volatile uint32_t EU33; /* + 0xec unused */ |
---|
| 644 | volatile uint32_t EU34; /* + 0xf0 unused */ |
---|
| 645 | volatile uint32_t EU35; /* + 0xf4 unused */ |
---|
| 646 | volatile uint32_t EU36; /* + 0xf8 unused */ |
---|
| 647 | volatile uint32_t EU37; /* + 0xfc unused */ |
---|
| 648 | #if 0 |
---|
| 649 | volatile uint32_t res8[0x340]; |
---|
| 650 | #else |
---|
| 651 | volatile uint8_t res_1300[0xc00]; |
---|
| 652 | |
---|
| 653 | volatile uint32_t reserved0; /* MBAR_XLB_ARB + 0x0000 reserved */ |
---|
| 654 | volatile uint32_t reserved1; /* MBAR_XLB_ARB + 0x0004 reserved */ |
---|
| 655 | volatile uint32_t reserved2; /* MBAR_XLB_ARB + 0x0008 reserved */ |
---|
| 656 | volatile uint32_t reserved3; /* MBAR_XLB_ARB + 0x000c reserved */ |
---|
| 657 | volatile uint32_t reserved4; /* MBAR_XLB_ARB + 0x0010 reserved */ |
---|
| 658 | volatile uint32_t reserved5; /* MBAR_XLB_ARB + 0x0014 reserved */ |
---|
| 659 | volatile uint32_t reserved6; /* MBAR_XLB_ARB + 0x0018 reserved */ |
---|
| 660 | volatile uint32_t reserved7; /* MBAR_XLB_ARB + 0x001c reserved */ |
---|
| 661 | volatile uint32_t reserved8; /* MBAR_XLB_ARB + 0x0020 reserved */ |
---|
| 662 | volatile uint32_t reserved9; /* MBAR_XLB_ARB + 0x0024 reserved */ |
---|
| 663 | volatile uint32_t reserved10; /* MBAR_XLB_ARB + 0x0028 reserved */ |
---|
| 664 | volatile uint32_t reserved11; /* MBAR_XLB_ARB + 0x002c reserved */ |
---|
| 665 | volatile uint32_t reserved12; /* MBAR_XLB_ARB + 0x0030 reserved */ |
---|
| 666 | volatile uint32_t reserved13; /* MBAR_XLB_ARB + 0x0034 reserved */ |
---|
| 667 | volatile uint32_t reserved14; /* MBAR_XLB_ARB + 0x0038 reserved */ |
---|
| 668 | volatile uint32_t reserved15; /* MBAR_XLB_ARB + 0x003c reserved */ |
---|
| 669 | |
---|
| 670 | volatile uint32_t config; /* MBAR_XLB_ARB + 0x0040 */ |
---|
| 671 | volatile uint32_t version; /* MBAR_XLB_ARB + 0x0044 read only = 0x0001 */ |
---|
| 672 | volatile uint32_t xlb_status; /* MBAR_XLB_ARB + 0x0048 */ |
---|
| 673 | volatile uint32_t int_enable; /* MBAR_XLB_ARB + 0x004c */ |
---|
| 674 | volatile uint32_t add_capture; /* MBAR_XLB_ARB + 0x0050 read only */ |
---|
| 675 | volatile uint32_t bus_sig_capture; /* MBAR_XLB_ARB + 0x0054 read only */ |
---|
| 676 | volatile uint32_t add_time_out; /* MBAR_XLB_ARB + 0x0058 */ |
---|
| 677 | volatile uint32_t data_time_out; /* MBAR_XLB_ARB + 0x005c */ |
---|
| 678 | volatile uint32_t bus_time_out; /* MBAR_XLB_ARB + 0x0060 */ |
---|
| 679 | volatile uint32_t priority_enable; /* MBAR_XLB_ARB + 0x0064 */ |
---|
| 680 | volatile uint32_t priority; /* MBAR_XLB_ARB + 0x0068 */ |
---|
| 681 | volatile uint32_t arb_base_addr2; /* MBAR_XLB_ARB + 0x006c */ |
---|
| 682 | volatile uint32_t snoop_window; /* MBAR_XLB_ARB + 0x0070 */ |
---|
| 683 | |
---|
| 684 | volatile uint32_t reserved16; /* MBAR_XLB_ARB + 0x0074 reserved */ |
---|
| 685 | volatile uint32_t reserved17; /* MBAR_XLB_ARB + 0x0078 reserved */ |
---|
| 686 | volatile uint32_t reserved18; /* MBAR_XLB_ARB + 0x007c reserved */ |
---|
| 687 | |
---|
| 688 | volatile uint32_t control; /* MBAR_XLB_ARB + 0x0080 */ |
---|
| 689 | volatile uint32_t init_total_count; /* MBAR_XLB_ARB + 0x0084 */ |
---|
| 690 | volatile uint32_t int_total_count; /* MBAR_XLB_ARB + 0x0088 */ |
---|
| 691 | |
---|
| 692 | volatile uint32_t reserved19; /* MBAR_XLB_ARB + 0x008c reserved */ |
---|
| 693 | |
---|
| 694 | volatile uint32_t lower_address; /* MBAR_XLB_ARB + 0x0090 */ |
---|
| 695 | volatile uint32_t higher_address; /* MBAR_XLB_ARB + 0x0094 */ |
---|
| 696 | volatile uint32_t int_window_count; /* MBAR_XLB_ARB + 0x0098 */ |
---|
| 697 | volatile uint32_t window_ter_count; /* MBAR_XLB_ARB + 0x009c */ |
---|
| 698 | volatile uint8_t res_0x1fa0[0x60]; |
---|
| 699 | |
---|
| 700 | |
---|
| 701 | #endif |
---|
[7da3405] | 702 | /* |
---|
[ca680bc5] | 703 | * programmable serial controller 1 (MBAR + 0x2000) |
---|
| 704 | */ |
---|
| 705 | |
---|
| 706 | struct mpc5200_psc |
---|
| 707 | { |
---|
| 708 | volatile uint8_t mr; /* +0x00 */ |
---|
| 709 | volatile uint8_t res1[3]; |
---|
| 710 | volatile uint16_t sr_csr; /* +0x04 */ |
---|
| 711 | volatile uint16_t res2[1]; |
---|
| 712 | volatile uint16_t cr; /* +0x08 */ |
---|
| 713 | volatile uint16_t res3[1]; |
---|
| 714 | volatile uint32_t rb_tb; /* +0x0c */ |
---|
| 715 | volatile uint16_t ipcr_acr; /* +0x10 */ |
---|
| 716 | volatile uint16_t res4[1]; |
---|
| 717 | volatile uint16_t isr_imr; /* +0x14 */ |
---|
| 718 | #define ISR_TX_RDY (1 << 8) |
---|
| 719 | #define ISR_RX_RDY_FULL (1 << 9) |
---|
| 720 | #define ISR_RB (1 << 15) |
---|
| 721 | #define ISR_FE (1 << 14) |
---|
| 722 | #define ISR_PE (1 << 13) |
---|
| 723 | #define ISR_OE (1 << 12) |
---|
| 724 | #define ISR_ERROR (ISR_FE | ISR_PE | ISR_OE) |
---|
| 725 | |
---|
| 726 | #define IMR_TX_RDY (1 << 8) |
---|
| 727 | #define IMR_RX_RDY_FULL (1 << 9) |
---|
| 728 | volatile uint16_t res5[1]; |
---|
| 729 | volatile uint8_t ctur; /* +0x18 */ |
---|
| 730 | volatile uint8_t res6[3]; |
---|
| 731 | volatile uint8_t ctlr; /* +0x1C */ |
---|
| 732 | volatile uint8_t res7[0x13]; |
---|
| 733 | volatile uint8_t ivr; /* +0x30 */ |
---|
| 734 | volatile uint8_t res8[3]; |
---|
| 735 | volatile uint8_t ip; /* +0x34 */ |
---|
| 736 | volatile uint8_t res9[3]; |
---|
| 737 | volatile uint8_t op1; /* +0x38 */ |
---|
| 738 | volatile uint8_t res10[3]; |
---|
| 739 | volatile uint8_t op0; /* +0x3C */ |
---|
| 740 | volatile uint8_t res11[3]; |
---|
| 741 | volatile uint8_t sicr; /* +0x40 */ |
---|
| 742 | volatile uint8_t res12[0x17]; |
---|
| 743 | volatile uint16_t rfnum; /* +0x58 */ |
---|
| 744 | volatile uint16_t res13[1]; |
---|
| 745 | volatile uint16_t tfnum; /* +0x5C */ |
---|
| 746 | volatile uint16_t res14[1]; |
---|
| 747 | volatile uint16_t rfdata; /* +0x60 */ |
---|
| 748 | volatile uint16_t res15[1]; |
---|
| 749 | volatile uint16_t rfstat; /* +0x64 */ |
---|
| 750 | volatile uint16_t res16[1]; |
---|
| 751 | volatile uint8_t rfcntl; /* +0x68 */ |
---|
| 752 | volatile uint8_t res17[5]; |
---|
| 753 | volatile uint16_t rfalarm; /* +0x6E */ |
---|
| 754 | volatile uint8_t res18[2]; |
---|
| 755 | volatile uint16_t rfrptr; /* +0x72 */ |
---|
| 756 | volatile uint16_t res19[1]; |
---|
| 757 | volatile uint16_t rfwptr; /* +0x76 */ |
---|
| 758 | volatile uint16_t res20[1]; |
---|
| 759 | volatile uint16_t rflrfptr; /* +0x7A */ |
---|
| 760 | volatile uint16_t rflwfptr; /* +0x7C */ |
---|
| 761 | volatile uint16_t res21[1]; |
---|
| 762 | volatile uint16_t tfdata; /* +0x80 */ |
---|
| 763 | volatile uint16_t res22[1]; |
---|
| 764 | volatile uint16_t tfstat; /* +0x84 */ |
---|
| 765 | volatile uint16_t res23[1]; |
---|
| 766 | volatile uint8_t tfcntl; /* +0x88 */ |
---|
| 767 | volatile uint8_t res24[5]; |
---|
| 768 | volatile uint16_t tfalarm; /* +0x8E */ |
---|
| 769 | volatile uint8_t res25[2]; |
---|
| 770 | volatile uint16_t tfrptr; /* +0x92 */ |
---|
| 771 | volatile uint16_t res26[1]; |
---|
| 772 | volatile uint16_t tfwptr; /* +0x96 */ |
---|
| 773 | volatile uint16_t res27[1]; |
---|
| 774 | volatile uint16_t tflrfptr; /* +0x96 */ |
---|
| 775 | volatile uint16_t tflwfptr; /* +0x9C */ |
---|
| 776 | volatile uint16_t res28[1]; /* end at offset 0x9F */ |
---|
| 777 | volatile uint8_t res29[0x160]; |
---|
| 778 | } psc[MPC5200_PSC_REG_SETS]; |
---|
| 779 | /* XXX: there are only 6 PSCs, but PSC6 has an extra register gap |
---|
| 780 | * from PSC5, therefore we instantiate seven(!) PSC register sets |
---|
| 781 | */ |
---|
| 782 | |
---|
| 783 | #define TX_FIFO_SIZE 256 |
---|
| 784 | #define RX_FIFO_SIZE 512 |
---|
| 785 | |
---|
| 786 | |
---|
| 787 | volatile uint8_t irda[0x200]; |
---|
| 788 | |
---|
| 789 | /* |
---|
| 790 | * ethernet registers (MBAR + 0x3000) |
---|
| 791 | */ |
---|
| 792 | |
---|
| 793 | /* Control and status Registers (offset 000-1FF) */ |
---|
| 794 | |
---|
| 795 | volatile uint32_t fec_id; /* + 0x000 */ |
---|
| 796 | volatile uint32_t ievent; /* + 0x004 */ |
---|
| 797 | volatile uint32_t imask; /* + 0x008 */ |
---|
| 798 | |
---|
| 799 | volatile uint32_t res9[1]; /* + 0x00C */ |
---|
| 800 | volatile uint32_t r_des_active; /* + 0x010 */ |
---|
| 801 | volatile uint32_t x_des_active; /* + 0x014 */ |
---|
| 802 | volatile uint32_t r_des_active_cl; /* + 0x018 */ |
---|
| 803 | volatile uint32_t x_des_active_cl; /* + 0x01C */ |
---|
| 804 | volatile uint32_t ivent_set; /* + 0x020 */ |
---|
| 805 | volatile uint32_t ecntrl; /* + 0x024 */ |
---|
| 806 | |
---|
| 807 | volatile uint32_t res10[6]; /* + 0x028-03C */ |
---|
| 808 | volatile uint32_t mii_data; /* + 0x040 */ |
---|
| 809 | volatile uint32_t mii_speed; /* + 0x044 */ |
---|
| 810 | volatile uint32_t mii_status; /* + 0x048 */ |
---|
| 811 | |
---|
| 812 | volatile uint32_t res11[5]; /* + 0x04C-05C */ |
---|
| 813 | volatile uint32_t mib_data; /* + 0x060 */ |
---|
| 814 | volatile uint32_t mib_control; /* + 0x064 */ |
---|
| 815 | |
---|
| 816 | volatile uint32_t res12[6]; /* + 0x068-7C */ |
---|
| 817 | volatile uint32_t r_activate; /* + 0x080 */ |
---|
| 818 | volatile uint32_t r_cntrl; /* + 0x084 */ |
---|
| 819 | volatile uint32_t r_hash; /* + 0x088 */ |
---|
| 820 | volatile uint32_t r_data; /* + 0x08C */ |
---|
| 821 | volatile uint32_t ar_done; /* + 0x090 */ |
---|
| 822 | volatile uint32_t r_test; /* + 0x094 */ |
---|
| 823 | volatile uint32_t r_mib; /* + 0x098 */ |
---|
| 824 | volatile uint32_t r_da_low; /* + 0x09C */ |
---|
| 825 | volatile uint32_t r_da_high; /* + 0x0A0 */ |
---|
| 826 | |
---|
| 827 | volatile uint32_t res13[7]; /* + 0x0A4-0BC */ |
---|
| 828 | volatile uint32_t x_activate; /* + 0x0C0 */ |
---|
| 829 | volatile uint32_t x_cntrl; /* + 0x0C4 */ |
---|
| 830 | volatile uint32_t backoff; /* + 0x0C8 */ |
---|
| 831 | volatile uint32_t x_data; /* + 0x0CC */ |
---|
| 832 | volatile uint32_t x_status; /* + 0x0D0 */ |
---|
| 833 | volatile uint32_t x_mib; /* + 0x0D4 */ |
---|
| 834 | volatile uint32_t x_test; /* + 0x0D8 */ |
---|
| 835 | volatile uint32_t fdxfc_da1; /* + 0x0DC */ |
---|
| 836 | volatile uint32_t fdxfc_da2; /* + 0x0E0 */ |
---|
| 837 | volatile uint32_t paddr1; /* + 0x0E4 */ |
---|
| 838 | volatile uint32_t paddr2; /* + 0x0E8 */ |
---|
| 839 | volatile uint32_t op_pause; /* + 0x0EC */ |
---|
| 840 | |
---|
| 841 | volatile uint32_t res14[4]; /* + 0x0F0-0FC */ |
---|
| 842 | volatile uint32_t instr_reg; /* + 0x100 */ |
---|
| 843 | volatile uint32_t context_reg; /* + 0x104 */ |
---|
| 844 | volatile uint32_t test_cntrl; /* + 0x108 */ |
---|
| 845 | volatile uint32_t acc_reg; /* + 0x10C */ |
---|
| 846 | volatile uint32_t ones; /* + 0x110 */ |
---|
| 847 | volatile uint32_t zeros; /* + 0x114 */ |
---|
| 848 | volatile uint32_t iaddr1; /* + 0x118 */ |
---|
| 849 | volatile uint32_t iaddr2; /* + 0x11C */ |
---|
| 850 | volatile uint32_t gaddr1; /* + 0x120 */ |
---|
| 851 | volatile uint32_t gaddr2; /* + 0x124 */ |
---|
| 852 | volatile uint32_t random; /* + 0x128 */ |
---|
| 853 | volatile uint32_t rand1; /* + 0x12C */ |
---|
| 854 | volatile uint32_t tmp; /* + 0x130 */ |
---|
| 855 | |
---|
| 856 | volatile uint32_t res15[3]; /* + 0x134-13C */ |
---|
| 857 | volatile uint32_t fifo_id; /* + 0x140 */ |
---|
| 858 | volatile uint32_t x_wmrk; /* + 0x144 */ |
---|
| 859 | volatile uint32_t fcntrl; /* + 0x148 */ |
---|
| 860 | volatile uint32_t r_bound; /* + 0x14C */ |
---|
| 861 | volatile uint32_t r_fstart; /* + 0x150 */ |
---|
| 862 | volatile uint32_t r_count; /* + 0x154 */ |
---|
| 863 | volatile uint32_t r_lag; /* + 0x158 */ |
---|
| 864 | volatile uint32_t r_read; /* + 0x15C */ |
---|
| 865 | volatile uint32_t r_write; /* + 0x160 */ |
---|
| 866 | volatile uint32_t x_count; /* + 0x164 */ |
---|
| 867 | volatile uint32_t x_lag; /* + 0x168 */ |
---|
| 868 | volatile uint32_t x_retry; /* + 0x16C */ |
---|
| 869 | volatile uint32_t x_write; /* + 0x170 */ |
---|
| 870 | volatile uint32_t x_read; /* + 0x174 */ |
---|
| 871 | |
---|
| 872 | volatile uint32_t res16[2]; /* + 0x178-17C */ |
---|
| 873 | volatile uint32_t fm_cntrl; /* + 0x180 */ |
---|
| 874 | volatile uint32_t rfifo_data; /* + 0x184 */ |
---|
| 875 | volatile uint32_t rfifo_status; /* + 0x188 */ |
---|
| 876 | volatile uint32_t rfifo_cntrl; /* + 0x18C */ |
---|
| 877 | volatile uint32_t rfifo_lrf_ptr; /* + 0x190 */ |
---|
| 878 | volatile uint32_t rfifo_lwf_ptr; /* + 0x194 */ |
---|
| 879 | volatile uint32_t rfifo_alarm; /* + 0x198 */ |
---|
| 880 | volatile uint32_t rfifo_rdptr; /* + 0x19C */ |
---|
| 881 | volatile uint32_t rfifo_wrptr; /* + 0x1A0 */ |
---|
| 882 | volatile uint32_t tfifo_data; /* + 0x1A4 */ |
---|
| 883 | volatile uint32_t tfifo_status; /* + 0x1A8 */ |
---|
| 884 | volatile uint32_t tfifo_cntrl; /* + 0x1AC */ |
---|
| 885 | volatile uint32_t tfifo_lrf_ptr; /* + 0x1B0 */ |
---|
| 886 | volatile uint32_t tfifo_lwf_ptr; /* + 0x1B4 */ |
---|
| 887 | volatile uint32_t tfifo_alarm; /* + 0x1B8 */ |
---|
| 888 | volatile uint32_t tfifo_rdptr; /* + 0x1BC */ |
---|
| 889 | volatile uint32_t tfifo_wrptr; /* + 0x1C0 */ |
---|
| 890 | |
---|
| 891 | volatile uint32_t reset_cntrl; /* + 0x1C4 */ |
---|
| 892 | volatile uint32_t xmit_fsm; /* + 0x1C8 */ |
---|
| 893 | |
---|
| 894 | volatile uint32_t res17[3]; /* + 0x1CC-1D4 */ |
---|
| 895 | volatile uint32_t rdes_data0; /* + 0x1D8 */ |
---|
| 896 | volatile uint32_t rdes_data1; /* + 0x1DC */ |
---|
| 897 | volatile uint32_t r_length; /* + 0x1E0 */ |
---|
| 898 | volatile uint32_t x_length; /* + 0x1E4 */ |
---|
| 899 | volatile uint32_t x_addr; /* + 0x1E8 */ |
---|
| 900 | volatile uint32_t cdes_data; /* + 0x1EC */ |
---|
| 901 | volatile uint32_t status; /* + 0x1F0 */ |
---|
| 902 | volatile uint32_t dma_control; /* + 0x1F4 */ |
---|
| 903 | volatile uint32_t des_cmnd; /* + 0x1F8 */ |
---|
| 904 | volatile uint32_t data; /* + 0x1FC */ |
---|
| 905 | |
---|
| 906 | volatile uint8_t RES[0x600]; |
---|
| 907 | |
---|
| 908 | |
---|
| 909 | #if 0 |
---|
| 910 | /* MIB COUNTERS (Offset 200-2FF) */ |
---|
| 911 | |
---|
| 912 | volatile uint32_t rmon_t_drop; /* + 0x200 */ |
---|
| 913 | volatile uint32_t rmon_t_packets; /* + 0x204 */ |
---|
| 914 | volatile uint32_t rmon_t_bc_pkt; /* + 0x208 */ |
---|
| 915 | volatile uint32_t rmon_t_mc_pkt; /* + 0x20C */ |
---|
| 916 | volatile uint32_t rmon_t_crc_align; /* + 0x210 */ |
---|
| 917 | volatile uint32_t rmon_t_undersize; /* + 0x214 */ |
---|
| 918 | volatile uint32_t rmon_t_oversize; /* + 0x218 */ |
---|
| 919 | volatile uint32_t rmon_t_frag; /* + 0x21C */ |
---|
| 920 | volatile uint32_t rmon_t_jab; /* + 0x220 */ |
---|
| 921 | volatile uint32_t rmon_t_col; /* + 0x224 */ |
---|
| 922 | volatile uint32_t rmon_t_p64; /* + 0x228 */ |
---|
| 923 | volatile uint32_t rmon_t_p65to127; /* + 0x22C */ |
---|
| 924 | volatile uint32_t rmon_t_p128to255; /* + 0x230 */ |
---|
| 925 | volatile uint32_t rmon_t_p256to511; /* + 0x234 */ |
---|
| 926 | volatile uint32_t rmon_t_p512to1023; /* + 0x238 */ |
---|
| 927 | volatile uint32_t rmon_t_p1024to2047;/* + 0x23C */ |
---|
| 928 | volatile uint32_t rmon_t_p_gte2048; /* + 0x240 */ |
---|
| 929 | volatile uint32_t rmon_t_octets; /* + 0x244 */ |
---|
| 930 | volatile uint32_t ieee_t_drop; /* + 0x248 */ |
---|
| 931 | volatile uint32_t ieee_t_frame_ok; /* + 0x24C */ |
---|
| 932 | volatile uint32_t ieee_t_1col; /* + 0x250 */ |
---|
| 933 | volatile uint32_t ieee_t_mcol; /* + 0x254 */ |
---|
| 934 | volatile uint32_t ieee_t_def; /* + 0x258 */ |
---|
| 935 | volatile uint32_t ieee_t_lcol; /* + 0x25C */ |
---|
| 936 | volatile uint32_t ieee_t_excol; /* + 0x260 */ |
---|
| 937 | volatile uint32_t ieee_t_macerr; /* + 0x264 */ |
---|
| 938 | volatile uint32_t ieee_t_cserr; /* + 0x268 */ |
---|
| 939 | volatile uint32_t ieee_t_sqe; /* + 0x26C */ |
---|
| 940 | volatile uint32_t t_fdxfc; /* + 0x270 */ |
---|
| 941 | volatile uint32_t ieee_t_octets_ok; /* + 0x274 */ |
---|
| 942 | |
---|
| 943 | volatile uint32_t res18[2]; /* + 0x278-27C */ |
---|
| 944 | volatile uint32_t rmon_r_drop; /* + 0x280 */ |
---|
| 945 | volatile uint32_t rmon_r_packets; /* + 0x284 */ |
---|
| 946 | volatile uint32_t rmon_r_bc_pkt; /* + 0x288 */ |
---|
| 947 | volatile uint32_t rmon_r_mc_pkt; /* + 0x28C */ |
---|
| 948 | volatile uint32_t rmon_r_crc_align; /* + 0x290 */ |
---|
| 949 | volatile uint32_t rmon_r_undersize; /* + 0x294 */ |
---|
| 950 | volatile uint32_t rmon_r_oversize; /* + 0x298 */ |
---|
| 951 | volatile uint32_t rmon_r_frag; /* + 0x29C */ |
---|
| 952 | volatile uint32_t rmon_r_jab; /* + 0x2A0 */ |
---|
| 953 | |
---|
| 954 | volatile uint32_t rmon_r_resvd_0; /* + 0x2A4 */ |
---|
| 955 | |
---|
| 956 | volatile uint32_t rmon_r_p64; /* + 0x2A8 */ |
---|
| 957 | volatile uint32_t rmon_r_p65to127; /* + 0x2AC */ |
---|
| 958 | volatile uint32_t rmon_r_p128to255; /* + 0x2B0 */ |
---|
| 959 | volatile uint32_t rmon_r_p256to511; /* + 0x2B4 */ |
---|
| 960 | volatile uint32_t rmon_r_p512to1023; /* + 0x2B8 */ |
---|
| 961 | volatile uint32_t rmon_r_p1024to2047;/* + 0x2BC */ |
---|
| 962 | volatile uint32_t rmon_r_p_gte2048; /* + 0x2C0 */ |
---|
| 963 | volatile uint32_t rmon_r_octets; /* + 0x2C4 */ |
---|
| 964 | volatile uint32_t ieee_r_drop; /* + 0x2C8 */ |
---|
| 965 | volatile uint32_t ieee_r_frame_ok; /* + 0x2CC */ |
---|
| 966 | volatile uint32_t ieee_r_crc; /* + 0x2D0 */ |
---|
| 967 | volatile uint32_t ieee_r_align; /* + 0x2D4 */ |
---|
| 968 | volatile uint32_t r_macerr; /* + 0x2D8 */ |
---|
| 969 | volatile uint32_t r_fdxfc; /* + 0x2DC */ |
---|
| 970 | volatile uint32_t ieee_r_octets_ok; /* + 0x2E0 */ |
---|
| 971 | |
---|
| 972 | volatile uint32_t res19[6]; /* + 0x2E4-2FC */ |
---|
| 973 | |
---|
| 974 | volatile uint32_t res20[64]; /* + 0x300-3FF */ |
---|
| 975 | |
---|
| 976 | volatile uint32_t res21[256]; /* + 0x400-800 */ |
---|
| 977 | #endif |
---|
| 978 | |
---|
| 979 | /* |
---|
| 980 | * SmartComm DMA PCI registers (MBAR + 0x3800) |
---|
| 981 | */ |
---|
| 982 | volatile uint8_t pci[0x200]; |
---|
| 983 | |
---|
| 984 | /* |
---|
| 985 | * advanced technology attachment registers (MBAR + 0x3A00) |
---|
| 986 | */ |
---|
| 987 | |
---|
| 988 | /* ATA host registers (offset 0x00-0x28) */ |
---|
| 989 | volatile uint32_t ata_hcfg; /* + 0x00 */ |
---|
| 990 | volatile uint32_t ata_hsr; /* + 0x04 */ |
---|
| 991 | volatile uint32_t ata_pio1; /* + 0x08 */ |
---|
| 992 | volatile uint32_t ata_pio2; /* + 0x0C */ |
---|
| 993 | volatile uint32_t ata_dma1; /* + 0x10 */ |
---|
| 994 | volatile uint32_t ata_dma2; /* + 0x14 */ |
---|
| 995 | volatile uint32_t ata_udma1; /* + 0x18 */ |
---|
| 996 | volatile uint32_t ata_udma2; /* + 0x1C */ |
---|
| 997 | volatile uint32_t ata_udma3; /* + 0x20 */ |
---|
| 998 | volatile uint32_t ata_udma4; /* + 0x24 */ |
---|
| 999 | volatile uint32_t ata_udma5; /* + 0x28 */ |
---|
| 1000 | volatile uint32_t ata_res1[4]; /* + 0x2C-0x3C */ |
---|
| 1001 | |
---|
| 1002 | /* ATA FIFO registers (offset 0x3C-0x50) */ |
---|
| 1003 | volatile uint32_t ata_rtfdwr; /* + 0x3C */ |
---|
| 1004 | volatile uint32_t ata_rtfsr; /* + 0x40 */ |
---|
| 1005 | volatile uint32_t ata_rtfcr; /* + 0x44 */ |
---|
| 1006 | volatile uint32_t ata_rtfar; /* + 0x48 */ |
---|
| 1007 | volatile uint32_t ata_rtfrpr; /* + 0x4C */ |
---|
| 1008 | volatile uint32_t ata_rtfwpr; /* + 0x50 */ |
---|
| 1009 | volatile uint32_t ata_res2[2]; /* + 0x54-0x5C */ |
---|
| 1010 | |
---|
| 1011 | /* ATA drive registers (offset 0x5C-0x80) */ |
---|
| 1012 | volatile uint32_t ata_dctr_dasr; /* + 0x5C */ |
---|
| 1013 | volatile uint32_t ata_ddr; /* + 0x60 */ |
---|
| 1014 | volatile uint32_t ata_dfr_der; /* + 0x64 */ |
---|
| 1015 | volatile uint32_t ata_dscr; /* + 0x68 */ |
---|
| 1016 | volatile uint32_t ata_dsnr; /* + 0x6C */ |
---|
| 1017 | volatile uint32_t ata_dclr; /* + 0x70 */ |
---|
| 1018 | volatile uint32_t ata_dchr; /* + 0x74 */ |
---|
| 1019 | volatile uint32_t ata_ddhr; /* + 0x78 */ |
---|
| 1020 | volatile uint32_t ata_dcr_dsr; /* + 0x7C */ |
---|
| 1021 | volatile uint32_t ata_res3[0xA0]; /* + 0x80-0x200 */ |
---|
| 1022 | |
---|
| 1023 | /* |
---|
| 1024 | * inter-integrated circuit registers (MBAR + 0x3D00) |
---|
| 1025 | */ |
---|
| 1026 | struct mpc5200_i2c_regs_s { |
---|
| 1027 | volatile uint8_t madr; /* i2c address reg. +0x00 */ |
---|
| 1028 | volatile uint8_t res_1[3]; |
---|
| 1029 | volatile uint8_t mfdr; /* i2c freq. divider reg. +0x04 */ |
---|
| 1030 | volatile uint8_t res_5[3]; |
---|
| 1031 | volatile uint8_t mcr; /* i2c control reg. +0x08 */ |
---|
| 1032 | volatile uint8_t res_9[3]; |
---|
| 1033 | |
---|
| 1034 | #define MPC5200_I2C_MCR_MEN (1 << (7-0)) |
---|
| 1035 | #define MPC5200_I2C_MCR_MIEN (1 << (7-1)) |
---|
| 1036 | #define MPC5200_I2C_MCR_MSTA (1 << (7-2)) |
---|
| 1037 | #define MPC5200_I2C_MCR_MTX (1 << (7-3)) |
---|
| 1038 | #define MPC5200_I2C_MCR_TXAK (1 << (7-4)) |
---|
| 1039 | #define MPC5200_I2C_MCR_RSTA (1 << (7-5)) |
---|
| 1040 | |
---|
| 1041 | volatile uint8_t msr; /* i2c status reg. +0x0C */ |
---|
| 1042 | volatile uint8_t res_d[3]; |
---|
| 1043 | #define MPC5200_I2C_MSR_CF (1 << (7-0)) |
---|
| 1044 | #define MPC5200_I2C_MSR_MAAS (1 << (7-1)) |
---|
| 1045 | #define MPC5200_I2C_MSR_BB (1 << (7-2)) |
---|
| 1046 | #define MPC5200_I2C_MSR_MAL (1 << (7-3)) |
---|
| 1047 | #define MPC5200_I2C_MSR_SRW (1 << (7-5)) |
---|
| 1048 | #define MPC5200_I2C_MSR_MIF (1 << (7-6)) |
---|
| 1049 | #define MPC5200_I2C_MSR_RXAK (1 << (7-7)) |
---|
| 1050 | volatile uint8_t mdr; /* i2c data I/O reg. +0x10 */ |
---|
| 1051 | volatile uint8_t res_11[3]; |
---|
| 1052 | volatile uint8_t res_14[12]; /* reserved +0x14 */ |
---|
| 1053 | volatile uint8_t icr; /* i2c irq ctrl reg. +0x20 */ |
---|
| 1054 | #define MPC5200_I2C_ICR_BNBE2 (1 << (7-0)) |
---|
| 1055 | #define MPC5200_I2C_ICR_TE2 (1 << (7-1)) |
---|
| 1056 | #define MPC5200_I2C_ICR_RE2 (1 << (7-2)) |
---|
| 1057 | #define MPC5200_I2C_ICR_IE2 (1 << (7-3)) |
---|
| 1058 | #define MPC5200_I2C_ICR_MASK2 (MPC5200_I2C_ICR_BNBE2|MPC5200_I2C_ICR_TE2\ |
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| 1059 | |MPC5200_I2C_ICR_RE2|MPC5200_I2C_ICR_IE2) |
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| 1060 | #define MPC5200_I2C_ICR_BNBE1 (1 << (7-4)) |
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| 1061 | #define MPC5200_I2C_ICR_TE1 (1 << (7-5)) |
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| 1062 | #define MPC5200_I2C_ICR_RE1 (1 << (7-6)) |
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| 1063 | #define MPC5200_I2C_ICR_IE1 (1 << (7-7)) |
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| 1064 | #define MPC5200_I2C_ICR_MASK1 (MPC5200_I2C_ICR_BNBE1|MPC5200_I2C_ICR_TE1\ |
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| 1065 | |MPC5200_I2C_ICR_RE1|MPC5200_I2C_ICR_IE1) |
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| 1066 | volatile uint8_t res_21[3]; |
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| 1067 | volatile uint32_t res_24[7]; /* reserved +0x24 */ |
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| 1068 | } i2c_regs[2]; |
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| 1069 | volatile uint8_t res_3d80[0x280]; |
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| 1070 | |
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| 1071 | /* |
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| 1072 | * on-chip static RAM memory locations (MBAR + 0x4000) |
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| 1073 | */ |
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| 1074 | volatile uint8_t sram_res0x4000[0x4000]; |
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| 1075 | volatile uint8_t sram[0x4000]; |
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| 1076 | |
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| 1077 | } mpc5200_t; |
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| 1078 | |
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| 1079 | extern volatile mpc5200_t mpc5200; |
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| 1080 | |
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| 1081 | #ifdef __cplusplus |
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| 1082 | } |
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| 1083 | #endif |
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| 1084 | |
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| 1085 | #endif /*ASM*/ |
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| 1086 | |
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| 1087 | #endif /* __MPC5200_h__ */ |
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