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source: rtems/c/src/lib/libbsp/powerpc/gen5200/include/irq.h @ c499856

4.115

Last change on this file since c499856 was c499856, checked in by Chris Johns <chrisj@…>, on 03/20/14 at 21:10:47
Change all references of rtems.com to rtems.org.
Property mode set to `100644`
File size: 11.0 KB

Line
1	/===============================================================\
2	\| Project: RTEMS generic MPC5200 BSP \|
3	+-----------------------------------------------------------------+
4	\| Partially based on the code references which are named below. \|
5	\| Adaptions, modifications, enhancements and any recent parts of \|
6	\| the code are: \|
7	\| Copyright (c) 2005, 2010 \|
8	\| Embedded Brains GmbH \|
9	\| Obere Lagerstr. 30 \|
10	\| D-82178 Puchheim \|
11	\| Germany \|
12	\| rtems@embedded-brains.de \|
13	+-----------------------------------------------------------------+
14	\| The license and distribution terms for this file may be \|
15	\| found in the file LICENSE in this distribution or at \|
16	\| \|
17	\| http://www.rtems.org/license/LICENSE. \|
18	\| \|
19	+-----------------------------------------------------------------+
20	\| this file contains declarations for the irq controller handler \|
21	\===============================================================/
22	/***********************************************************************/
23	/* */
24	/* Module: irq.h */
25	/* Date: 07/17/2003 */
26	/* Purpose: RTEMS MPC5x00 CPU interrupt header file */
27	/* */
28	/---------------------------------------------------------------------/
29	/* */
30	/* Description: This include file describe the data structure and */
31	/* the functions implemented by rtems to write */
32	/* interrupt handlers. */
33	/* */
34	/---------------------------------------------------------------------/
35	/* */
36	/* Code */
37	/* References: MPC8260ads CPU interrupt header file */
38	/* Module: irq.h */
39	/* Project: RTEMS 4.6.0pre1 / MCF8260ads BSP */
40	/* Version 1.1 */
41	/* Date: 10/10/2002 */
42	/* */
43	/* Author(s) / Copyright(s): */
44	/* */
45	/* Copyright (C) 1999 valette@crf.canon.fr */
46	/* */
47	/* This code is heavilly inspired by the public specification of */
48	/* STREAM V2 that can be found at: */
49	/* */
50	/* <http://www.chorus.com/Documentation/index.html> by following */
51	/* the STREAM API Specification Document link. */
52	/* */
53	/* Modified for mpc8260 by Andy Dachs <a.dachs@sstl.co.uk> */
54	/* Surrey Satellite Technology Limited */
55	/* The interrupt handling on the mpc8260 seems quite different from */
56	/* the 860 (I don't know the 860 well). Although some interrupts */
57	/* are routed via the CPM irq and some are direct to the SIU they */
58	/* all appear logically the same.Therefore I removed the distinction */
59	/* between SIU and CPM interrupts. */
60	/* */
61	/* The license and distribution terms for this file may be */
62	/* found in the file LICENSE in this distribution or at */
63	/* http://www.rtems.org/license/LICENSE. */
64	/* */
65	/---------------------------------------------------------------------/
66	/* */
67	/* Partially based on the code references which are named above. */
68	/* Adaptions, modifications, enhancements and any recent parts of */
69	/* the code are under the right of */
70	/* */
71	/* IPR Engineering, Dachauer StraÃe 38, D-80335 MÃŒnchen */
72	/* Copyright(C) 2003 */
73	/* */
74	/---------------------------------------------------------------------/
75	/* */
76	/* IPR Engineering makes no representation or warranties with */
77	/* respect to the performance of this computer program, and */
78	/* specifically disclaims any responsibility for any damages, */
79	/* special or consequential, connected with the use of this program. */
80	/* */
81	/---------------------------------------------------------------------/
82	/* */
83	/* Version history: 1.0 */
84	/* */
85	/***********************************************************************/
86
87	#ifndef LIBBSP_POWERPC_GEN5200_IRQ_H
88	#define LIBBSP_POWERPC_GEN5200_IRQ_H
89
90	#define PMCE_CE_SHADOW (1U << (31 - 31))
91	#define PMCE_CSE_STICKY (1U << (31 - 21))
92	#define PMCE_MSE_STICKY (1U << (31 - 10))
93	#define PMCE_PSE_STICKY (1U << (31 - 2))
94	#define PMCE_CSE_SOURCE(_pmce) (((_pmce) >> 8) & 0x3U)
95	#define PMCE_MSE_SOURCE(_pmce) (((_pmce) >> 16) & 0x1fU)
96	#define PMCE_PSE_SOURCE(_pmce) (((_pmce) >> 24) & 0x1fU)
97
98	/*
99	* Peripheral IRQ handlers related definitions
100	*/
101	#define BSP_PER_IRQ_NUMBER 22
102	#define BSP_PER_IRQ_LOWEST_OFFSET 0
103	#define BSP_PER_IRQ_MAX_OFFSET \
104	(BSP_PER_IRQ_LOWEST_OFFSET + BSP_PER_IRQ_NUMBER - 1) /* 21 */
105	/*
106	* Main IRQ handlers related definitions
107	*/
108	#define BSP_MAIN_IRQ_NUMBER 17
109	#define BSP_MAIN_IRQ_LOWEST_OFFSET BSP_PER_IRQ_MAX_OFFSET + 1 /* 22 */
110	#define BSP_MAIN_IRQ_MAX_OFFSET \
111	(BSP_MAIN_IRQ_LOWEST_OFFSET + BSP_MAIN_IRQ_NUMBER - 1) /* 38 */
112	/*
113	* Critical IRQ handlers related definitions
114	*/
115	#define BSP_CRIT_IRQ_NUMBER 4
116	#define BSP_CRIT_IRQ_LOWEST_OFFSET BSP_MAIN_IRQ_MAX_OFFSET + 1 /* 39 */
117	#define BSP_CRIT_IRQ_MAX_OFFSET \
118	(BSP_CRIT_IRQ_LOWEST_OFFSET + BSP_CRIT_IRQ_NUMBER - 1) /* 42 */
119	/*
120	* Summary of SIU interrupts
121	*/
122	#define BSP_SIU_IRQ_NUMBER BSP_CRIT_IRQ_MAX_OFFSET + 1 /* 43 */
123	#define BSP_SIU_IRQ_LOWEST_OFFSET BSP_PER_IRQ_LOWEST_OFFSET /* 0 */
124	#define BSP_SIU_IRQ_MAX_OFFSET BSP_CRIT_IRQ_MAX_OFFSET /* 42 */
125	/*
126	* Processor IRQ handlers related definitions
127	*/
128	#define BSP_PROCESSOR_IRQ_NUMBER 3
129	#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET BSP_CRIT_IRQ_MAX_OFFSET + 1 /* 44 */
130	#define BSP_PROCESSOR_IRQ_MAX_OFFSET \
131	(BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER - 1) /* 46 */
132	/*
133	* Summary
134	*/
135	#define BSP_IRQ_NUMBER BSP_PROCESSOR_IRQ_MAX_OFFSET + 1 /* 47 */
136	#define BSP_LOWEST_OFFSET BSP_PER_IRQ_LOWEST_OFFSET /* 0 */
137	#define BSP_MAX_OFFSET BSP_PROCESSOR_IRQ_MAX_OFFSET /* 46 */
138
139	#ifndef ASM
140
141	#include <rtems.h>
142	#include <rtems/irq.h>
143	#include <rtems/irq-extension.h>
144
145	/*
146	* index table for the module specific handlers, a few entries are only placeholders
147	*/
148	typedef enum {
149	BSP_SIU_IRQ_SMARTCOMM = BSP_PER_IRQ_LOWEST_OFFSET + 0,
150	BSP_SIU_IRQ_PSC1 = BSP_PER_IRQ_LOWEST_OFFSET + 1,
151	BSP_SIU_IRQ_PSC2 = BSP_PER_IRQ_LOWEST_OFFSET + 2,
152	BSP_SIU_IRQ_PSC3 = BSP_PER_IRQ_LOWEST_OFFSET + 3,
153	BSP_SIU_IRQ_PSC6 = BSP_PER_IRQ_LOWEST_OFFSET + 4,
154	BSP_SIU_IRQ_ETH = BSP_PER_IRQ_LOWEST_OFFSET + 5,
155	BSP_SIU_IRQ_USB = BSP_PER_IRQ_LOWEST_OFFSET + 6,
156	BSP_SIU_IRQ_ATA = BSP_PER_IRQ_LOWEST_OFFSET + 7,
157	BSP_SIU_IRQ_PCI_CRT = BSP_PER_IRQ_LOWEST_OFFSET + 8,
158	BSP_SIU_IRQ_PCI_SC_RX = BSP_PER_IRQ_LOWEST_OFFSET + 9,
159	BSP_SIU_IRQ_PCI_SC_TX = BSP_PER_IRQ_LOWEST_OFFSET + 10,
160	BSP_SIU_IRQ_PSC4 = BSP_PER_IRQ_LOWEST_OFFSET + 11,
161	BSP_SIU_IRQ_PSC5 = BSP_PER_IRQ_LOWEST_OFFSET + 12,
162	BSP_SIU_IRQ_SPI_MODF = BSP_PER_IRQ_LOWEST_OFFSET + 13,
163	BSP_SIU_IRQ_SPI_SPIF = BSP_PER_IRQ_LOWEST_OFFSET + 14,
164	BSP_SIU_IRQ_I2C1 = BSP_PER_IRQ_LOWEST_OFFSET + 15,
165	BSP_SIU_IRQ_I2C2 = BSP_PER_IRQ_LOWEST_OFFSET + 16,
166	BSP_SIU_IRQ_MSCAN1 = BSP_PER_IRQ_LOWEST_OFFSET + 17,
167	BSP_SIU_IRQ_MSCAN2 = BSP_PER_IRQ_LOWEST_OFFSET + 18,
168	BSP_SIU_IRQ_IR_RX = BSP_PER_IRQ_LOWEST_OFFSET + 19,
169	BSP_SIU_IRQ_IR_TX = BSP_PER_IRQ_LOWEST_OFFSET + 20,
170	BSP_SIU_IRQ_XLB_ARB = BSP_PER_IRQ_LOWEST_OFFSET + 21,
171
172	/* SL_TIMER1 -- handler entry only used in case of SMI */
173	BSP_SIU_IRQ_SL_TIMER1 = BSP_MAIN_IRQ_LOWEST_OFFSET + 0,
174	BSP_SIU_IRQ_IRQ1 = BSP_MAIN_IRQ_LOWEST_OFFSET + 1,
175	BSP_SIU_IRQ_IRQ2 = BSP_MAIN_IRQ_LOWEST_OFFSET + 2,
176	BSP_SIU_IRQ_IRQ3 = BSP_MAIN_IRQ_LOWEST_OFFSET + 3,
177	/* LO_INT -- handler entry never used (only placeholder) */
178	BSP_SIU_IRQ_LO_INT = BSP_MAIN_IRQ_LOWEST_OFFSET + 4,
179	BSP_SIU_IRQ_RTC_PER = BSP_MAIN_IRQ_LOWEST_OFFSET + 5,
180	BSP_SIU_IRQ_RTC_STW = BSP_MAIN_IRQ_LOWEST_OFFSET + 6,
181	BSP_SIU_IRQ_GPIO_STD = BSP_MAIN_IRQ_LOWEST_OFFSET + 7,
182	BSP_SIU_IRQ_GPIO_WKUP = BSP_MAIN_IRQ_LOWEST_OFFSET + 8,
183	BSP_SIU_IRQ_TMR0 = BSP_MAIN_IRQ_LOWEST_OFFSET + 9,
184	BSP_SIU_IRQ_TMR1 = BSP_MAIN_IRQ_LOWEST_OFFSET + 10,
185	BSP_SIU_IRQ_TMR2 = BSP_MAIN_IRQ_LOWEST_OFFSET + 1,
186	BSP_SIU_IRQ_TMR3 = BSP_MAIN_IRQ_LOWEST_OFFSET + 12,
187	BSP_SIU_IRQ_TMR4 = BSP_MAIN_IRQ_LOWEST_OFFSET + 13,
188	BSP_SIU_IRQ_TMR5 = BSP_MAIN_IRQ_LOWEST_OFFSET + 14,
189	BSP_SIU_IRQ_TMR6 = BSP_MAIN_IRQ_LOWEST_OFFSET + 15,
190	BSP_SIU_IRQ_TMR7 = BSP_MAIN_IRQ_LOWEST_OFFSET + 16,
191
192	BSP_SIU_IRQ_IRQ0 = BSP_CRIT_IRQ_LOWEST_OFFSET + 0,
193	BSP_SIU_IRQ_SL_TIMER0 = BSP_CRIT_IRQ_LOWEST_OFFSET + 1,
194	/* HI_INT -- handler entry never used (only placeholder) */
195	BSP_SIU_IRQ_HI_INT = BSP_CRIT_IRQ_LOWEST_OFFSET + 2,
196	BSP_SIU_IRQ_CSS_WKUP = BSP_CRIT_IRQ_LOWEST_OFFSET + 3,
197
198	BSP_DECREMENTER = BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 0,
199	BSP_SYSMGMT = BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 1,
200	BSP_EXT = BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 2
201	} rtems_irq_symbolic_name;
202
203	#define BSP_CRIT_IRQ_PRIO_LEVELS 4
204	#define BSP_PERIODIC_TIMER BSP_SIU_IRQ_TMR6
205
206	#define BSP_INTERRUPT_VECTOR_MIN BSP_LOWEST_OFFSET
207
208	#define BSP_INTERRUPT_VECTOR_MAX BSP_MAX_OFFSET
209
210	#endif
211
212	#endif /* LIBBSP_POWERPC_GEN5200_IRQ_H */

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