1 | /*===============================================================*\ |
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2 | | Project: RTEMS generic MPC5200 BSP | |
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3 | +-----------------------------------------------------------------+ |
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4 | | Partially based on the code references which are named below. | |
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5 | | Adaptions, modifications, enhancements and any recent parts of | |
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6 | | the code are: | |
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7 | | Copyright (c) 2005, 2010 | |
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8 | | Embedded Brains GmbH | |
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9 | | Obere Lagerstr. 30 | |
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10 | | D-82178 Puchheim | |
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11 | | Germany | |
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12 | | rtems@embedded-brains.de | |
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13 | +-----------------------------------------------------------------+ |
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14 | | The license and distribution terms for this file may be | |
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15 | | found in the file LICENSE in this distribution or at | |
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16 | | | |
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17 | | http://www.rtems.org/license/LICENSE. | |
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18 | | | |
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19 | +-----------------------------------------------------------------+ |
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20 | | this file contains declarations for the irq controller handler | |
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21 | \*===============================================================*/ |
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22 | /***********************************************************************/ |
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23 | /* */ |
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24 | /* Module: irq.h */ |
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25 | /* Date: 07/17/2003 */ |
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26 | /* Purpose: RTEMS MPC5x00 CPU interrupt header file */ |
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27 | /* */ |
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28 | /*---------------------------------------------------------------------*/ |
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29 | /* */ |
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30 | /* Description: This include file describe the data structure and */ |
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31 | /* the functions implemented by rtems to write */ |
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32 | /* interrupt handlers. */ |
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33 | /* */ |
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34 | /*---------------------------------------------------------------------*/ |
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35 | /* */ |
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36 | /* Code */ |
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37 | /* References: MPC8260ads CPU interrupt header file */ |
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38 | /* Module: irq.h */ |
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39 | /* Project: RTEMS 4.6.0pre1 / MCF8260ads BSP */ |
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40 | /* Version 1.1 */ |
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41 | /* Date: 10/10/2002 */ |
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42 | /* */ |
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43 | /* Author(s) / Copyright(s): */ |
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44 | /* */ |
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45 | /* Copyright (C) 1999 valette@crf.canon.fr */ |
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46 | /* */ |
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47 | /* This code is heavilly inspired by the public specification of */ |
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48 | /* STREAM V2 that can be found at: */ |
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49 | /* */ |
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50 | /* <http://www.chorus.com/Documentation/index.html> by following */ |
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51 | /* the STREAM API Specification Document link. */ |
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52 | /* */ |
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53 | /* Modified for mpc8260 by Andy Dachs <a.dachs@sstl.co.uk> */ |
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54 | /* Surrey Satellite Technology Limited */ |
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55 | /* The interrupt handling on the mpc8260 seems quite different from */ |
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56 | /* the 860 (I don't know the 860 well). Although some interrupts */ |
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57 | /* are routed via the CPM irq and some are direct to the SIU they */ |
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58 | /* all appear logically the same.Therefore I removed the distinction */ |
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59 | /* between SIU and CPM interrupts. */ |
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60 | /* */ |
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61 | /* The license and distribution terms for this file may be */ |
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62 | /* found in the file LICENSE in this distribution or at */ |
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63 | /* http://www.rtems.org/license/LICENSE. */ |
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64 | /* */ |
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65 | /*---------------------------------------------------------------------*/ |
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66 | /* */ |
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67 | /* Partially based on the code references which are named above. */ |
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68 | /* Adaptions, modifications, enhancements and any recent parts of */ |
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69 | /* the code are under the right of */ |
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70 | /* */ |
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71 | /* IPR Engineering, Dachauer StraÃe 38, D-80335 MÃŒnchen */ |
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72 | /* Copyright(C) 2003 */ |
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73 | /* */ |
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74 | /*---------------------------------------------------------------------*/ |
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75 | /* */ |
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76 | /* IPR Engineering makes no representation or warranties with */ |
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77 | /* respect to the performance of this computer program, and */ |
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78 | /* specifically disclaims any responsibility for any damages, */ |
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79 | /* special or consequential, connected with the use of this program. */ |
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80 | /* */ |
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81 | /*---------------------------------------------------------------------*/ |
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82 | /* */ |
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83 | /* Version history: 1.0 */ |
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84 | /* */ |
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85 | /***********************************************************************/ |
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86 | |
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87 | #ifndef LIBBSP_POWERPC_GEN5200_IRQ_H |
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88 | #define LIBBSP_POWERPC_GEN5200_IRQ_H |
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89 | |
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90 | #define PMCE_CE_SHADOW (1U << (31 - 31)) |
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91 | #define PMCE_CSE_STICKY (1U << (31 - 21)) |
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92 | #define PMCE_MSE_STICKY (1U << (31 - 10)) |
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93 | #define PMCE_PSE_STICKY (1U << (31 - 2)) |
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94 | #define PMCE_CSE_SOURCE(_pmce) (((_pmce) >> 8) & 0x3U) |
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95 | #define PMCE_MSE_SOURCE(_pmce) (((_pmce) >> 16) & 0x1fU) |
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96 | #define PMCE_PSE_SOURCE(_pmce) (((_pmce) >> 24) & 0x1fU) |
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97 | |
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98 | /* |
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99 | * Peripheral IRQ handlers related definitions |
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100 | */ |
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101 | #define BSP_PER_IRQ_NUMBER 22 |
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102 | #define BSP_PER_IRQ_LOWEST_OFFSET 0 |
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103 | #define BSP_PER_IRQ_MAX_OFFSET \ |
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104 | (BSP_PER_IRQ_LOWEST_OFFSET + BSP_PER_IRQ_NUMBER - 1) /* 21 */ |
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105 | /* |
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106 | * Main IRQ handlers related definitions |
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107 | */ |
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108 | #define BSP_MAIN_IRQ_NUMBER 17 |
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109 | #define BSP_MAIN_IRQ_LOWEST_OFFSET BSP_PER_IRQ_MAX_OFFSET + 1 /* 22 */ |
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110 | #define BSP_MAIN_IRQ_MAX_OFFSET \ |
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111 | (BSP_MAIN_IRQ_LOWEST_OFFSET + BSP_MAIN_IRQ_NUMBER - 1) /* 38 */ |
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112 | /* |
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113 | * Critical IRQ handlers related definitions |
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114 | */ |
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115 | #define BSP_CRIT_IRQ_NUMBER 4 |
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116 | #define BSP_CRIT_IRQ_LOWEST_OFFSET BSP_MAIN_IRQ_MAX_OFFSET + 1 /* 39 */ |
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117 | #define BSP_CRIT_IRQ_MAX_OFFSET \ |
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118 | (BSP_CRIT_IRQ_LOWEST_OFFSET + BSP_CRIT_IRQ_NUMBER - 1) /* 42 */ |
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119 | /* |
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120 | * Summary of SIU interrupts |
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121 | */ |
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122 | #define BSP_SIU_IRQ_NUMBER BSP_CRIT_IRQ_MAX_OFFSET + 1 /* 43 */ |
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123 | #define BSP_SIU_IRQ_LOWEST_OFFSET BSP_PER_IRQ_LOWEST_OFFSET /* 0 */ |
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124 | #define BSP_SIU_IRQ_MAX_OFFSET BSP_CRIT_IRQ_MAX_OFFSET /* 42 */ |
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125 | /* |
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126 | * Processor IRQ handlers related definitions |
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127 | */ |
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128 | #define BSP_PROCESSOR_IRQ_NUMBER 3 |
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129 | #define BSP_PROCESSOR_IRQ_LOWEST_OFFSET BSP_CRIT_IRQ_MAX_OFFSET + 1 /* 44 */ |
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130 | #define BSP_PROCESSOR_IRQ_MAX_OFFSET \ |
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131 | (BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER - 1) /* 46 */ |
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132 | /* |
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133 | * Summary |
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134 | */ |
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135 | #define BSP_IRQ_NUMBER BSP_PROCESSOR_IRQ_MAX_OFFSET + 1 /* 47 */ |
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136 | #define BSP_LOWEST_OFFSET BSP_PER_IRQ_LOWEST_OFFSET /* 0 */ |
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137 | #define BSP_MAX_OFFSET BSP_PROCESSOR_IRQ_MAX_OFFSET /* 46 */ |
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138 | |
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139 | #ifndef ASM |
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140 | |
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141 | #include <rtems.h> |
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142 | #include <rtems/irq.h> |
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143 | #include <rtems/irq-extension.h> |
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144 | |
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145 | /* |
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146 | * index table for the module specific handlers, a few entries are only placeholders |
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147 | */ |
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148 | typedef enum { |
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149 | BSP_SIU_IRQ_SMARTCOMM = BSP_PER_IRQ_LOWEST_OFFSET + 0, |
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150 | BSP_SIU_IRQ_PSC1 = BSP_PER_IRQ_LOWEST_OFFSET + 1, |
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151 | BSP_SIU_IRQ_PSC2 = BSP_PER_IRQ_LOWEST_OFFSET + 2, |
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152 | BSP_SIU_IRQ_PSC3 = BSP_PER_IRQ_LOWEST_OFFSET + 3, |
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153 | BSP_SIU_IRQ_PSC6 = BSP_PER_IRQ_LOWEST_OFFSET + 4, |
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154 | BSP_SIU_IRQ_ETH = BSP_PER_IRQ_LOWEST_OFFSET + 5, |
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155 | BSP_SIU_IRQ_USB = BSP_PER_IRQ_LOWEST_OFFSET + 6, |
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156 | BSP_SIU_IRQ_ATA = BSP_PER_IRQ_LOWEST_OFFSET + 7, |
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157 | BSP_SIU_IRQ_PCI_CRT = BSP_PER_IRQ_LOWEST_OFFSET + 8, |
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158 | BSP_SIU_IRQ_PCI_SC_RX = BSP_PER_IRQ_LOWEST_OFFSET + 9, |
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159 | BSP_SIU_IRQ_PCI_SC_TX = BSP_PER_IRQ_LOWEST_OFFSET + 10, |
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160 | BSP_SIU_IRQ_PSC4 = BSP_PER_IRQ_LOWEST_OFFSET + 11, |
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161 | BSP_SIU_IRQ_PSC5 = BSP_PER_IRQ_LOWEST_OFFSET + 12, |
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162 | BSP_SIU_IRQ_SPI_MODF = BSP_PER_IRQ_LOWEST_OFFSET + 13, |
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163 | BSP_SIU_IRQ_SPI_SPIF = BSP_PER_IRQ_LOWEST_OFFSET + 14, |
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164 | BSP_SIU_IRQ_I2C1 = BSP_PER_IRQ_LOWEST_OFFSET + 15, |
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165 | BSP_SIU_IRQ_I2C2 = BSP_PER_IRQ_LOWEST_OFFSET + 16, |
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166 | BSP_SIU_IRQ_MSCAN1 = BSP_PER_IRQ_LOWEST_OFFSET + 17, |
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167 | BSP_SIU_IRQ_MSCAN2 = BSP_PER_IRQ_LOWEST_OFFSET + 18, |
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168 | BSP_SIU_IRQ_IR_RX = BSP_PER_IRQ_LOWEST_OFFSET + 19, |
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169 | BSP_SIU_IRQ_IR_TX = BSP_PER_IRQ_LOWEST_OFFSET + 20, |
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170 | BSP_SIU_IRQ_XLB_ARB = BSP_PER_IRQ_LOWEST_OFFSET + 21, |
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171 | |
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172 | /* SL_TIMER1 -- handler entry only used in case of SMI */ |
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173 | BSP_SIU_IRQ_SL_TIMER1 = BSP_MAIN_IRQ_LOWEST_OFFSET + 0, |
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174 | BSP_SIU_IRQ_IRQ1 = BSP_MAIN_IRQ_LOWEST_OFFSET + 1, |
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175 | BSP_SIU_IRQ_IRQ2 = BSP_MAIN_IRQ_LOWEST_OFFSET + 2, |
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176 | BSP_SIU_IRQ_IRQ3 = BSP_MAIN_IRQ_LOWEST_OFFSET + 3, |
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177 | /* LO_INT -- handler entry never used (only placeholder) */ |
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178 | BSP_SIU_IRQ_LO_INT = BSP_MAIN_IRQ_LOWEST_OFFSET + 4, |
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179 | BSP_SIU_IRQ_RTC_PER = BSP_MAIN_IRQ_LOWEST_OFFSET + 5, |
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180 | BSP_SIU_IRQ_RTC_STW = BSP_MAIN_IRQ_LOWEST_OFFSET + 6, |
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181 | BSP_SIU_IRQ_GPIO_STD = BSP_MAIN_IRQ_LOWEST_OFFSET + 7, |
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182 | BSP_SIU_IRQ_GPIO_WKUP = BSP_MAIN_IRQ_LOWEST_OFFSET + 8, |
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183 | BSP_SIU_IRQ_TMR0 = BSP_MAIN_IRQ_LOWEST_OFFSET + 9, |
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184 | BSP_SIU_IRQ_TMR1 = BSP_MAIN_IRQ_LOWEST_OFFSET + 10, |
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185 | BSP_SIU_IRQ_TMR2 = BSP_MAIN_IRQ_LOWEST_OFFSET + 1, |
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186 | BSP_SIU_IRQ_TMR3 = BSP_MAIN_IRQ_LOWEST_OFFSET + 12, |
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187 | BSP_SIU_IRQ_TMR4 = BSP_MAIN_IRQ_LOWEST_OFFSET + 13, |
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188 | BSP_SIU_IRQ_TMR5 = BSP_MAIN_IRQ_LOWEST_OFFSET + 14, |
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189 | BSP_SIU_IRQ_TMR6 = BSP_MAIN_IRQ_LOWEST_OFFSET + 15, |
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190 | BSP_SIU_IRQ_TMR7 = BSP_MAIN_IRQ_LOWEST_OFFSET + 16, |
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191 | |
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192 | BSP_SIU_IRQ_IRQ0 = BSP_CRIT_IRQ_LOWEST_OFFSET + 0, |
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193 | BSP_SIU_IRQ_SL_TIMER0 = BSP_CRIT_IRQ_LOWEST_OFFSET + 1, |
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194 | /* HI_INT -- handler entry never used (only placeholder) */ |
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195 | BSP_SIU_IRQ_HI_INT = BSP_CRIT_IRQ_LOWEST_OFFSET + 2, |
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196 | BSP_SIU_IRQ_CSS_WKUP = BSP_CRIT_IRQ_LOWEST_OFFSET + 3, |
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197 | |
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198 | BSP_DECREMENTER = BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 0, |
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199 | BSP_SYSMGMT = BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 1, |
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200 | BSP_EXT = BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 2 |
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201 | } rtems_irq_symbolic_name; |
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202 | |
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203 | #define BSP_CRIT_IRQ_PRIO_LEVELS 4 |
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204 | #define BSP_PERIODIC_TIMER BSP_SIU_IRQ_TMR6 |
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205 | |
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206 | #define BSP_INTERRUPT_VECTOR_MIN BSP_LOWEST_OFFSET |
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207 | |
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208 | #define BSP_INTERRUPT_VECTOR_MAX BSP_MAX_OFFSET |
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209 | |
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210 | #endif |
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211 | |
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212 | #endif /* LIBBSP_POWERPC_GEN5200_IRQ_H */ |
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