1 | /*===============================================================*\ |
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2 | | Project: RTEMS generic MPC5200 BSP | |
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3 | +-----------------------------------------------------------------+ |
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4 | | Partially based on the code references which are named below. | |
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5 | | Adaptions, modifications, enhancements and any recent parts of | |
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6 | | the code are: | |
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7 | | Copyright (c) 2005 | |
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8 | | Embedded Brains GmbH | |
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9 | | Obere Lagerstr. 30 | |
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10 | | D-82178 Puchheim | |
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11 | | Germany | |
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12 | | rtems@embedded-brains.de | |
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13 | +-----------------------------------------------------------------+ |
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14 | | The license and distribution terms for this file may be | |
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15 | | found in the file LICENSE in this distribution or at | |
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16 | | | |
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17 | | http://www.rtems.com/license/LICENSE. | |
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18 | | | |
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19 | +-----------------------------------------------------------------+ |
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20 | | this file contains board specific definitions | |
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21 | \*===============================================================*/ |
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22 | |
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23 | #ifndef __GEN5200_BSP_h |
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24 | #define __GEN5200_BSP_h |
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25 | |
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26 | /* |
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27 | * distinguish board characteristics |
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28 | */ |
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29 | /* |
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30 | * for PM520 mdule on a ZE30 carrier |
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31 | */ |
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32 | #if defined(PM520_ZE30) |
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33 | #define PM520 |
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34 | #define GPIOPCR_INITMASK 0x337F3F77 |
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35 | #define GPIOPCR_INITVAL 0x01552114 |
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36 | /* we have PSC1/4/5/6 */ |
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37 | /* #define GEN5200_UART_AVAIL_MASK 0x39 */ |
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38 | #define GEN5200_UART_AVAIL_MASK 0x39 |
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39 | #endif |
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40 | /* |
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41 | * for PM520 mdule on a CR825 carrier |
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42 | */ |
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43 | #if defined(PM520_CR825) |
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44 | #define PM520 |
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45 | #define GPIOPCR_INITMASK 0x330F0F77 |
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46 | #define GPIOPCR_INITVAL 0x01050444 |
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47 | /* we have PSC1/2/3*/ |
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48 | #define GEN5200_UART_AVAIL_MASK 0x07 |
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49 | #endif |
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50 | |
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51 | #if defined(BRS5L) |
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52 | /* |
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53 | * IMD Custom Board BRS5L |
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54 | */ |
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55 | #define GPIOPCR_INITMASK 0xb30F0F77 |
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56 | #define GPIOPCR_INITVAL 0x91050444 |
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57 | /* we have PSC1/2/3 */ |
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58 | #define GEN5200_UART_AVAIL_MASK 0x07 |
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59 | /* |
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60 | * address range definitions |
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61 | */ |
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62 | /* ROM definitions (2 MB) */ |
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63 | #define ROM_START 0xFFE00000 |
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64 | #define ROM_END 0xFFFFFFFF |
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65 | #define BOOT_START ROM_START |
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66 | #define BOOT_END ROM_END |
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67 | |
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68 | /* SDRAM definitions (256 MB) */ |
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69 | #define RAM_START 0x00000000 |
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70 | #define RAM_END 0x0FFFFFFF |
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71 | |
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72 | /* DPRAM definitions (64 KB) */ |
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73 | #define DPRAM_START 0xFF000000 |
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74 | #define DPRAM_END 0xFF0003FF |
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75 | |
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76 | /* internal memory map definitions (64 KB) */ |
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77 | #define MBAR 0xF0000000 |
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78 | |
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79 | /* we need the low level initialization in start.S*/ |
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80 | #define NEED_LOW_LEVEL_INIT |
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81 | |
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82 | #define HAS_NVRAM_93CXX |
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83 | #elif defined (PM520) |
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84 | |
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85 | /* |
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86 | * MicroSys PM520 internal memory map definitions |
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87 | */ |
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88 | #define MBAR 0xF0000000 |
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89 | #define HAS_UBOOT |
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90 | |
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91 | #else |
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92 | #error "board type not defined" |
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93 | #endif |
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94 | |
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95 | #ifndef ASM |
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96 | |
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97 | #ifdef __cplusplus |
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98 | extern "C" { |
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99 | #endif |
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100 | |
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101 | #include "bspopts.h" |
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102 | |
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103 | #include <rtems.h> |
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104 | #include <rtems/console.h> |
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105 | #include <rtems/clockdrv.h> |
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106 | #include <i2cdrv.h> |
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107 | |
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108 | #if defined(HAS_UBOOT) |
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109 | #define CONFIG_MPC5xxx |
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110 | #include <u-boot.h> |
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111 | extern bd_t *uboot_bdinfo_ptr; |
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112 | extern bd_t uboot_bdinfo_copy; |
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113 | #endif |
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114 | |
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115 | /* |
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116 | * Network driver configuration |
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117 | */ |
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118 | struct rtems_bsdnet_ifconfig; |
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119 | extern int rtems_mpc5200_fec_driver_attach_detach (struct rtems_bsdnet_ifconfig *config, int attaching); |
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120 | #define RTEMS_BSP_NETWORK_DRIVER_NAME "eth1" |
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121 | #define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_mpc5200_fec_driver_attach_detach |
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122 | |
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123 | /* miscellaneous stuff assumed to exist */ |
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124 | |
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125 | extern rtems_configuration_table BSP_Configuration; |
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126 | /* |
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127 | * We need to decide how much memory will be non-cacheable. This |
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128 | * will mainly be memory that will be used in DMA (network and serial |
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129 | * buffers). |
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130 | */ |
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131 | /* |
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132 | #define NOCACHE_MEM_SIZE 512*1024 |
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133 | */ |
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134 | |
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135 | /* |
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136 | * Define the time limits for RTEMS Test Suite test durations. |
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137 | * Long test and short test duration limits are provided. These |
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138 | * values are in seconds and need to be converted to ticks for the |
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139 | * application. |
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140 | * |
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141 | */ |
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142 | |
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143 | #define MAX_LONG_TEST_DURATION 300 /* 5 minutes = 300 seconds */ |
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144 | #define MAX_SHORT_TEST_DURATION 3 /* 3 seconds */ |
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145 | |
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146 | /* |
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147 | * Stuff for Time Test 27 |
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148 | */ |
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149 | #define MUST_WAIT_FOR_INTERRUPT 0 |
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150 | |
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151 | /* |
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152 | * Device Driver Table Entries |
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153 | */ |
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154 | |
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155 | /* |
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156 | * NOTE: Use the standard Console driver entry |
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157 | */ |
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158 | |
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159 | /* |
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160 | * NOTE: Use the standard Clock driver entry |
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161 | */ |
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162 | |
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163 | #ifdef HAS_NVRAM_93CXX |
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164 | #define NVRAM_DRIVER_TABLE_ENTRY \ |
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165 | { nvram_driver_initialize, nvram_driver_open, nvram_driver_close, \ |
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166 | nvram_driver_read, nvram_driver_write, NULL } |
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167 | #endif |
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168 | |
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169 | #define RTC_DRIVER_TABLE_ENTRY \ |
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170 | { rtc_initialize, NULL, NULL, NULL, NULL, NULL } |
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171 | extern rtems_device_driver rtc_initialize( |
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172 | rtems_device_major_number major, |
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173 | rtems_device_minor_number minor, |
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174 | void *arg |
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175 | ); |
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176 | |
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177 | /* |
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178 | * indicate, that BSP has IDE driver |
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179 | */ |
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180 | #define RTEMS_BSP_HAS_IDE_DRIVER |
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181 | |
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182 | /* |
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183 | * How many libio files we want |
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184 | */ |
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185 | #define BSP_LIBIO_MAX_FDS 20 |
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186 | |
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187 | /* functions */ |
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188 | |
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189 | void bsp_cleanup(void); |
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190 | |
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191 | /* console modes (only termios) */ |
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192 | #ifdef PRINTK_MINOR |
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193 | #undef PRINTK_MINOR |
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194 | #endif |
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195 | #define PRINTK_MINOR PSC1_MINOR |
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196 | |
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197 | #define SINGLE_CHAR_MODE |
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198 | #define UARTS_USE_TERMIOS_INT 1 |
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199 | |
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200 | /* ata modes */ |
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201 | #undef ATA_USE_INT |
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202 | |
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203 | /* clock settings */ |
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204 | #if defined(HAS_UBOOT) |
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205 | #define IPB_CLOCK (uboot_bdinfo_ptr->bi_ipbfreq) |
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206 | #define XLB_CLOCK (uboot_bdinfo_ptr->bi_busfreq) |
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207 | #define G2_CLOCK (uboot_bdinfo_ptr->bi_intfreq) |
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208 | #else |
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209 | #define IPB_CLOCK 33000000 /* 33 MHz */ |
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210 | #define XLB_CLOCK 66000000 /* 66 MHz */ |
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211 | #define G2_CLOCK 231000000 /* 231 MHz */ |
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212 | #endif |
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213 | |
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214 | /* slicetimer settings */ |
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215 | #define USE_SLICETIMER_0 TRUE |
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216 | #define USE_SLICETIMER_1 FALSE |
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217 | |
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218 | #ifdef __cplusplus |
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219 | } |
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220 | #endif |
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221 | |
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222 | #endif /* ASM */ |
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223 | |
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224 | #endif /* GEN5200 */ |
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