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source: rtems/c/src/lib/libbsp/powerpc/gen5200/ide/pcmcia_ide.c @ caeaae26

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Last change on this file since caeaae26 was caeaae26, checked in by Chris Johns <chrisj@…>, on 01/04/18 at 07:50:56

bsp/gen5200: Use public include path

Update #3254.

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File size: 21.8 KB

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1	/===============================================================\
2	\| Project: RTEMS generic MPC5200 BSP \|
3	+-----------------------------------------------------------------+
4	\| Partially based on the code references which are named below. \|
5	\| Adaptions, modifications, enhancements and any recent parts of \|
6	\| the code are: \|
7	\| Copyright (c) 2005 \|
8	\| Embedded Brains GmbH \|
9	\| Obere Lagerstr. 30 \|
10	\| D-82178 Puchheim \|
11	\| Germany \|
12	\| rtems@embedded-brains.de \|
13	+-----------------------------------------------------------------+
14	\| The license and distribution terms for this file may be \|
15	\| found in the file LICENSE in this distribution or at \|
16	\| \|
17	\| http://www.rtems.org/license/LICENSE. \|
18	\| \|
19	+-----------------------------------------------------------------+
20	\| this file contains the PCMCIA IDE access functions \|
21	\===============================================================/
22	/***********************************************************************/
23	/* */
24	/* Module: pcmcia_ide.c */
25	/* Date: 07/17/2003 */
26	/* Purpose: RTEMS MPC5x00 PCMCIA IDE harddisk driver */
27	/* */
28	/---------------------------------------------------------------------/
29	/* */
30	/* Description: */
31	/* */
32	/---------------------------------------------------------------------/
33	/* */
34	/* Code */
35	/* References: RTEMS MBX8xx PCMCIA IDE harddisc driver */
36	/* Module: pcmcia_ide.c */
37	/* Project: RTEMS 4.6.0pre1 / Mbx8xx BSP */
38	/* Version */
39	/* Date: 01/14/2003 */
40	/* */
41	/* Author(s) / Copyright(s): */
42	/* */
43	/* Copyright (c) 2003 IMD */
44	/* Ingenieurbuero fuer Microcomputertechnik Th. Doerfler */
45	/* <Thomas.Doerfler@imd-systems.de> */
46	/* all rights reserved */
47	/* */
48	/* this file contains the BSP layer for PCMCIA IDE access below the */
49	/* libchip IDE harddisc driver based on a board specific driver from */
50	/* Eugeny S. Mints, Oktet */
51	/* */
52	/* The license and distribution terms for this file may be */
53	/* found in the file LICENSE in this distribution or at */
54	/* http://www.rtems.org/license/LICENSE. */
55	/* */
56	/---------------------------------------------------------------------/
57	/* */
58	/* Partially based on the code references which are named above. */
59	/* Adaptions, modifications, enhancements and any recent parts of */
60	/* the code are under the right of */
61	/* */
62	/* IPR Engineering, Dachauer StraÃe 38, D-80335 MÃŒnchen */
63	/* Copyright(C) 2003 */
64	/* */
65	/---------------------------------------------------------------------/
66	/* */
67	/* IPR Engineering makes no representation or warranties with */
68	/* respect to the performance of this computer program, and */
69	/* specifically disclaims any responsibility for any damages, */
70	/* special or consequential, connected with the use of this program. */
71	/* */
72	/---------------------------------------------------------------------/
73	/* */
74	/* Version history: 1.0 */
75	/* */
76	/***********************************************************************/
77
78	#include <sys/param.h>
79	#include <rtems.h>
80	#include <rtems/error.h>
81	#include <rtems/score/sysstate.h>
82	#include <bsp.h>
83	#include <bsp/irq.h>
84	#include <bsp/mpc5200.h>
85	#include "./pcmcia_ide.h"
86
87	#include <libchip/ide_ctrl.h>
88	#include <libchip/ide_ctrl_cfg.h>
89	#include <libchip/ide_ctrl_io.h>
90	#include <string.h>
91
92	#define IDE_DMA_TEST FALSE
93
94	/* DMA supported PIO mode is broken */
95	#define IDE_USE_INT TRUE
96	#define IDE_READ_USE_DMA FALSE
97	#define IDE_USE_READ_PIO_OPT FALSE
98	#define IDE_WRITE_USE_DMA FALSE
99	#define IDE_USE_WRITE_PIO_OPT FALSE
100	#define IDE_USE_DMA (IDE_READ_USE_DMA \|\| IDE_WRITE_USE_DMA)
101
102	#define IDE_USE_STATISTICS TRUE
103
104	#if IDE_USE_DMA
105	#define PCMCIA_IDE_DMA_WR_BD_CNT 2
106	#define PCMCIA_IDE_DMA_RD_BD_CNT 2
107	#define PCMCIA_IDE_INTERRUPT_EVENT RTEMS_EVENT_2
108	/* Task number assignment */
109	#include "../bestcomm/bestcomm_glue.h"
110	#include "../bestcomm/bestcomm_api.h"
111	#include "../bestcomm/task_api/bestcomm_cntrl.h"
112	#include "../bestcomm/task_api/tasksetup_bdtable.h"
113
114	#define IDE_RX_TASK_NO TASK_GEN_DP_BD_0
115	#define IDE_TX_TASK_NO TASK_GEN_DP_BD_1
116	static TaskId pcmcia_ide_rxTaskId; /* SDMA RX task ID */
117	static TaskId pcmcia_ide_txTaskId; /* SDMA TX task ID */
118	#define PCMCIA_IDE_RD_SECTOR_SIZE 512 /* FIXME: make this better... */
119	#define PCMCIA_IDE_WR_SECTOR_SIZE 512 /* FIXME: make this better... */
120
121	bool mpc5200_dma_task_started[2] = {false,false};
122	#endif /* IDE_USE_DMA */
123
124	#if IDE_USE_STATISTICS
125	uint32_t mpc5200_pcmciaide_write_block_call_cnt = 0;
126	uint32_t mpc5200_pcmciaide_write_block_block_cnt = 0;
127	uint32_t mpc5200_pcmciaide_read_block_call_cnt = 0;
128	uint32_t mpc5200_pcmciaide_read_block_block_cnt = 0;
129	#endif
130
131	extern volatile uint32_t * mpc5200_ata_drive_regs[];
132	extern uint32_t ata_pio_timings[2][6];
133
134	void mpc5200_pcmciaide_dma_blockop(
135	bool, int, uint16_t, rtems_blkdev_sg_buffer , uint32_t , uint32_t *);
136	/*
137	* support functions for PCMCIA IDE IF
138	*/
139	static bool mpc5200_pcmciaide_probe(int minor)
140	{
141	bool ide_card_plugged = false; /* assume: we don't have a card plugged in */
142	struct mpc5200_gpt gpt = (struct mpc5200_gpt )(&mpc5200.gpt[GPT2]);
143
144	#ifdef MPC5200_BOARD_DP2
145	/* Deactivate RESET signal */
146	rtems_interrupt_level level;
147	rtems_interrupt_disable(level);
148	mpc5200.gpiowe \|= GPIO_W_PIN_PSC1_4;
149	mpc5200.gpiowod &= ~GPIO_W_PIN_PSC1_4;
150	mpc5200.gpiowdd \|= GPIO_W_PIN_PSC1_4;
151	mpc5200.gpiowdo \|= GPIO_W_PIN_PSC1_4;
152	rtems_interrupt_enable(level);
153	/* FIXME */
154	volatile int i = 0;
155	while (++i < 20000000);
156	#endif
157
158	/* enable card detection on GPT2 */
159	gpt->emsel = (GPT_EMSEL_GPIO_IN \| GPT_EMSEL_TIMER_MS_GPIO);
160
161	#if defined (MPC5200_BOARD_BRS5L)
162	/* Check for card detection (-CD0) */
163	if((gpt->status) & GPT_STATUS_PIN)
164	ide_card_plugged = false;
165	else
166	#endif
167	ide_card_plugged = true;
168
169	return ide_card_plugged;
170
171	}
172
173	#define DMA1_T0(val) BSP_BFLD32(COUNT_VAL(val), 0, 7)
174	#define DMA1_TD(val) BSP_BFLD32(COUNT_VAL(val), 8, 15)
175	#define DMA1_TK(val) BSP_BFLD32(COUNT_VAL(val), 16, 23)
176	#define DMA1_TM(val) BSP_BFLD32(COUNT_VAL(val), 24, 31)
177
178	#define DMA2_TH(val) BSP_BFLD32(COUNT_VAL(val), 0, 7)
179	#define DMA2_TJ(val) BSP_BFLD32(COUNT_VAL(val), 8, 15)
180	#define DMA2_TN(val) BSP_BFLD32(COUNT_VAL(val), 16, 23)
181
182	static rtems_status_code mpc5200_pcmciaide_config_io_speed(int minor, uint16_t modes_avail)
183	{
184	uint8_t pio_t0, pio_t2_8, pio_t2_16, pio_t4, pio_t1, pio_ta;
185
186	if((modes_avail & ATA_MODES_PIO4) != 0)
187	{
188
189	pio_t0 = ata_pio_timings[PIO_4][T0];
190	pio_t2_8 = ata_pio_timings[PIO_4][T2_8];
191	pio_t2_16 = ata_pio_timings[PIO_4][T2_16];
192	pio_t4 = ata_pio_timings[PIO_4][T4];
193	pio_t1 = ata_pio_timings[PIO_4][T1];
194	pio_ta = ata_pio_timings[PIO_4][TA];
195
196	}
197	else
198	{
199
200	pio_t0 = ata_pio_timings[PIO_3][T0];
201	pio_t2_8 = ata_pio_timings[PIO_3][T2_8];
202	pio_t2_16 = ata_pio_timings[PIO_3][T2_16];
203	pio_t4 = ata_pio_timings[PIO_3][T4];
204	pio_t1 = ata_pio_timings[PIO_3][T1];
205	pio_ta = ata_pio_timings[PIO_3][TA];
206
207	}
208
209	/* set timings according according to selected ATA mode */
210	mpc5200.ata_pio1 = ATA_PIO_TIMING_1(pio_t0, pio_t2_8, pio_t2_16);
211	mpc5200.ata_pio2 = ATA_PIO_TIMING_2(pio_t4, pio_t1, pio_ta);
212
213	mpc5200.ata_dma1 = DMA1_T0(120) \| DMA1_TD(70) \| DMA1_TK(25) \| DMA1_TM(25);
214	mpc5200.ata_dma2 = DMA2_TH(10) \| DMA2_TJ(5) \| DMA2_TN(10);
215
216	return RTEMS_SUCCESSFUL;
217
218	}
219
220
221
222	static void mpc5200_pcmciaide_read_reg(int minor, int reg, uint16_t *value)
223	{
224	volatile uint32_t *ata_reg = mpc5200_ata_drive_regs[reg];
225
226	if(reg == IDE_REGISTER_DATA_WORD)
227	value = (volatile uint16_t *)(ata_reg);
228	else
229	value = (volatile uint8_t *)(ata_reg);
230	}
231
232
233	static void mpc5200_pcmciaide_write_reg(int minor, int reg, uint16_t value)
234	{
235	volatile uint32_t *ata_reg = mpc5200_ata_drive_regs[reg];
236
237	if(reg == IDE_REGISTER_DATA_WORD)
238	(volatile uint16_t )(ata_reg) = value;
239	else
240	(volatile uint8_t )(ata_reg) = value;
241	}
242
243	#if IDE_USE_DMA
244
245
246	uint32_t pcmcia_ide_rxInterrupts;
247	uint32_t pcmcia_ide_txInterrupts;
248	volatile rtems_id pcmcia_ide_hdl_task = 0;
249	/*
250	* MPC5200 BestComm interrupt handlers
251	*/
252	static void pcmcia_ide_recv_dmairq_hdl(rtems_irq_hdl_param unused)
253	{
254	SDMA_CLEAR_IEVENT(&mpc5200.sdma.IntPend,IDE_RX_TASK_NO);
255
256	/Disable receive ints/
257	bestcomm_glue_irq_disable(IDE_RX_TASK_NO);
258
259	pcmcia_ide_rxInterrupts++; /* Rx int has occurred */
260
261	if (pcmcia_ide_hdl_task != 0) {
262	rtems_event_send(pcmcia_ide_hdl_task,PCMCIA_IDE_INTERRUPT_EVENT);
263	}
264	}
265
266	static void pcmcia_ide_xmit_dmairq_hdl(rtems_irq_hdl_param unused)
267	{
268
269	SDMA_CLEAR_IEVENT(&mpc5200.sdma.IntPend,IDE_TX_TASK_NO);
270
271	/Disable transmit ints/
272	bestcomm_glue_irq_disable(IDE_TX_TASK_NO);
273
274	pcmcia_ide_txInterrupts++; /* Tx int has occurred */
275
276	if (pcmcia_ide_hdl_task != 0) {
277	rtems_event_send(pcmcia_ide_hdl_task,PCMCIA_IDE_INTERRUPT_EVENT);
278	}
279	}
280
281
282	void mpc5200_pcmciaide_dma_init(int minor)
283	{
284	TaskSetupParamSet_t rxParam; /* RX task setup parameters */
285	TaskSetupParamSet_t txParam; /* TX task setup parameters */
286	/*
287	* Init Bestcomm system
288	*/
289	bestcomm_glue_init();
290	/*
291	* Setup the SDMA RX task.
292	*/
293	rxParam.NumBD = PCMCIA_IDE_DMA_RD_BD_CNT;
294	rxParam.Size.MaxBuf = PCMCIA_IDE_RD_SECTOR_SIZE;
295	rxParam.Initiator = INITIATOR_ALWAYS;
296	rxParam.StartAddrSrc =
297	(uint32)mpc5200_ata_drive_regs[IDE_REGISTER_DATA_WORD];
298	rxParam.IncrSrc = 0;
299	rxParam.SzSrc = sizeof(uint16_t);
300	rxParam.StartAddrDst = (uint32)NULL;
301	rxParam.IncrDst = sizeof(uint16_t);
302	rxParam.SzDst = sizeof(uint16_t); /* XXX: set this to 32 bit? */
303
304	pcmcia_ide_rxTaskId = TaskSetup(IDE_RX_TASK_NO,&rxParam );
305
306	/*
307	* Setup the TX task.
308	*/
309	txParam.NumBD = PCMCIA_IDE_DMA_WR_BD_CNT;
310	txParam.Size.MaxBuf = PCMCIA_IDE_WR_SECTOR_SIZE;
311	txParam.Initiator = INITIATOR_ALWAYS;
312	txParam.StartAddrSrc = (uint32)NULL;
313	txParam.IncrSrc = sizeof(uint16_t);
314	txParam.SzSrc = sizeof(uint16_t); /* do not set this to 32 bit! */
315	txParam.StartAddrDst =
316	(uint32)mpc5200_ata_drive_regs[IDE_REGISTER_DATA_WORD];
317	txParam.IncrDst = 0;
318	txParam.SzDst = sizeof(uint16_t);
319
320	pcmcia_ide_txTaskId = TaskSetup( IDE_TX_TASK_NO, &txParam );
321	/*
322	* FIXME: Init BD rings
323	*/
324	/*
325	* Enable the SmartDMA transmit/receive task.
326	* do not enable interrupts to CPU
327	*/
328	/*
329	* connect interrupt handlers
330	*/
331	bestcomm_glue_irq_install(IDE_TX_TASK_NO,pcmcia_ide_xmit_dmairq_hdl,NULL);
332	bestcomm_glue_irq_install(IDE_RX_TASK_NO,pcmcia_ide_recv_dmairq_hdl,NULL);
333	}
334	#endif /* IDE_USE_DMA */
335
336	void mpc5200_pcmciaide_dma_blockop(bool is_write,
337	int minor,
338	uint16_t block_size,
339	rtems_blkdev_sg_buffer *bufs,
340	uint32_t *cbuf,
341	uint32_t *pos)
342
343	{
344	#if IDE_USE_DMA
345	/*
346	* Nameing:
347	* - a block is one unit of data on disk (multiple sectors)
348	* - a buffer is a contignuous chunk of data in memory
349	* a block on disk may be filled with data from several buffers
350	*/
351	uint32_t buf_idx,bufs_from_dma, bufs_to_dma,bufs_total;
352	uint32_t bds_free;
353	uint32_t llength;
354	rtems_status_code rc = RTEMS_SUCCESSFUL;
355	rtems_event_set events;
356	BDIdx nxt_bd_idx;
357	bool use_irq = (_System_state_Current == SYSTEM_STATE_UP);
358	/*
359	* determine number of blocks
360	*/
361	llength = 0;
362	buf_idx = 0;
363	bufs += cbuf; / cbuf is the index of the next buffer to send in this transaction /
364	while (llength < block_size) {
365	llength += bufs[buf_idx++].length;
366	}
367	bufs_from_dma = 0;
368	bufs_to_dma = 0;
369	bufs_total = buf_idx;
370	/*
371	* here all BDs should be unused
372	*/
373	bds_free = is_write ? PCMCIA_IDE_DMA_WR_BD_CNT : PCMCIA_IDE_DMA_RD_BD_CNT;
374	/*
375	* repeat, until all bufs are transferred
376	*/
377	while ((rc == RTEMS_SUCCESSFUL) &&
378	(bufs_from_dma < bufs_total)) {
379
380	while ((rc == RTEMS_SUCCESSFUL) &&
381	(bufs_to_dma < bufs_total) &&
382	(bds_free > 0)) {
383	/*
384	* fill in BD, set interrupt if needed
385	*/
386	SDMA_CLEAR_IEVENT(&mpc5200.sdma.IntPend,(is_write
387	? IDE_TX_TASK_NO
388	: IDE_RX_TASK_NO));
389	if (is_write) {
390	TaskBDAssign(pcmcia_ide_txTaskId ,
391	(void *)bufs[bufs_to_dma].buffer,
392	(void *)mpc5200_ata_drive_regs[IDE_REGISTER_DATA_WORD],
393	bufs[bufs_to_dma].length,
394	0/* flags */);
395	#if IDE_USE_STATISTICS
396	mpc5200_pcmciaide_write_block_block_cnt++;
397	#endif
398	}
399	else {
400	TaskBDAssign(pcmcia_ide_rxTaskId ,
401	(void *)mpc5200_ata_drive_regs[IDE_REGISTER_DATA_WORD],
402	(void *)bufs[bufs_to_dma].buffer,
403	bufs[bufs_to_dma].length,
404	0/* flags */);
405	#if IDE_USE_STATISTICS
406	mpc5200_pcmciaide_read_block_block_cnt++;
407	#endif
408	}
409	bufs_to_dma ++;
410	bds_free --;
411	}
412	if (is_write) {
413	TaskStart( pcmcia_ide_txTaskId, TASK_AUTOSTART_DISABLE,
414	pcmcia_ide_txTaskId, TASK_INTERRUPT_DISABLE );
415	}
416	else {
417	TaskStart( pcmcia_ide_rxTaskId, TASK_AUTOSTART_DISABLE,
418	pcmcia_ide_rxTaskId, TASK_INTERRUPT_DISABLE );
419	}
420	if (use_irq) {
421
422	/*
423	* enable interrupts, wait for interrupt event
424	*/
425	pcmcia_ide_hdl_task = rtems_task_self();
426	bestcomm_glue_irq_enable((is_write
427	? IDE_TX_TASK_NO
428	: IDE_RX_TASK_NO));
429
430	rtems_event_receive(PCMCIA_IDE_INTERRUPT_EVENT,
431	RTEMS_WAIT \| RTEMS_EVENT_ANY,
432	RTEMS_NO_TIMEOUT, &events);
433
434	pcmcia_ide_hdl_task = 0;
435	}
436	else {
437	/*
438	* HACK: just wait some time...
439	*/
440	/*
441	* FIXME: poll, until SDMA is finished
442	*/
443	volatile int32_t i;
444	for (i = 0;i < 10000;i++) {};
445	}
446
447	do {
448	nxt_bd_idx = TaskBDRelease(is_write
449	? pcmcia_ide_txTaskId
450	: pcmcia_ide_rxTaskId);
451	if ((nxt_bd_idx != TASK_ERR_BD_RING_EMPTY) &&
452	(nxt_bd_idx != TASK_ERR_BD_BUSY)) {
453	(*cbuf)++;
454	(*pos) += bufs[bufs_from_dma].length;
455	bufs_from_dma++;
456	bds_free++;
457	}
458	} while ((nxt_bd_idx != TASK_ERR_BD_RING_EMPTY) &&
459	(nxt_bd_idx != TASK_ERR_BD_BUSY) &&
460	(bufs_from_dma < bufs_to_dma));
461	}
462	#endif /* IDE_USE_DMA */
463	}
464
465
466	static void mpc5200_pcmciaide_read_block(int minor, uint32_t block_size,
467	rtems_blkdev_sg_buffer bufs, uint32_t cbuf, uint32_t *pos)
468	{
469
470	volatile uint32_t *ata_reg=mpc5200_ata_drive_regs[IDE_REGISTER_DATA_WORD];
471	uint16_t cnt = 0;
472	uint16_t lbuf = (uint16_t)((uint8_t)(bufs[(cbuf)].buffer)+(*pos));
473	uint32_t llength = bufs[(*cbuf)].length;
474	bool use_dma;
475
476	#if IDE_USE_STATISTICS
477	mpc5200_pcmciaide_read_block_call_cnt++;
478	#endif
479	#if IDE_READ_USE_DMA
480	/*
481	* FIXME: walk through buffer list. If any buffer has other size than default,
482	* then do not use DMA
483	* Is this needed?
484	*/
485	use_dma = true;
486	/* use_dma = false; */
487	#else
488	use_dma = false;
489	#endif
490	if (use_dma) {
491	/*
492	* FIXME: wait for DRQ ready
493	* check, that once DRQ is ready, we really can send ALL data for this
494	* type of transfer mode
495	*/
496	while ((GET_UP_BYTE_OF_MPC5200_ATA_DRIVE_REG((volatile uint32_t)
497	(mpc5200.ata_dctr_dasr)) &
498	IDE_REGISTER_STATUS_DRQ) == 0);
499	/*
500	* translate (part of) buffer list into DMA BDs
501	* only last (available) DMA BD sends interrupt
502	* DMA BDs may get ready as soon as possible
503	*/
504	mpc5200_pcmciaide_dma_blockop(FALSE, /* read operation */
505	minor,
506	block_size,bufs,cbuf,pos);
507	}
508	else {
509	#if IDE_USE_READ_PIO_OPT
510	while(cnt < block_size) {
511
512	lbuf++ = GET_UP_WORD_OF_MPC5200_ATA_DRIVE_REG((volatile uint32_t )(ata_reg)); / only 16 bit data port */
513	cnt += 2;
514	(*pos) += 2;
515
516	if((*pos) == llength) {
517
518	(*pos) = 0;
519	(*cbuf)++;
520	lbuf = bufs[(*cbuf)].buffer;
521	llength = bufs[(*cbuf)].length;
522
523	}
524	}
525	#else
526
527	while((GET_UP_BYTE_OF_MPC5200_ATA_DRIVE_REG((volatile uint32_t)(mpc5200.ata_dctr_dasr)) & IDE_REGISTER_STATUS_DRQ) && (cnt < block_size)) {
528
529	lbuf++ = (volatile uint16_t )(ata_reg); / only 16 bit data port */
530	cnt += 2;
531	(*pos) += 2;
532
533	if((*pos) == llength) {
534	(*pos) = 0;
535	(*cbuf)++;
536	lbuf = bufs[(*cbuf)].buffer;
537	llength = bufs[(*cbuf)].length;
538	}
539	}
540	#endif
541	}
542	}
543
544	static void mpc5200_pcmciaide_write_block(int minor, uint32_t block_size,
545	rtems_blkdev_sg_buffer bufs, uint32_t cbuf, uint32_t *pos)
546	{
547
548
549	volatile uint32_t *ata_reg = mpc5200_ata_drive_regs[IDE_REGISTER_DATA_WORD];
550	uint16_t cnt = 0;
551	uint16_t lbuf = (uint16_t )((uint8_t )(bufs[(cbuf)].buffer) + (*pos));
552	uint32_t llength = bufs[(*cbuf)].length;
553	bool use_dma;
554
555	#if IDE_USE_STATISTICS
556	mpc5200_pcmciaide_write_block_call_cnt++;
557	#endif
558	#if IDE_WRITE_USE_DMA
559	/*
560	* FIXME: walk through buffer list. If any buffer has other size than default,
561	* then do not use DMA
562	* Is this needed?
563	*/
564	use_dma = true;
565	#else
566	use_dma = false;
567	#endif
568
569	if (use_dma) {
570	/*
571	* wait for DRQ ready
572	* FIXME: check, that once DRQ is ready, we really can send ALL data for this
573	* type of transfer mode
574	*/
575	while ((GET_UP_BYTE_OF_MPC5200_ATA_DRIVE_REG((volatile uint32_t)
576	(mpc5200.ata_dctr_dasr)) &
577	IDE_REGISTER_STATUS_DRQ) == 0);
578	/*
579	* translate (part of) buffer list into DMA BDs
580	* only last (available) DMA BD sends interrupt
581	* DMA BDs may get ready as soon as possible
582	*/
583	mpc5200_pcmciaide_dma_blockop(true, /* write opeartion */
584	minor,
585	block_size,bufs,cbuf,pos);
586	}
587	else {
588	#if IDE_USE_WRITE_PIO_OPT
589	while(cnt < block_size) {
590	int32_t loop_cnt,loop_max;
591
592	#if IDE_USE_STATISTICS
593	mpc5200_pcmciaide_write_block_block_cnt++;
594	#endif
595
596	loop_max = llength - (*pos) ;
597	if (loop_max > (block_size - cnt)) {
598	loop_max = (block_size - cnt);
599	}
600	for (loop_cnt = loop_max/2;loop_cnt > 0;loop_cnt--) {
601	(volatile uint32_t )(ata_reg) =
602	SET_UP_WORD_OF_MPC5200_ATA_DRIVE_REG(lbuf++); / only 16 bit data port */
603	}
604	cnt += loop_max;
605	(*pos) += loop_max;
606
607	if((*pos) == llength) {
608
609	(*pos) = 0;
610	(*cbuf)++;
611	lbuf = bufs[(*cbuf)].buffer;
612	llength = bufs[(*cbuf)].length;
613	}
614	}
615	#else
616	while((GET_UP_BYTE_OF_MPC5200_ATA_DRIVE_REG((volatile uint32_t)(mpc5200.ata_dctr_dasr))
617	& IDE_REGISTER_STATUS_DRQ)
618	&& (cnt < block_size)) {
619	(volatile uint16_t )(ata_reg) = lbuf++; / only 16 bit data port */
620	cnt += 2;
621	(*pos) += 2;
622
623	if((*pos) == llength) {
624	(*pos) = 0;
625	(*cbuf)++;
626	lbuf = bufs[(*cbuf)].buffer;
627	llength = bufs[(*cbuf)].length;
628	}
629	}
630	#endif
631	}
632	}
633
634	static int mpc5200_pcmciaide_control(int minor, uint32_t cmd, void * arg)
635	{
636	return RTEMS_SUCCESSFUL;
637	}
638
639	static void mpc5200_pcmciaide_initialize(int minor)
640	{
641	#if defined (MPC5200_BOARD_BRS5L)
642	struct mpc5200_gpt gpt = (struct mpc5200_gpt )(&mpc5200.gpt[GPT7]);
643
644	/* invert ATA reset on GPT7 */
645	gpt->emsel = (GPT_EMSEL_GPIO_OUT_HIGH \| GPT_EMSEL_TIMER_MS_GPIO);
646	#endif
647	/* reset ata host contr. and FIFO */
648	mpc5200.ata_hcfg \|= (ATA_HCFG_SMR \| ATA_HCFG_FR);
649	mpc5200.ata_hcfg &= ~(ATA_HCFG_SMR \| ATA_HCFG_FR);
650
651	/* for the first access set lowest performance transfer mode to PIO3 */
652	mpc5200_pcmciaide_config_io_speed(minor, ATA_MODES_PIO3);
653
654	/* enable PIO operations (PIO 3/4) */
655	mpc5200.ata_hcfg \|= ATA_HCFG_IORDY;
656
657	#ifdef IDE_USE_INT
658	mpc5200.ata_hcfg \|= ATA_HCFG_IE ;
659	#endif
660
661	#if IDE_USE_DMA
662	mpc5200_pcmciaide_dma_init(minor);
663	#endif
664	}
665
666
667	/*
668	* The following table configures the functions used for IDE drivers
669	* in this BSP.
670	*/
671	ide_ctrl_fns_t mpc5200_pcmciaide_ctrl_fns =
672	{
673	mpc5200_pcmciaide_probe,
674	mpc5200_pcmciaide_initialize,
675	mpc5200_pcmciaide_control,
676	mpc5200_pcmciaide_read_reg,
677	mpc5200_pcmciaide_write_reg,
678	mpc5200_pcmciaide_read_block,
679	mpc5200_pcmciaide_write_block,
680	mpc5200_pcmciaide_config_io_speed
681	};
682

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