1 | /*===============================================================*\ |
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2 | | Project: RTEMS generic MPC5200 BSP | |
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3 | +-----------------------------------------------------------------+ |
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4 | | Partially based on the code references which are named below. | |
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5 | | Adaptions, modifications, enhancements and any recent parts of | |
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6 | | the code are: | |
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7 | | Copyright (c) 2005 | |
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8 | | Embedded Brains GmbH | |
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9 | | Obere Lagerstr. 30 | |
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10 | | D-82178 Puchheim | |
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11 | | Germany | |
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12 | | rtems@embedded-brains.de | |
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13 | +-----------------------------------------------------------------+ |
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14 | | The license and distribution terms for this file may be | |
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15 | | found in the file LICENSE in this distribution or at | |
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16 | | | |
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17 | | http://www.rtems.com/license/LICENSE. | |
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18 | | | |
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19 | +-----------------------------------------------------------------+ |
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20 | | this file contains the PCMCIA IDE access functions | |
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21 | \*===============================================================*/ |
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22 | /***********************************************************************/ |
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23 | /* */ |
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24 | /* Module: pcmcia_ide.c */ |
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25 | /* Date: 07/17/2003 */ |
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26 | /* Purpose: RTEMS MPC5x00 PCMCIA IDE harddisk driver */ |
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27 | /* */ |
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28 | /*---------------------------------------------------------------------*/ |
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29 | /* */ |
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30 | /* Description: */ |
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31 | /* */ |
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32 | /*---------------------------------------------------------------------*/ |
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33 | /* */ |
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34 | /* Code */ |
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35 | /* References: RTEMS MBX8xx PCMCIA IDE harddisc driver */ |
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36 | /* Module: pcmcia_ide.c */ |
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37 | /* Project: RTEMS 4.6.0pre1 / Mbx8xx BSP */ |
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38 | /* Version */ |
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39 | /* Date: 01/14/2003 */ |
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40 | /* */ |
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41 | /* Author(s) / Copyright(s): */ |
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42 | /* */ |
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43 | /* Copyright (c) 2003 IMD */ |
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44 | /* Ingenieurbuero fuer Microcomputertechnik Th. Doerfler */ |
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45 | /* <Thomas.Doerfler@imd-systems.de> */ |
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46 | /* all rights reserved */ |
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47 | /* */ |
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48 | /* this file contains the BSP layer for PCMCIA IDE access below the */ |
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49 | /* libchip IDE harddisc driver based on a board specific driver from */ |
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50 | /* Eugeny S. Mints, Oktet */ |
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51 | /* */ |
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52 | /* The license and distribution terms for this file may be */ |
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53 | /* found in the file LICENSE in this distribution or at */ |
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54 | /* http://www.rtems.com/license/LICENSE. */ |
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55 | /* */ |
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56 | /*---------------------------------------------------------------------*/ |
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57 | /* */ |
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58 | /* Partially based on the code references which are named above. */ |
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59 | /* Adaptions, modifications, enhancements and any recent parts of */ |
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60 | /* the code are under the right of */ |
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61 | /* */ |
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62 | /* IPR Engineering, Dachauer StraÃe 38, D-80335 MÃŒnchen */ |
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63 | /* Copyright(C) 2003 */ |
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64 | /* */ |
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65 | /*---------------------------------------------------------------------*/ |
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66 | /* */ |
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67 | /* IPR Engineering makes no representation or warranties with */ |
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68 | /* respect to the performance of this computer program, and */ |
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69 | /* specifically disclaims any responsibility for any damages, */ |
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70 | /* special or consequential, connected with the use of this program. */ |
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71 | /* */ |
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72 | /*---------------------------------------------------------------------*/ |
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73 | /* */ |
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74 | /* Version history: 1.0 */ |
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75 | /* */ |
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76 | /***********************************************************************/ |
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77 | |
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78 | #include <rtems.h> |
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79 | #include <rtems/error.h> |
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80 | #include <bsp.h> |
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81 | #include <bsp/irq.h> |
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82 | #include "../include/mpc5200.h" |
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83 | #include "./pcmcia_ide.h" |
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84 | |
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85 | #include <libchip/ide_ctrl.h> |
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86 | #include <libchip/ide_ctrl_cfg.h> |
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87 | #include <libchip/ide_ctrl_io.h> |
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88 | #include <string.h> |
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89 | |
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90 | #ifndef MIN |
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91 | #define MIN(a,b) (((a)<(b))?(a):(b)) |
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92 | #endif |
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93 | #define IDE_DMA_TEST FALSE |
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94 | |
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95 | #ifdef BRS5L |
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96 | #define IDE_USE_INT TRUE |
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97 | #define IDE_READ_USE_DMA TRUE |
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98 | #define IDE_USE_READ_PIO_OPT FALSE |
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99 | #define IDE_WRITE_USE_DMA TRUE |
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100 | #define IDE_USE_WRITE_PIO_OPT TRUE |
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101 | /* #define IDE_USE_DMA (IDE_READ_USE_DMA||IDE_WRITE_USE_DMA) */ |
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102 | #define IDE_USE_DMA TRUE |
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103 | #else |
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104 | #define IDE_USE_INT TRUE |
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105 | #define IDE_READ_USE_DMA FALSE |
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106 | #define IDE_USE_READ_PIO_OPT FALSE |
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107 | #define IDE_WRITE_USE_DMA FALSE |
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108 | #define IDE_USE_WRITE_PIO_OPT FALSE |
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109 | /* #define IDE_USE_DMA (IDE_READ_USE_DMA||IDE_WRITE_USE_DMA) */ |
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110 | #define IDE_USE_DMA FALSE |
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111 | #endif |
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112 | |
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113 | #define IDE_USE_STATISTICS TRUE |
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114 | |
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115 | #if IDE_USE_DMA |
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116 | #define PCMCIA_IDE_DMA_WR_BD_CNT 2 |
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117 | #define PCMCIA_IDE_DMA_RD_BD_CNT 2 |
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118 | #define PCMCIA_IDE_INTERRUPT_EVENT RTEMS_EVENT_2 |
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119 | /* Task number assignment */ |
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120 | #include "../bestcomm/bestcomm_glue.h" |
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121 | #include "../bestcomm/bestcomm_api.h" |
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122 | #include "../bestcomm/task_api/bestcomm_cntrl.h" |
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123 | #include "../bestcomm/task_api/tasksetup_bdtable.h" |
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124 | |
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125 | #define IDE_RECV_TASK_NO TASK_GEN_DP_BD_0 |
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126 | #define TASK_GEN_DP_BD_1 TASK_GEN_DP_BD_1 |
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127 | static TaskId pcmcia_ide_rxTaskId; /* SDMA RX task ID */ |
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128 | static TaskId pcmcia_ide_txTaskId; /* SDMA TX task ID */ |
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129 | #define PCMCIA_IDE_RD_SECTOR_SIZE 512 /* FIXME: make this better... */ |
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130 | #define PCMCIA_IDE_WR_SECTOR_SIZE 512 /* FIXME: make this better... */ |
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131 | |
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132 | bool mpc5200_dma_task_started[2] = {false,false}; |
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133 | #endif /* IDE_USE_DMA */ |
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134 | |
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135 | #if IDE_USE_STATISTICS |
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136 | uint32_t mpc5200_pcmciaide_write_block_call_cnt = 0; |
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137 | uint32_t mpc5200_pcmciaide_write_block_block_cnt = 0; |
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138 | uint32_t mpc5200_pcmciaide_read_block_call_cnt = 0; |
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139 | uint32_t mpc5200_pcmciaide_read_block_block_cnt = 0; |
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140 | #endif |
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141 | |
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142 | extern volatile uint32_t * mpc5200_ata_drive_regs[]; |
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143 | extern uint32_t ata_pio_timings[2][6]; |
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144 | |
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145 | void mpc5200_pcmciaide_dma_blockop( |
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146 | bool, int, uint16_t, rtems_blkdev_sg_buffer *, uint32_t *, uint32_t *); |
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147 | /* |
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148 | * support functions for PCMCIA IDE IF |
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149 | */ |
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150 | bool mpc5200_pcmciaide_probe(int minor) |
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151 | { |
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152 | bool ide_card_plugged = false; /* assume: we don't have a card plugged in */ |
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153 | struct mpc5200_gpt *gpt = (struct mpc5200_gpt *)(&mpc5200.gpt[GPT2]); |
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154 | |
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155 | /* enable card detection on GPT2 */ |
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156 | gpt->emsel = (GPT_EMSEL_GPIO_IN | GPT_EMSEL_TIMER_MS_GPIO); |
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157 | |
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158 | #if defined (BRS5L) |
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159 | /* Check for card detection (-CD0) */ |
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160 | if((gpt->status) & GPT_STATUS_PIN) |
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161 | ide_card_plugged = false; |
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162 | else |
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163 | #endif |
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164 | ide_card_plugged = true; |
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165 | |
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166 | return ide_card_plugged; |
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167 | |
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168 | } |
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169 | |
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170 | |
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171 | rtems_status_code mpc5200_pcmciaide_config_io_speed(int minor, uint16_t modes_avail) |
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172 | { |
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173 | uint8_t pio_t0, pio_t2_8, pio_t2_16, pio_t4, pio_t1, pio_ta; |
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174 | |
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175 | if((modes_avail & ATA_MODES_PIO4) != 0) |
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176 | { |
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177 | |
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178 | pio_t0 = ata_pio_timings[PIO_4][T0]; |
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179 | pio_t2_8 = ata_pio_timings[PIO_4][T2_8]; |
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180 | pio_t2_16 = ata_pio_timings[PIO_4][T2_16]; |
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181 | pio_t4 = ata_pio_timings[PIO_4][T4]; |
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182 | pio_t1 = ata_pio_timings[PIO_4][T1]; |
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183 | pio_ta = ata_pio_timings[PIO_4][TA]; |
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184 | |
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185 | } |
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186 | else |
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187 | { |
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188 | |
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189 | pio_t0 = ata_pio_timings[PIO_3][T0]; |
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190 | pio_t2_8 = ata_pio_timings[PIO_3][T2_8]; |
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191 | pio_t2_16 = ata_pio_timings[PIO_3][T2_16]; |
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192 | pio_t4 = ata_pio_timings[PIO_3][T4]; |
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193 | pio_t1 = ata_pio_timings[PIO_3][T1]; |
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194 | pio_ta = ata_pio_timings[PIO_3][TA]; |
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195 | |
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196 | } |
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197 | |
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198 | /* set timings according according to selected ATA mode */ |
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199 | mpc5200.ata_pio1 = ATA_PIO_TIMING_1(pio_t0, pio_t2_8, pio_t2_16); |
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200 | mpc5200.ata_pio2 = ATA_PIO_TIMING_2(pio_t4, pio_t1, pio_ta); |
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201 | |
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202 | return RTEMS_SUCCESSFUL; |
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203 | |
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204 | } |
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205 | |
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206 | |
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207 | |
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208 | void mpc5200_pcmciaide_read_reg(int minor, int reg, uint16_t *value) |
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209 | { |
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210 | volatile uint32_t *ata_reg = mpc5200_ata_drive_regs[reg]; |
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211 | |
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212 | if(reg == IDE_REGISTER_DATA_WORD) |
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213 | *value = *(volatile uint16_t *)(ata_reg); |
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214 | else |
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215 | *value = *(volatile uint8_t *)(ata_reg); |
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216 | } |
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217 | |
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218 | |
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219 | void mpc5200_pcmciaide_write_reg(int minor, int reg, uint16_t value) |
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220 | { |
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221 | volatile uint32_t *ata_reg = mpc5200_ata_drive_regs[reg]; |
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222 | |
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223 | if(reg == IDE_REGISTER_DATA_WORD) |
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224 | *(volatile uint16_t *)(ata_reg) = value; |
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225 | else |
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226 | *(volatile uint8_t *)(ata_reg) = value; |
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227 | } |
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228 | |
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229 | #if IDE_USE_DMA |
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230 | |
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231 | |
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232 | uint32_t pcmcia_ide_rxInterrupts; |
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233 | uint32_t pcmcia_ide_txInterrupts; |
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234 | volatile rtems_id pcmcia_ide_hdl_task = 0; |
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235 | /* |
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236 | * MPC5200 BestComm interrupt handlers |
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237 | */ |
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238 | static void pcmcia_ide_recv_dmairq_hdl(rtems_irq_hdl_param unused) |
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239 | { |
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240 | SDMA_CLEAR_IEVENT(&mpc5200.IntPend,TASK_GEN_DP_BD_0); |
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241 | |
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242 | /*Disable receive ints*/ |
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243 | bestcomm_glue_irq_disable(TASK_GEN_DP_BD_0); |
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244 | |
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245 | pcmcia_ide_rxInterrupts++; /* Rx int has occurred */ |
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246 | |
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247 | if (pcmcia_ide_hdl_task != 0) { |
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248 | rtems_event_send(pcmcia_ide_hdl_task,PCMCIA_IDE_INTERRUPT_EVENT); |
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249 | } |
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250 | } |
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251 | |
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252 | static void pcmcia_ide_xmit_dmairq_hdl(rtems_irq_hdl_param unused) |
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253 | { |
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254 | |
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255 | SDMA_CLEAR_IEVENT(&mpc5200.IntPend,TASK_GEN_DP_BD_1); |
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256 | |
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257 | /*Disable transmit ints*/ |
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258 | bestcomm_glue_irq_disable(TASK_GEN_DP_BD_1); |
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259 | |
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260 | pcmcia_ide_txInterrupts++; /* Tx int has occurred */ |
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261 | |
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262 | if (pcmcia_ide_hdl_task != 0) { |
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263 | rtems_event_send(pcmcia_ide_hdl_task,PCMCIA_IDE_INTERRUPT_EVENT); |
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264 | } |
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265 | } |
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266 | |
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267 | |
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268 | void mpc5200_pcmciaide_dma_init(int minor) |
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269 | { |
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270 | TaskSetupParamSet_t rxParam; /* RX task setup parameters */ |
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271 | TaskSetupParamSet_t txParam; /* TX task setup parameters */ |
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272 | /* |
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273 | * Init Bestcomm system |
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274 | */ |
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275 | bestcomm_glue_init(); |
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276 | /* |
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277 | * Setup the SDMA RX task. |
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278 | */ |
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279 | rxParam.NumBD = PCMCIA_IDE_DMA_RD_BD_CNT; |
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280 | rxParam.Size.MaxBuf = PCMCIA_IDE_RD_SECTOR_SIZE; |
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281 | rxParam.Initiator = INITIATOR_ALWAYS; |
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282 | rxParam.StartAddrSrc = |
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283 | (uint32)mpc5200_ata_drive_regs[IDE_REGISTER_DATA_WORD]; |
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284 | rxParam.IncrSrc = 0; |
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285 | rxParam.SzSrc = sizeof(uint16_t); |
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286 | rxParam.StartAddrDst = (uint32)NULL; |
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287 | rxParam.IncrDst = sizeof(uint16_t); |
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288 | rxParam.SzDst = sizeof(uint16_t); /* XXX: set this to 32 bit? */ |
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289 | |
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290 | pcmcia_ide_rxTaskId = TaskSetup(TASK_GEN_DP_BD_0,&rxParam ); |
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291 | |
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292 | /* |
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293 | * Setup the TX task. |
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294 | */ |
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295 | txParam.NumBD = PCMCIA_IDE_DMA_WR_BD_CNT; |
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296 | txParam.Size.MaxBuf = PCMCIA_IDE_WR_SECTOR_SIZE; |
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297 | txParam.Initiator = INITIATOR_ALWAYS; |
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298 | txParam.StartAddrSrc = (uint32)NULL; |
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299 | txParam.IncrSrc = sizeof(uint16_t); |
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300 | txParam.SzSrc = sizeof(uint16_t); /* do not set this to 32 bit! */ |
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301 | txParam.StartAddrDst = |
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302 | (uint32)mpc5200_ata_drive_regs[IDE_REGISTER_DATA_WORD]; |
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303 | txParam.IncrDst = 0; |
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304 | txParam.SzDst = sizeof(uint16_t); |
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305 | |
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306 | pcmcia_ide_txTaskId = TaskSetup( TASK_GEN_DP_BD_1, &txParam ); |
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307 | /* |
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308 | * FIXME: Init BD rings |
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309 | */ |
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310 | /* |
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311 | * Enable the SmartDMA transmit/receive task. |
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312 | * do not enable interrupts to CPU |
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313 | */ |
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314 | /* |
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315 | * connect interrupt handlers |
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316 | */ |
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317 | bestcomm_glue_irq_install(TASK_GEN_DP_BD_1,pcmcia_ide_xmit_dmairq_hdl,NULL); |
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318 | bestcomm_glue_irq_install(TASK_GEN_DP_BD_0,pcmcia_ide_recv_dmairq_hdl,NULL); |
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319 | } |
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320 | |
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321 | void mpc5200_pcmciaide_dma_blockop(bool is_write, |
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322 | int minor, |
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323 | uint16_t block_size, |
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324 | rtems_blkdev_sg_buffer *bufs, |
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325 | uint32_t *cbuf, |
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326 | uint32_t *pos) |
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327 | |
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328 | { |
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329 | /* |
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330 | * Nameing: |
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331 | * - a block is one unit of data on disk (multiple sectors) |
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332 | * - a buffer is a contignuous chunk of data in memory |
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333 | * a block on disk may be filled with data from several buffers |
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334 | */ |
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335 | uint32_t buf_idx,bufs_from_dma, bufs_to_dma,bufs_total; |
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336 | uint32_t bds_free; |
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337 | uint32_t llength; |
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338 | rtems_status_code rc = RTEMS_SUCCESSFUL; |
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339 | rtems_event_set events; |
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340 | BDIdx nxt_bd_idx; |
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341 | bool use_irq = (_System_state_Current == SYSTEM_STATE_UP); |
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342 | /* |
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343 | * determine number of blocks |
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344 | */ |
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345 | llength = 0; |
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346 | buf_idx = 0; |
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347 | bufs += *cbuf; /* *cbuf is the index of the next buffer to send in this transaction */ |
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348 | while (llength < block_size) { |
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349 | llength += bufs[buf_idx++].length; |
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350 | } |
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351 | bufs_from_dma = 0; |
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352 | bufs_to_dma = 0; |
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353 | bufs_total = buf_idx; |
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354 | /* |
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355 | * here all BDs should be unused |
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356 | */ |
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357 | bds_free = is_write ? PCMCIA_IDE_DMA_WR_BD_CNT : PCMCIA_IDE_DMA_RD_BD_CNT; |
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358 | /* |
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359 | * repeat, until all bufs are transferred |
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360 | */ |
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361 | while ((rc == RTEMS_SUCCESSFUL) && |
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362 | (bufs_from_dma < bufs_total)) { |
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363 | |
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364 | while ((rc == RTEMS_SUCCESSFUL) && |
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365 | (bufs_to_dma < bufs_total) && |
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366 | (bds_free > 0)) { |
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367 | /* |
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368 | * fill in BD, set interrupt if needed |
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369 | */ |
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370 | SDMA_CLEAR_IEVENT(&mpc5200.IntPend,(is_write |
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371 | ? TASK_GEN_DP_BD_1 |
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372 | : TASK_GEN_DP_BD_0)); |
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373 | if (is_write) { |
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374 | TaskBDAssign(pcmcia_ide_txTaskId , |
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375 | (void *)bufs[bufs_to_dma].buffer, |
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376 | (void *)mpc5200_ata_drive_regs[IDE_REGISTER_DATA_WORD], |
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377 | bufs[bufs_to_dma].length, |
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378 | 0/* flags */); |
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379 | #if IDE_USE_STATISTICS |
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380 | mpc5200_pcmciaide_write_block_block_cnt++; |
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381 | #endif |
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382 | } |
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383 | else { |
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384 | TaskBDAssign(pcmcia_ide_rxTaskId , |
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385 | (void *)mpc5200_ata_drive_regs[IDE_REGISTER_DATA_WORD], |
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386 | (void *)bufs[bufs_to_dma].buffer, |
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387 | bufs[bufs_to_dma].length, |
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388 | 0/* flags */); |
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389 | #if IDE_USE_STATISTICS |
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390 | mpc5200_pcmciaide_read_block_block_cnt++; |
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391 | #endif |
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392 | } |
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393 | bufs_to_dma ++; |
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394 | bds_free --; |
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395 | } |
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396 | if (is_write) { |
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397 | TaskStart( pcmcia_ide_txTaskId, TASK_AUTOSTART_DISABLE, |
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398 | pcmcia_ide_txTaskId, TASK_INTERRUPT_DISABLE ); |
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399 | } |
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400 | else { |
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401 | TaskStart( pcmcia_ide_rxTaskId, TASK_AUTOSTART_DISABLE, |
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402 | pcmcia_ide_rxTaskId, TASK_INTERRUPT_DISABLE ); |
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403 | } |
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404 | if (use_irq) { |
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405 | |
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406 | /* |
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407 | * enable interrupts, wait for interrupt event |
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408 | */ |
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409 | rtems_task_ident(RTEMS_SELF,0,(rtems_id *)&pcmcia_ide_hdl_task); |
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410 | bestcomm_glue_irq_enable((is_write |
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411 | ? TASK_GEN_DP_BD_1 |
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412 | : TASK_GEN_DP_BD_0)); |
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413 | |
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414 | rtems_event_receive(PCMCIA_IDE_INTERRUPT_EVENT, |
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415 | RTEMS_WAIT | RTEMS_EVENT_ANY, |
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416 | RTEMS_NO_TIMEOUT, &events); |
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417 | |
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418 | pcmcia_ide_hdl_task = 0; |
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419 | } |
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420 | else { |
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421 | /* |
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422 | * HACK: just wait some time... |
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423 | */ |
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424 | /* |
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425 | * FIXME: poll, until SDMA is finished |
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426 | */ |
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427 | volatile int32_t i; |
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428 | for (i = 0;i < 10000;i++) {}; |
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429 | } |
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430 | |
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431 | do { |
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432 | nxt_bd_idx = TaskBDRelease(is_write |
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433 | ? pcmcia_ide_txTaskId |
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434 | : pcmcia_ide_rxTaskId); |
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435 | if ((nxt_bd_idx != TASK_ERR_BD_RING_EMPTY) && |
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436 | (nxt_bd_idx != TASK_ERR_BD_BUSY)) { |
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437 | (*cbuf)++; |
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438 | (*pos) += bufs[bufs_from_dma].length; |
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439 | bufs_from_dma++; |
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440 | } |
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441 | } while ((nxt_bd_idx != TASK_ERR_BD_RING_EMPTY) && |
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442 | (nxt_bd_idx != TASK_ERR_BD_BUSY) && |
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443 | (bufs_from_dma < bufs_to_dma)); |
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444 | } |
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445 | } |
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446 | #endif /* IDE_USE_DMA */ |
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447 | |
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448 | |
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449 | void mpc5200_pcmciaide_read_block(int minor, uint32_t block_size, rtems_blkdev_sg_buffer *bufs, |
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450 | uint32_t *cbuf, uint32_t *pos) |
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451 | { |
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452 | |
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453 | volatile uint32_t *ata_reg=mpc5200_ata_drive_regs[IDE_REGISTER_DATA_WORD]; |
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454 | uint16_t cnt = 0; |
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455 | uint16_t *lbuf = (uint16_t*)((uint8_t*)(bufs[(*cbuf)].buffer)+(*pos)); |
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456 | uint32_t llength = bufs[(*cbuf)].length; |
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457 | bool use_dma; |
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458 | |
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459 | #if IDE_USE_STATISTICS |
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460 | mpc5200_pcmciaide_read_block_call_cnt++; |
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461 | #endif |
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462 | #if IDE_READ_USE_DMA |
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463 | /* |
---|
464 | * FIXME: walk through buffer list. If any buffer has other size than default, |
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465 | * then do not use DMA |
---|
466 | * Is this needed? |
---|
467 | */ |
---|
468 | use_dma = true; |
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469 | /* use_dma = false; */ |
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470 | #else |
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471 | use_dma = false; |
---|
472 | #endif |
---|
473 | if (use_dma) { |
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474 | /* |
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475 | * FIXME: wait for DRQ ready |
---|
476 | * check, that once DRQ is ready, we really can send ALL data for this |
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477 | * type of transfer mode |
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478 | */ |
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479 | while ((GET_UP_BYTE_OF_MPC5200_ATA_DRIVE_REG((volatile uint32_t) |
---|
480 | (mpc5200.ata_dctr_dasr)) & |
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481 | IDE_REGISTER_STATUS_DRQ) == 0); |
---|
482 | /* |
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483 | * translate (part of) buffer list into DMA BDs |
---|
484 | * only last (available) DMA BD sends interrupt |
---|
485 | * DMA BDs may get ready as soon as possible |
---|
486 | */ |
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487 | mpc5200_pcmciaide_dma_blockop(FALSE, /* read operation */ |
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488 | minor, |
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489 | block_size,bufs,cbuf,pos); |
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490 | } |
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491 | else { |
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492 | #if IDE_USE_READ_PIO_OPT |
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493 | while(cnt < block_size) { |
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494 | |
---|
495 | *lbuf++ = GET_UP_WORD_OF_MPC5200_ATA_DRIVE_REG(*(volatile uint32_t *)(ata_reg)); /* only 16 bit data port */ |
---|
496 | cnt += 2; |
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497 | (*pos) += 2; |
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498 | |
---|
499 | if((*pos) == llength) { |
---|
500 | |
---|
501 | (*pos) = 0; |
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502 | (*cbuf)++; |
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503 | lbuf = bufs[(*cbuf)].buffer; |
---|
504 | llength = bufs[(*cbuf)].length; |
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505 | |
---|
506 | } |
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507 | } |
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508 | #else |
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509 | |
---|
510 | while((GET_UP_BYTE_OF_MPC5200_ATA_DRIVE_REG((volatile uint32_t)(mpc5200.ata_dctr_dasr)) & IDE_REGISTER_STATUS_DRQ) && (cnt < block_size)) { |
---|
511 | |
---|
512 | *lbuf++ = *(volatile uint16_t *)(ata_reg); /* only 16 bit data port */ |
---|
513 | cnt += 2; |
---|
514 | (*pos) += 2; |
---|
515 | |
---|
516 | if((*pos) == llength) { |
---|
517 | (*pos) = 0; |
---|
518 | (*cbuf)++; |
---|
519 | lbuf = bufs[(*cbuf)].buffer; |
---|
520 | llength = bufs[(*cbuf)].length; |
---|
521 | } |
---|
522 | } |
---|
523 | #endif |
---|
524 | while (cnt < block_size) { |
---|
525 | *lbuf++ = 0; /* fill buffer with dummy data */ |
---|
526 | cnt += 2; |
---|
527 | (*pos) += 2; |
---|
528 | |
---|
529 | if((*pos) == llength) { |
---|
530 | (*pos) = 0; |
---|
531 | (*cbuf)++; |
---|
532 | lbuf = bufs[(*cbuf)].buffer; |
---|
533 | llength = bufs[(*cbuf)].length; |
---|
534 | } |
---|
535 | } |
---|
536 | } |
---|
537 | } |
---|
538 | |
---|
539 | void mpc5200_pcmciaide_write_block(int minor, uint32_t block_size, |
---|
540 | rtems_blkdev_sg_buffer *bufs, uint32_t *cbuf, |
---|
541 | uint32_t *pos) |
---|
542 | |
---|
543 | { |
---|
544 | |
---|
545 | |
---|
546 | volatile uint32_t *ata_reg = mpc5200_ata_drive_regs[IDE_REGISTER_DATA_WORD]; |
---|
547 | uint16_t cnt = 0; |
---|
548 | uint16_t *lbuf = (uint16_t *)((uint8_t *)(bufs[(*cbuf)].buffer) + (*pos)); |
---|
549 | uint32_t llength = bufs[(*cbuf)].length; |
---|
550 | bool use_dma; |
---|
551 | |
---|
552 | #if IDE_USE_STATISTICS |
---|
553 | mpc5200_pcmciaide_write_block_call_cnt++; |
---|
554 | #endif |
---|
555 | #if IDE_WRITE_USE_DMA |
---|
556 | /* |
---|
557 | * FIXME: walk through buffer list. If any buffer has other size than default, |
---|
558 | * then do not use DMA |
---|
559 | * Is this needed? |
---|
560 | */ |
---|
561 | use_dma = true; |
---|
562 | #else |
---|
563 | use_dma = false; |
---|
564 | #endif |
---|
565 | |
---|
566 | if (use_dma) { |
---|
567 | /* |
---|
568 | * wait for DRQ ready |
---|
569 | * FIXME: check, that once DRQ is ready, we really can send ALL data for this |
---|
570 | * type of transfer mode |
---|
571 | */ |
---|
572 | while ((GET_UP_BYTE_OF_MPC5200_ATA_DRIVE_REG((volatile uint32_t) |
---|
573 | (mpc5200.ata_dctr_dasr)) & |
---|
574 | IDE_REGISTER_STATUS_DRQ) == 0); |
---|
575 | /* |
---|
576 | * translate (part of) buffer list into DMA BDs |
---|
577 | * only last (available) DMA BD sends interrupt |
---|
578 | * DMA BDs may get ready as soon as possible |
---|
579 | */ |
---|
580 | mpc5200_pcmciaide_dma_blockop(true, /* write opeartion */ |
---|
581 | minor, |
---|
582 | block_size,bufs,cbuf,pos); |
---|
583 | } |
---|
584 | else { |
---|
585 | #if IDE_USE_WRITE_PIO_OPT |
---|
586 | while(cnt < block_size) { |
---|
587 | int32_t loop_cnt,loop_max; |
---|
588 | |
---|
589 | #if IDE_USE_STATISTICS |
---|
590 | mpc5200_pcmciaide_write_block_block_cnt++; |
---|
591 | #endif |
---|
592 | |
---|
593 | loop_max = llength - (*pos) ; |
---|
594 | if (loop_max > (block_size - cnt)) { |
---|
595 | loop_max = (block_size - cnt); |
---|
596 | } |
---|
597 | for (loop_cnt = loop_max/2;loop_cnt > 0;loop_cnt--) { |
---|
598 | *(volatile uint32_t *)(ata_reg) = |
---|
599 | SET_UP_WORD_OF_MPC5200_ATA_DRIVE_REG(*lbuf++); /* only 16 bit data port */ |
---|
600 | } |
---|
601 | cnt += loop_max; |
---|
602 | (*pos) += loop_max; |
---|
603 | |
---|
604 | if((*pos) == llength) { |
---|
605 | |
---|
606 | (*pos) = 0; |
---|
607 | (*cbuf)++; |
---|
608 | lbuf = bufs[(*cbuf)].buffer; |
---|
609 | llength = bufs[(*cbuf)].length; |
---|
610 | } |
---|
611 | } |
---|
612 | #else |
---|
613 | while((GET_UP_BYTE_OF_MPC5200_ATA_DRIVE_REG((volatile uint32_t)(mpc5200.ata_dctr_dasr)) |
---|
614 | & IDE_REGISTER_STATUS_DRQ) |
---|
615 | && (cnt < block_size)) { |
---|
616 | *(volatile uint16_t *)(ata_reg) = *lbuf++; /* only 16 bit data port */ |
---|
617 | cnt += 2; |
---|
618 | (*pos) += 2; |
---|
619 | |
---|
620 | if((*pos) == llength) { |
---|
621 | (*pos) = 0; |
---|
622 | (*cbuf)++; |
---|
623 | lbuf = bufs[(*cbuf)].buffer; |
---|
624 | llength = bufs[(*cbuf)].length; |
---|
625 | } |
---|
626 | } |
---|
627 | #endif |
---|
628 | } |
---|
629 | } |
---|
630 | |
---|
631 | int mpc5200_pcmciaide_control(int minor, uint32_t cmd, void * arg) |
---|
632 | { |
---|
633 | return RTEMS_SUCCESSFUL; |
---|
634 | } |
---|
635 | |
---|
636 | void mpc5200_pcmciaide_initialize(int minor) |
---|
637 | { |
---|
638 | #if defined (BRS5L) |
---|
639 | struct mpc5200_gpt *gpt = (struct mpc5200_gpt *)(&mpc5200.gpt[GPT7]); |
---|
640 | |
---|
641 | /* invert ATA reset on GPT7 */ |
---|
642 | gpt->emsel = (GPT_EMSEL_GPIO_OUT_HIGH | GPT_EMSEL_TIMER_MS_GPIO); |
---|
643 | #endif |
---|
644 | /* reset ata host contr. and FIFO */ |
---|
645 | mpc5200.ata_hcfg |= (ATA_HCFG_SMR | ATA_HCFG_FR); |
---|
646 | mpc5200.ata_hcfg &= ~(ATA_HCFG_SMR | ATA_HCFG_FR); |
---|
647 | |
---|
648 | /* for the first access set lowest performance transfer mode to PIO3 */ |
---|
649 | mpc5200_pcmciaide_config_io_speed(minor, ATA_MODES_PIO3); |
---|
650 | |
---|
651 | /* enable PIO operations (PIO 3/4) */ |
---|
652 | mpc5200.ata_hcfg |= ATA_HCFG_IORDY; |
---|
653 | |
---|
654 | #ifdef IDE_USE_INT |
---|
655 | mpc5200.ata_hcfg |= ATA_HCFG_IE ; |
---|
656 | #endif |
---|
657 | |
---|
658 | #if IDE_USE_DMA |
---|
659 | mpc5200_pcmciaide_dma_init(minor); |
---|
660 | #endif |
---|
661 | } |
---|
662 | |
---|
663 | |
---|
664 | /* |
---|
665 | * The following table configures the functions used for IDE drivers |
---|
666 | * in this BSP. |
---|
667 | */ |
---|
668 | ide_ctrl_fns_t mpc5200_pcmciaide_ctrl_fns = |
---|
669 | { |
---|
670 | mpc5200_pcmciaide_probe, |
---|
671 | mpc5200_pcmciaide_initialize, |
---|
672 | mpc5200_pcmciaide_control, |
---|
673 | mpc5200_pcmciaide_read_reg, |
---|
674 | mpc5200_pcmciaide_write_reg, |
---|
675 | mpc5200_pcmciaide_read_block, |
---|
676 | mpc5200_pcmciaide_write_block, |
---|
677 | mpc5200_pcmciaide_config_io_speed |
---|
678 | }; |
---|
679 | |
---|