1 | /*===============================================================*\ |
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2 | | Project: RTEMS generic MPC5200 BSP | |
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3 | +-----------------------------------------------------------------+ |
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4 | | Partially based on the code references which are named below. | |
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5 | | Adaptions, modifications, enhancements and any recent parts of | |
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6 | | the code are: | |
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7 | | Copyright (c) 2005 | |
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8 | | Embedded Brains GmbH | |
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9 | | Obere Lagerstr. 30 | |
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10 | | D-82178 Puchheim | |
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11 | | Germany | |
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12 | | rtems@embedded-brains.de | |
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13 | | | |
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14 | | Reworked by Joel Sherrill to use clockdrv_shell.c | |
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15 | +-----------------------------------------------------------------+ |
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16 | | The license and distribution terms for this file may be | |
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17 | | found in the file LICENSE in this distribution or at | |
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18 | | | |
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19 | | http://www.rtems.com/license/LICENSE. | |
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20 | | | |
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21 | +-----------------------------------------------------------------+ |
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22 | | this file contains the clock driver functions | |
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23 | \*===============================================================*/ |
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24 | /***********************************************************************/ |
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25 | /* */ |
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26 | /* Module: clock.c */ |
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27 | /* Date: 07/17/2003 */ |
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28 | /* Purpose: RTEMS MPC5x00 clock driver */ |
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29 | /* */ |
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30 | /*---------------------------------------------------------------------*/ |
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31 | /* */ |
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32 | /* Description: Use one of the GPTs for time base generation */ |
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33 | /* instead of the decrementer. The routine initializes */ |
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34 | /* the General Purpose Timer GPT6 on the MPC5x00. */ |
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35 | /* The tick frequency is specified by the bsp. */ |
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36 | /* */ |
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37 | /*---------------------------------------------------------------------*/ |
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38 | /* */ |
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39 | /* Code */ |
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40 | /* References: Clock driver for PPC403 */ |
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41 | /* Module: clock.c */ |
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42 | /* Project: RTEMS 4.6.0pre1 / PPC403 BSP */ |
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43 | /* Version 1.16 */ |
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44 | /* Date: 2002/11/01 */ |
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45 | /* Author(s) / Copyright(s): */ |
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46 | /* */ |
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47 | /* Author: Jay Monkman (jmonkman@frasca.com) */ |
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48 | /* Copyright (C) 1998 by Frasca International, Inc. */ |
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49 | /* */ |
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50 | /* Derived from c/src/lib/libcpu/ppc/ppc403/clock/clock.c: */ |
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51 | /* */ |
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52 | /* Author: Andrew Bray <andy@i-cubed.co.uk> */ |
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53 | /* */ |
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54 | /* COPYRIGHT (c) 1995 by i-cubed ltd. */ |
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55 | /* */ |
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56 | /* To anyone who acknowledges that this file is provided "AS IS" */ |
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57 | /* without any express or implied warranty: */ |
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58 | /* permission to use, copy, modify, and distribute this file */ |
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59 | /* for any purpose is hereby granted without fee, provided that */ |
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60 | /* the above copyright notice and this notice appears in all */ |
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61 | /* copies, and that the name of i-cubed limited not be used in */ |
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62 | /* advertising or publicity pertaining to distribution of the */ |
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63 | /* software without specific, written prior permission. */ |
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64 | /* i-cubed limited makes no representations about the suitability */ |
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65 | /* of this software for any purpose. */ |
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66 | /* */ |
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67 | /* Derived from c/src/lib/libcpu/hppa1.1/clock/clock.c: */ |
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68 | /* */ |
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69 | /* Modifications for deriving timer clock from cpu system clock by */ |
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70 | /* Thomas Doerfler <td@imd.m.isar.de> */ |
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71 | /* for these modifications: */ |
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72 | /* COPYRIGHT (c) 1997 by IMD, Puchheim, Germany. */ |
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73 | /* */ |
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74 | /* COPYRIGHT (c) 1989-2007. */ |
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75 | /* On-Line Applications Research Corporation (OAR). */ |
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76 | /* */ |
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77 | /* The license and distribution terms for this file may be */ |
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78 | /* found in the file LICENSE in this distribution or at */ |
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79 | /* http://www.rtems.com/license/LICENSE. */ |
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80 | /* */ |
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81 | /* Modifications for PPC405GP by Dennis Ehlin */ |
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82 | /*---------------------------------------------------------------------*/ |
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83 | /* */ |
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84 | /* Partially based on the code references which are named above. */ |
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85 | /* Adaptions, modifications, enhancements and any recent parts of */ |
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86 | /* the code are under the right of */ |
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87 | /* */ |
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88 | /* IPR Engineering, Dachauer StraÃe 38, D-80335 MÃŒnchen */ |
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89 | /* Copyright(C) 2003 */ |
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90 | /* */ |
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91 | /*---------------------------------------------------------------------*/ |
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92 | /* */ |
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93 | /* IPR Engineering makes no representation or warranties with */ |
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94 | /* respect to the performance of this computer program, and */ |
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95 | /* specifically disclaims any responsibility for any damages, */ |
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96 | /* special or consequential, connected with the use of this program. */ |
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97 | /* */ |
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98 | /*---------------------------------------------------------------------*/ |
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99 | /* */ |
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100 | /* Version history: 1.0 */ |
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101 | /* */ |
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102 | /***********************************************************************/ |
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103 | |
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104 | #include <bsp.h> |
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105 | #include <rtems/bspIo.h> |
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106 | #include <bsp/irq.h> |
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107 | |
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108 | #include <rtems.h> |
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109 | #include <rtems/clockdrv.h> |
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110 | |
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111 | #include <stdlib.h> /* for atexit() */ |
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112 | #include "../include/mpc5200.h" |
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113 | |
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114 | #define GPT (BSP_PERIODIC_TIMER - BSP_SIU_IRQ_TMR0) |
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115 | |
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116 | extern uint32_t bsp_clicks_per_usec; |
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117 | |
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118 | /* this lets us do nanoseconds since last tick */ |
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119 | uint64_t Clock_last_TBR; |
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120 | volatile uint32_t counter_value; |
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121 | volatile int ClockInitialized = 0; |
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122 | |
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123 | /* |
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124 | * ISR Handlers |
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125 | */ |
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126 | void mpc5200_gpt_clock_isr(rtems_vector_number vector, void *handle) |
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127 | { |
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128 | uint32_t status; |
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129 | struct mpc5200_gpt *gpt = (struct mpc5200_gpt *)handle; |
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130 | |
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131 | status = gpt->status; |
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132 | |
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133 | if (ClockInitialized && (status & GPT_STATUS_TEXP)) { |
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134 | gpt->status |= GPT_STATUS_RESET; |
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135 | Clock_last_TBR = PPC_Get_timebase_register(); |
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136 | |
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137 | Clock_driver_ticks++; |
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138 | rtems_clock_tick(); |
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139 | } |
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140 | } |
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141 | |
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142 | /* |
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143 | * Initialize MPC5x00 GPT |
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144 | */ |
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145 | void mpc5200_init_gpt(uint32_t gpt_no) |
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146 | { |
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147 | struct mpc5200_gpt *gpt = (struct mpc5200_gpt *)(&mpc5200.gpt[gpt_no]); |
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148 | |
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149 | gpt->status = GPT_STATUS_RESET; |
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150 | gpt->emsel = GPT_EMSEL_CE | GPT_EMSEL_ST_CONT | GPT_EMSEL_INTEN | |
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151 | GPT_EMSEL_GPIO_OUT_HIGH | GPT_EMSEL_TIMER_MS_GPIO; |
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152 | |
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153 | } |
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154 | |
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155 | /* |
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156 | * Set MPC5x00 GPT counter |
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157 | */ |
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158 | void mpc5200_set_gpt_count(uint32_t counter_value, uint32_t gpt_no) |
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159 | { |
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160 | uint32_t prescaler_value = 1; |
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161 | uint32_t counter = counter_value; |
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162 | struct mpc5200_gpt *gpt = (struct mpc5200_gpt *)(&mpc5200.gpt[gpt_no]); |
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163 | |
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164 | /* Calculate counter/prescaler value, e.g. |
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165 | * IPB_Clock=33MHz -> Int. every 0,3 nsecs. - 130 secs |
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166 | */ |
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167 | while ((counter >= (1 << 16)) && (prescaler_value < (1 << 16))) { |
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168 | prescaler_value++; |
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169 | counter = counter_value / prescaler_value; |
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170 | } |
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171 | |
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172 | counter = (uint16_t)counter; |
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173 | |
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174 | gpt->count_in = (prescaler_value << 16) + counter; |
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175 | |
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176 | } |
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177 | |
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178 | uint32_t bsp_clock_nanoseconds_since_last_tick(void) |
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179 | { |
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180 | uint64_t new_tbr; |
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181 | uint64_t bus_cycles; |
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182 | uint32_t nsecs; |
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183 | |
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184 | new_tbr = PPC_Get_timebase_register(); |
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185 | bus_cycles = (new_tbr - Clock_last_TBR) * 4; |
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186 | nsecs = (uint32_t) (bus_cycles / (XLB_CLOCK / 1000000)) * 1000; |
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187 | |
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188 | return nsecs; |
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189 | } |
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190 | |
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191 | /* |
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192 | * Enable MPC5x00 GPT interrupt |
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193 | */ |
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194 | void mpc5200_enable_gpt_int(uint32_t gpt_no) |
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195 | { |
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196 | struct mpc5200_gpt *gpt = (struct mpc5200_gpt *)(&mpc5200.gpt[gpt_no]); |
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197 | |
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198 | gpt->emsel |= GPT_EMSEL_CE | GPT_EMSEL_INTEN; |
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199 | Clock_last_TBR = PPC_Get_timebase_register(); |
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200 | } |
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201 | |
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202 | /* |
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203 | * Disable MPC5x00 GPT interrupt |
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204 | */ |
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205 | void mpc5200_disable_gpt_int(uint32_t gpt_no) |
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206 | { |
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207 | struct mpc5200_gpt *gpt = (struct mpc5200_gpt *)(&mpc5200.gpt[gpt_no]); |
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208 | |
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209 | gpt->emsel &= ~(GPT_EMSEL_CE | GPT_EMSEL_INTEN); |
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210 | } |
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211 | |
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212 | /* |
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213 | * Check MPC5x00 GPT status |
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214 | */ |
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215 | uint32_t mpc5200_check_gpt_status(uint32_t gpt_no) |
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216 | { |
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217 | struct mpc5200_gpt *gpt = (struct mpc5200_gpt *)(&mpc5200.gpt[gpt_no]); |
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218 | |
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219 | return ((gpt->emsel) & (GPT_EMSEL_CE | GPT_EMSEL_INTEN)); |
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220 | } |
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221 | |
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222 | void clockOn() |
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223 | { |
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224 | uint32_t gpt_no; |
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225 | |
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226 | gpt_no = BSP_SIU_IRQ_TMR0 - BSP_PERIODIC_TIMER; |
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227 | |
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228 | counter_value = rtems_configuration_get_microseconds_per_tick() * |
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229 | bsp_clicks_per_usec; |
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230 | |
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231 | mpc5200_set_gpt_count(counter_value, gpt_no); |
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232 | mpc5200_enable_gpt_int(gpt_no); |
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233 | |
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234 | ClockInitialized = 1; |
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235 | } |
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236 | |
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237 | void clockOff() |
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238 | { |
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239 | uint32_t gpt_no; |
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240 | |
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241 | gpt_no = BSP_SIU_IRQ_TMR0 - BSP_PERIODIC_TIMER; |
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242 | |
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243 | mpc5200_disable_gpt_int(gpt_no); |
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244 | |
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245 | ClockInitialized = 0; |
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246 | } |
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247 | |
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248 | int BSP_get_clock_irq_level(void) |
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249 | { |
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250 | /* |
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251 | * Caution : if you change this, you must change the |
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252 | * definition of BSP_PERIODIC_TIMER accordingly |
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253 | */ |
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254 | return BSP_PERIODIC_TIMER; |
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255 | } |
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256 | |
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257 | int BSP_disconnect_clock_handler (unsigned gpt_no) |
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258 | { |
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259 | rtems_status_code sc = RTEMS_SUCCESSFUL; |
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260 | |
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261 | if ((gpt_no < GPT0) || (gpt_no > GPT7)) { |
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262 | return 0; |
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263 | } |
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264 | |
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265 | clockOff( BSP_PERIODIC_TIMER); |
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266 | |
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267 | sc = rtems_interrupt_handler_remove( |
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268 | BSP_PERIODIC_TIMER, |
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269 | mpc5200_gpt_clock_isr, |
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270 | &mpc5200.gpt [gpt_no] |
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271 | ); |
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272 | if (sc != RTEMS_SUCCESSFUL) { |
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273 | return 0; |
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274 | } |
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275 | |
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276 | return 1; |
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277 | } |
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278 | |
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279 | int BSP_connect_clock_handler (unsigned gpt_no) |
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280 | { |
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281 | rtems_status_code sc = RTEMS_SUCCESSFUL; |
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282 | |
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283 | if ((gpt_no < GPT0) || (gpt_no > GPT7)) { |
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284 | printk("Unable to set system clock handler\n"); |
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285 | rtems_fatal_error_occurred(1); |
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286 | } |
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287 | |
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288 | sc = rtems_interrupt_handler_install( |
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289 | BSP_PERIODIC_TIMER, |
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290 | "Clock", |
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291 | RTEMS_INTERRUPT_UNIQUE, |
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292 | mpc5200_gpt_clock_isr, |
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293 | &mpc5200.gpt [gpt_no] |
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294 | ); |
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295 | if (sc != RTEMS_SUCCESSFUL) { |
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296 | return 0; |
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297 | } |
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298 | |
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299 | clockOn(); |
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300 | |
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301 | return 1; |
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302 | } |
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303 | |
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304 | #define CLOCK_VECTOR 0 |
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305 | |
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306 | #define Clock_driver_support_at_tick() \ |
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307 | do { \ |
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308 | uint32_t status; \ |
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309 | struct mpc5200_gpt *gpt = (struct mpc5200_gpt *)(&mpc5200.gpt[GPT]); \ |
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310 | \ |
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311 | status = gpt->status; \ |
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312 | \ |
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313 | if (ClockInitialized && (status & GPT_STATUS_TEXP)) { \ |
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314 | gpt->status |= GPT_STATUS_RESET; \ |
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315 | Clock_last_TBR = PPC_Get_timebase_register(); \ |
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316 | } \ |
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317 | } while(0) |
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318 | |
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319 | #define Clock_driver_support_install_isr( _new, _old ) \ |
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320 | do { \ |
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321 | (_old) = NULL; /* avoid warning */; \ |
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322 | BSP_connect_clock_handler(GPT); \ |
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323 | } while(0) |
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324 | |
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325 | /* This driver does this in clockOn called at connection time */ |
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326 | #define Clock_driver_support_initialize_hardware() \ |
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327 | do { \ |
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328 | counter_value = rtems_configuration_get_microseconds_per_tick() * \ |
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329 | bsp_clicks_per_usec; \ |
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330 | mpc5200_init_gpt(GPT); \ |
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331 | mpc5200_set_gpt_count(counter_value, GPT); \ |
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332 | } while (0) |
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333 | |
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334 | #define Clock_driver_nanoseconds_since_last_tick \ |
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335 | bsp_clock_nanoseconds_since_last_tick |
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336 | |
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337 | #define Clock_driver_support_shutdown_hardware() \ |
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338 | do { \ |
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339 | (void) BSP_disconnect_clock_handler (GPT); \ |
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340 | } while (0) |
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341 | |
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342 | #include "../../../shared/clockdrv_shell.c" |
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343 | |
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