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source: rtems/c/src/lib/libbsp/powerpc/gen5200/bestcomm/task_api/bestcomm_cntrl.h @ ca680bc5

4.104.114.84.95

Last change on this file since ca680bc5 was ca680bc5, checked in by Ralf Corsepius <ralf.corsepius@…>, on 12/31/05 at 05:09:26
New (CVS import Thomas Doerfler <Thomas.Doerfler@…>'s submission).
Property mode set to `100644`
File size: 10.5 KB

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1	#ifndef __TASK_API_BESTCOMM_CNTRL_H
2	#define __TASK_API_BESTCOMM_CNTRL_H 1
3
4	/******************************************************************************
5	*
6	* Copyright (c) 2004 Freescale Semiconductor, Inc.
7	*
8	* Permission is hereby granted, free of charge, to any person obtaining a
9	* copy of this software and associated documentation files (the "Software"),
10	* to deal in the Software without restriction, including without limitation
11	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
12	* and/or sell copies of the Software, and to permit persons to whom the
13	* Software is furnished to do so, subject to the following conditions:
14	*
15	* The above copyright notice and this permission notice shall be included
16	* in all copies or substantial portions of the Software.
17	*
18	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
22	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
24	* OTHER DEALINGS IN THE SOFTWARE.
25	*
26	* Filename: $Source$
27	* Author: $Author$
28	* Locker: $Locker$
29	* State: $State$
30	* Revision: $Revision$
31	*
32	******************************************************************************/
33
34	/*******************************************************************************
35	* Defines to control SmartDMA and its tasks. These defines are used for the
36	* task build process to minimize disconnects at the task/driver interface.
37	******************************************************************************/
38
39	#define SDMA_INT_BIT_DBG 31 /* debug interrupt bit */
40	#define SDMA_INT_BIT_TEA 28 /* TEA interrupt bit */
41	#define SDMA_INT_BIT_TEA_TASK 24 /* lsb for TEA task number */
42	#define SDMA_INT_BIT_IMPL 0x9000FFFF
43
44	#define SDMA_PTDCTRL_BIT_TEA 14 /* TEA detection enable bit */
45
46	#define SDMA_TCR_BIT_AUTO 15 /* auto start bit */
47	#define SDMA_TCR_BIT_HOLD 5 /* hold initiator bit */
48
49	#define SDMA_STAT_BIT_ALARM 17
50	#define SDMA_FIFO_ALARM_MASK 0x0020000
51
52	#define SDMA_DRD_BIT_TFD 27 /* mark last buffer of frame */
53	#define SDMA_DRD_BIT_INT 26 /* interrupt after buffer processed */
54	#define SDMA_DRD_BIT_INIT 21 /* lsb position of initiator */
55	#define SDMA_DRD_MASK_FLAGS 0x0C000000 /* BD_FLAGS flag bits */
56	#define SDMA_DRD_MASK_LENGTH 0x03FFFFFF /* BD_FLAGS length mask */
57	#define SDMA_BD_BIT_READY 30 /* Status BD ready bit */
58	#ifdef SAS_COMPILE
59	#define SDMA_BD_MASK_READY constant(1<<SDMA_BD_BIT_READY)
60	#else
61	#define SDMA_BD_MASK_READY (1<<SDMA_BD_BIT_READY)
62	#endif
63	#define SDMA_BD_MASK_SIGN 0x7FFFFFFF /* task code needs Status>0 */
64
65	#define SDMA_PRAGMA_BIT_RSV 7 /* reserved pragma bit */
66	#define SDMA_PRAGMA_BIT_PRECISE_INC 6 /* increment 0=when possible, 1=iter end */
67	#define SDMA_PRAGMA_BIT_RST_ERROR_NO 5 /* don't reset errors on task enable */
68	#define SDMA_PRAGMA_BIT_PACK 4 /* pack data enable */
69	#define SDMA_PRAGMA_BIT_INTEGER 3 /* data alignment 0=frac(msb), 1=int(lsb) */
70	#define SDMA_PRAGMA_BIT_SPECREAD 2 /* XLB speculative read enable */
71	#define SDMA_PRAGMA_BIT_CW 1 /* write line buffer enable */
72	#define SDMA_PRAGMA_BIT_RL 0 /* read line buffer enable */
73
74	#define SDMA_TASK_ENTRY_BYTES 32 /* Bytes per task in entry table */
75	#define SDMA_TASK_GROUP_NUM 16 /* Number of tasks per task group */
76	#define SDMA_TASK_GROUP_BYTES (SDMA_TASK_ENTRY_BYTES*SDMA_TASK_GROUP_NUM)
77
78
79	/*******************************************************************************
80	* Task group control macros, use when TaskNum > 15
81	******************************************************************************/
82	#define SDMA_TASKNUM_EXT(OldTaskNum) (OldTaskNum%16)
83
84	#define SDMA_TASKBAR_CHANGE(sdma, OldTaskNum) { \
85	sdma->taskBar += (((int)(OldTaskNum/SDMA_TASK_GROUP_NUM))*SDMA_TASK_GROUP_BYTES); \
86	}
87
88	#define SDMA_TASKBAR_RESTORE(sdma, OldTaskNum) { \
89	sdma->taskBar -= (((int)(OldTaskNum/SDMA_TASK_GROUP_NUM))*SDMA_TASK_GROUP_BYTES); \
90	}
91
92
93	/*******************************************************************************
94	* Task control macros
95	******************************************************************************/
96	#define SDMA_TASK_CFG(RegAddr, TaskNum, AutoStart, AutoStartNum) { \
97	(((uint16 )RegAddr)+TaskNum) = (uint16)(0x0000 \| \
98	((AutoStart!=0)<<7) \| \
99	(AutoStartNum&0xF) ); \
100	}
101
102	#define SDMA_TASK_AUTO_START(RegAddr, TaskNum, AutoStart, AutoStartNum) { \
103	(((uint16 )RegAddr)+TaskNum) = (uint16)(((((uint16 )RegAddr)+TaskNum) & \
104	(uint16) 0xff30) \| ((uint16)(0x0000 \| \
105	((AutoStart!=0)<<7) \| \
106	(AutoStartNum&0xF)) )); \
107	}
108
109	#define SDMA_TASK_ENABLE(RegAddr, TaskNum) { \
110	(((uint16 )RegAddr)+TaskNum) \|= (uint16)0x8000; \
111	}
112
113	#define SDMA_TASK_DISABLE(RegAddr, TaskNum) { \
114	(((uint16 )RegAddr)+TaskNum) &= ~(uint16)0x8000; \
115	}
116
117	#define SDMA_TASK_STATUS(RegAddr, TaskNum) \
118	(((uint16 )RegAddr)+TaskNum)
119
120
121	/*******************************************************************************
122	* Interrupt control macros
123	******************************************************************************/
124	#define SDMA_INT_ENABLE(RegAddr, Bit) { \
125	((uint32 )RegAddr) &= ~((uint32)(1<<Bit)); \
126	}
127
128	#define SDMA_INT_DISABLE(RegAddr, Bit) { \
129	((uint32 )(RegAddr)) \|= ((uint32)(1<<Bit)); \
130	}
131
132	#define SDMA_INT_SOURCE(RegPend, RegMask) \
133	(((uint32 )(RegPend)) & (~((uint32 )(RegMask))) & (uint32)SDMA_INT_BIT_IMPL)
134
135	#define SDMA_INT_PENDING(RegPend, RegMask) \
136	(((uint32 )(RegPend)) & (~((uint32 )(RegMask))))
137
138	#define SDMA_INT_TEST(IntSource, Bit) \
139	(((uint32)IntSource) & ((uint32)(1<<Bit)))
140
141	/*
142	* define SDMA_INT_FIND to get int bit rather than scan all bits use
143	* cntlzw
144	*/
145
146	/* Clear the IntPend bit */
147	#define SDMA_CLEAR_IEVENT(RegAddr, Bit) { \
148	((uint32 )RegAddr) = ((uint32)(1<<Bit)); \
149	}
150
151	#define SDMA_GET_PENDINGBIT(sdma, Bit) \
152	(sdma->IntPend & (uint32)(1<<Bit))
153
154	#define SDMA_GET_MASKBIT(sdma, Bit) \
155	(sdma->IntMask & (uint32)(1<<Bit))
156
157
158	/*******************************************************************************
159	* SmartDMA FIFO control macros
160	******************************************************************************/
161
162	/*******************************************************************************
163	* SmartDMA TEA detection control macros
164	******************************************************************************/
165	/* Enable SmartDMA TEA detection and TEA interrupt */
166	#define SDMA_TEA_ENABLE(sdma) { \
167	SDMA_INT_ENABLE(sdma, SDMA_INT_BIT_TEA); \
168	sdma->PtdCntrl &= ~((uint32)(1<<SDMA_PTDCTRL_BIT_TEA)); \
169	}
170
171	/* Disable SmartDMA TEA detection and TEA interrupt */
172	#define SDMA_TEA_DISABLE(sdma) { \
173	SDMA_INT_DISABLE(sdma, SDMA_INT_BIT_TEA); \
174	sdma->PtdCntrl \|= ((uint32)(1<<SDMA_PTDCTRL_BIT_TEA)); \
175	}
176
177	/* Clear the TEA interrupt */
178	#define SDMA_TEA_CLEAR(sdma) { \
179	sdma->IntPend = ((uint32)(0x1F<<SDMA_INT_BIT_TEA_TASK)); \
180	}
181
182	/* Determine which task caused a TEA on the XLB */
183	#define SDMA_TEA_SOURCE(RegPend) \
184	(uint32)((((uint32 )RegPend)>>SDMA_INT_BIT_TEA_TASK) & 0xF)
185
186
187	/*******************************************************************************
188	* SmartDMA debug control macros
189	******************************************************************************/
190	/* Enable the SmartDMA debug unit and DBG interrupt */
191	/* add sdma->dbg_regs setup? */
192	#define SDMA_DBG_ENABLE(sdma) { \
193	SDMA_INT_ENABLE(sdma, SDMA_INT_BIT_DBG); \
194	}
195
196	#define SDMA_DBG_DISABLE(sdma) { \
197	SDMA_INT_DISABLE(sdma, SDMA_INT_BIT_DBG); \
198	}
199
200	/* Clear the debug interrupt */
201	#define SDMA_DBG_CLEAR(sdma) { \
202	SDMA_CLEAR_IEVENT(sdma, SDMA_INT_BIT_DBG); \
203	}
204
205	#define SDMA_DBG_MDE(dst, sdma, addr) { \
206	sdma->MDEDebug = addr; \
207	dst = sdma->MDEDebug; \
208	}
209
210	#define SDMA_DBG_ADS(dst, sdma, addr) { \
211	sdma->ADSDebug = addr; \
212	dst = sdma->ADSDebug; \
213	}
214
215	#define SDMA_DBG_PTD(dst, sdma, addr) { \
216	sdma->PTDDebug = addr; \
217	dst = sdma->PTDDebug; \
218	}
219
220
221	/*******************************************************************************
222	* Initiator control macros
223	******************************************************************************/
224
225	/* This macro may not work, getting compile errors */
226	/* Set the Transfer Size */
227	/* Note that masking the size w/ 0x3 gives the desired value for uint32 */
228	/* (expressed as 4), namely 0. */
229	#define SDMA_SET_SIZE(RegAddr, TaskNum, SrcSize, DstSize) \
230	(((uint8 )RegAddr)+((uint32)(TaskNum/2))) = \
231	(uint8)(((((uint8 )RegAddr)+((uint32)(TaskNum/2))) & \
232	((TaskNum%2) ? 0xf0 : 0x0f)) \| \
233	((uint8)(((SrcSize & 0x3)<<2) \| \
234	( DstSize & 0x3 ) ) <<(4*((int)(1-(TaskNum%2))))));
235
236	/* This macro may not work */
237	/* Set the Initiator in TCR */
238	#define SDMA_SET_INIT(RegAddr, TaskNum, Initiator) \
239	{ \
240	(((uint16 )RegAddr)+TaskNum) &= (uint16)0xE0FF; \
241	(((uint16 )RegAddr)+TaskNum) \|= (((0x01F & Initiator)<<8) \| \
242	(0<<SDMA_TCR_BIT_HOLD)); \
243	}
244
245	/* Change DRD initiator number */
246	#define SDMA_INIT_CHANGE(task, oldInitiator, newInitiator) { \
247	int i; \
248	for (i=0; i<task->NumDRD; i++) { \
249	if (SDMA_INIT_READ(task->DRD[i]) == (uint32)oldInitiator) { \
250	SDMA_INIT_WRITE(task->DRD[i],newInitiator); \
251	} \
252	} \
253	}
254
255	/* Set the Initiator Priority */
256	#define SDMA_SET_INITIATOR_PRIORITY(sdma, initiator, priority) \
257	(((uint8 )&sdma->IPR0)+initiator) = priority;
258
259
260	/* Read DRD initiator number */
261	#define SDMA_INIT_READ(PtrDRD) \
262	((((uint32 )PtrDRD)>>SDMA_DRD_BIT_INIT) & (uint32)0x1F)
263
264	/* Write DRD initiator number */
265	#define SDMA_INIT_WRITE(PtrDRD, Initiator) { \
266	(uint32 )PtrDRD = (((uint32 )PtrDRD) & 0xFC1FFFFF) \| \
267	(Initiator<<SDMA_DRD_BIT_INIT); \
268	}
269
270	/* Change DRD initiator number */
271	#define SDMA_INIT_CHANGE(task, oldInitiator, newInitiator) { \
272	int i; \
273	for (i=0; i<task->NumDRD; i++) { \
274	if (SDMA_INIT_READ(task->DRD[i]) == (uint32)oldInitiator) { \
275	SDMA_INIT_WRITE(task->DRD[i],newInitiator); \
276	} \
277	} \
278	}
279
280	#endif /* __TASK_API_BESTCOMM_CNTRL_H */

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