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README @ ca680bc5

4.104.114.84.95

Last change on this file since ca680bc5 was ca680bc5, checked in by Ralf Corsepius <ralf.corsepius@…>, on 12/31/05 at 05:09:26
New (CVS import Thomas Doerfler <Thomas.Doerfler@…>'s submission).
Property mode set to `100644`
File size: 1.4 KB

Line
1	#
2	# README,v 1.1 2001/10/22 14:45:58 joel Exp
3	#
4
5	BSP NAME: gen5200
6	BOARD: various boards based on MPC5200 Controller:
7	MicroSys PM520 with Carrier board CR825
8	BUS: N/A
9	CPU FAMILY: ppc
10	CPU: PowerPC MPC5200
11	COPROCESSORS: Hardware FPU
12	MODE: 32 bit mode, I and D cache enabled
13	DEBUG MONITOR: None
14
15	PERIPHERALS
16	===========
17	TIMERS: GPT
18	SERIAL PORTS: 3 PSCs
19	2 CAN IFs
20	1 I2C IF
21	REAL-TIME CLOCK: PCF8563
22	DMA: for Ethernet and CompactFlash
23	VIDEO: none
24	SCSI: none
25	IDE: 1 CompactFlash Slot supported
26	NETWORKING: 1 FEC Fast Ethernet
27
28	DRIVER INFORMATION
29	==================
30	CLOCK DRIVER: using one GPT
31	IOSUPP DRIVER: none
32	SHMSUPP: none
33	TIMER DRIVER: Timebase register (lower 32 bits only)
34
35	STDIO
36	=====
37	PORT: PSC1
38	ELECTRICAL: RS-232
39	BAUD: 9600
40	BITS PER CHARACTER: 8
41	PARITY: None
42	STOP BITS: 1
43
44	NOTES
45	=====
46	On-chip resources:
47	PSC1 /dev/console /dev/tty00
48	PSC2 /dev/tty01
49	PSC3 /dev/tty02
50
51
52	Board description
53	-----------------
54
55	Clock rate: external clock: 33MHz
56	Bus width: 32 bit Flash, 32 bit SDRAM
57	FLASH: 8MByte
58	RAM: 64MByte SDRAM
59
60
61	Debugging/ Code loading:
62	------------------------
63
64	Tested using the Lauterbach TRACE32 ICD debugger.
65

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