source: rtems/c/src/lib/libbsp/powerpc/eth_comm/vectors/vectors.h @ 4055e6f8

4.104.114.84.95
Last change on this file since 4055e6f8 was 4055e6f8, checked in by Joel Sherrill <joel.sherrill@…>, on Apr 16, 2001 at 8:18:03 PM

2001-04-11 Eric Valette <valette@…>

  • clock/.cvsignore, clock/Makefile.am, clock/p_clock.c, include/8xx_immap.h, include/commproc.h, irq/.cvsignore, irq/Makefile.am, irq/irq.c, irq/irq.h, irq/irq_asm.S, irq/irq_init.c, vectors/.cvsignore, vectors/Makefile.am, vectors/vectors.S, vectors/vectors.h, vectors/vectors_init.c: New file.
  • Switch the eth_comm BSP to use the "new exception processing model."
  • Property mode set to 100644
File size: 3.6 KB
Line 
1/*
2 * vectors.h Exception frame related contant and API.
3 *
4 *  This include file describe the data structure and the functions implemented
5 *  by rtems to handle exceptions.
6 *
7 *  CopyRight (C) 1999 valette@crf.canon.fr
8 *
9 *  The license and distribution terms for this file may be
10 *  found in found in the file LICENSE in this distribution or at
11 *  http://www.OARcorp.com/rtems/license.html.
12 *
13 *  $Id$
14 */
15#ifndef LIBBSP_POWERPC_ETH_COMM_VECTORS_H
16#define LIBBSP_POWERPC_Eth_Comm_VECTORS_H
17
18/*
19 * The callee (high level exception code written in C)
20 * will store the Link Registers (return address) at entry r1 + 4 !!!.
21 * So let room for it!!!.
22 */ 
23#define LINK_REGISTER_CALLEE_UPDATE_ROOM 4
24#define SRR0_FRAME_OFFSET 8
25#define SRR1_FRAME_OFFSET 12
26#define EXCEPTION_NUMBER_OFFSET 16
27#define GPR0_OFFSET 20
28#define GPR1_OFFSET 24
29#define GPR2_OFFSET 28
30#define GPR3_OFFSET 32
31#define GPR4_OFFSET 36
32#define GPR5_OFFSET 40
33#define GPR6_OFFSET 44
34#define GPR7_OFFSET 48
35#define GPR8_OFFSET 52
36#define GPR9_OFFSET 56
37#define GPR10_OFFSET 60
38#define GPR11_OFFSET 64
39#define GPR12_OFFSET 68
40#define GPR13_OFFSET 72
41#define GPR14_OFFSET 76
42#define GPR15_OFFSET 80
43#define GPR16_OFFSET 84
44#define GPR17_OFFSET 88
45#define GPR18_OFFSET 92
46#define GPR19_OFFSET 96
47#define GPR20_OFFSET 100
48#define GPR21_OFFSET 104
49#define GPR22_OFFSET 108
50#define GPR23_OFFSET 112
51#define GPR24_OFFSET 116
52#define GPR25_OFFSET 120
53#define GPR26_OFFSET 124
54#define GPR27_OFFSET 128
55#define GPR28_OFFSET 132
56#define GPR29_OFFSET 136
57#define GPR30_OFFSET 140
58#define GPR31_OFFSET 144
59#define EXC_CR_OFFSET 148
60#define EXC_CTR_OFFSET 152
61#define EXC_XER_OFFSET 156
62#define EXC_LR_OFFSET 160
63#define EXC_DAR_OFFSET 164
64/*
65 * maintain the EABI requested 8 bytes aligment
66 * As SVR4 ABI requires 16, make it 16 (as some
67 * exception may need more registers to be processed...)
68 */
69#define    EXCEPTION_FRAME_END 176
70
71#ifndef ASM
72/*
73 * default raw exception handlers
74 */
75
76extern  void default_exception_vector_code_prolog();
77extern  int  default_exception_vector_code_prolog_size;
78
79/* codemove is like memmove, but it also gets the cache line size
80 * as 4th parameter to synchronize them. If this last parameter is
81 * zero, it performs more or less like memmove. No copy is performed if
82 * source and destination addresses are equal. However the caches
83 * are synchronized. Note that the size is always rounded up to the
84 * next mutiple of 4.
85 */
86extern void * codemove(void *, const void *, unsigned int, unsigned long);
87extern void initialize_exceptions();
88
89typedef struct {
90  unsigned      EXC_SRR0;
91  unsigned      EXC_SRR1;
92  unsigned      _EXC_number;
93  unsigned      GPR0;
94  unsigned      GPR1;
95  unsigned      GPR2;
96  unsigned      GPR3;
97  unsigned      GPR4;
98  unsigned      GPR5;
99  unsigned      GPR6;
100  unsigned      GPR7;
101  unsigned      GPR8;
102  unsigned      GPR9;
103  unsigned      GPR10;
104  unsigned      GPR11;
105  unsigned      GPR12;
106  unsigned      GPR13;
107  unsigned      GPR14;
108  unsigned      GPR15;
109  unsigned      GPR16;
110  unsigned      GPR17;
111  unsigned      GPR18;
112  unsigned      GPR19;
113  unsigned      GPR20;
114  unsigned      GPR21;
115  unsigned      GPR22;
116  unsigned      GPR23;
117  unsigned      GPR24;
118  unsigned      GPR25;
119  unsigned      GPR26;
120  unsigned      GPR27;
121  unsigned      GPR28;
122  unsigned      GPR29;
123  unsigned      GPR30;
124  unsigned      GPR31;
125  unsigned      EXC_CR;
126  unsigned      EXC_CTR;
127  unsigned      EXC_XER;
128  unsigned      EXC_LR;
129  unsigned      EXC_MSR;
130  unsigned      EXC_DAR;
131}BSP_Exception_frame;
132
133
134typedef void (*exception_handler_t) (BSP_Exception_frame* excPtr);
135extern exception_handler_t globalExceptHdl;
136/*
137 * Compatibility with pc386
138 */
139typedef BSP_Exception_frame CPU_Exception_frame;
140typedef exception_handler_t cpuExcHandlerType;
141
142#endif /* ASM */
143
144#endif /* LIBBSP_POWERPC_MCP750_VECTORS_H */
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