1 | /* |
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2 | * mmutlbtab.c |
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3 | * |
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4 | * This file defines the MMU_TLB_table for the eth_comm board. |
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5 | * |
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6 | * The license and distribution terms for this file may be |
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7 | * found in the file LICENSE in this distribution or at |
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8 | * http://www.rtems.com/license/LICENSE. |
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9 | */ |
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10 | |
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11 | #include <bsp.h> |
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12 | #include <mpc8xx/mmu.h> |
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13 | |
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14 | /* |
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15 | * This MMU_TLB_table is used to statically initialize the Table Lookaside |
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16 | * Buffers in the MMU of the MPC860 processor. |
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17 | * |
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18 | * We initialize the entries in both the instruction and data TLBs |
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19 | * with the same values - a few bits relevant to the data TLB are unused |
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20 | * in the instruction TLB. |
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21 | * |
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22 | * An Effective Page Number (EPN), Tablewalk Control Register (TWC) and |
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23 | * Real Page Number (RPN) value are supplied in the table for each TLB entry. |
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24 | * |
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25 | * The instruction and data TLBs each can hold 32 entries, so _TLB_Table must |
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26 | * not have more than 32 lines in it! |
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27 | * |
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28 | * We set up the virtual memory map so that virtual address of a |
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29 | * location is equal to its real address. |
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30 | */ |
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31 | MMU_TLB_table_t MMU_TLB_table[] = { |
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32 | /* |
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33 | * DRAM: CS1, Start address 0x00000000, 8M, |
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34 | * ASID=0x0, APG=0x0, not guarded memory, copyback data cache policy, |
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35 | * R/W,X for supervisor, no ASID comparison, not cache-inhibited. |
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36 | * EPN TWC RPN |
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37 | */ |
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38 | { 0x00000200, 0x0D, 0x000001FD } /* DRAM - PS=PS=8M */ |
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39 | }; |
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40 | |
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41 | /* |
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42 | * MMU_N_TLB_Table_Entries is defined here because the size of the |
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43 | * MMU_TLB_table is only known in this file. |
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44 | */ |
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45 | int MMU_N_TLB_Table_Entries = ( sizeof(MMU_TLB_table) / sizeof(MMU_TLB_table[0]) ); |
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