source: rtems/c/src/lib/libbsp/powerpc/eth_comm/startup/mmutlbtab.c @ 6128a4a

4.104.114.84.95
Last change on this file since 6128a4a was 6128a4a, checked in by Ralf Corsepius <ralf.corsepius@…>, on 04/21/04 at 10:43:04

Remove stray white spaces.

  • Property mode set to 100644
File size: 1.5 KB
Line 
1/*
2 * mmutlbtab.c
3 *
4 * This file defines the MMU_TLB_table for the eth_comm board.
5 *
6 * The license and distribution terms for this file may be
7 * found in the file LICENSE in this distribution or at
8 * http://www.rtems.com/license/LICENSE.
9 */
10
11#include <bsp.h>
12#include <mpc8xx/mmu.h>
13
14/*
15 * This MMU_TLB_table is used to statically initialize the Table Lookaside
16 * Buffers in the MMU of the MPC860 processor.
17 *
18 * We initialize the entries in both the instruction and data TLBs
19 * with the same values - a few bits relevant to the data TLB are unused
20 * in the instruction TLB.
21 *
22 * An Effective Page Number (EPN), Tablewalk Control Register (TWC) and
23 * Real Page Number (RPN) value are supplied in the table for each TLB entry.
24 *
25 * The instruction and data TLBs each can hold 32 entries, so _TLB_Table must
26 * not have more than 32 lines in it!
27 *
28 * We set up the virtual memory map so that virtual address of a
29 * location is equal to its real address.
30 */
31MMU_TLB_table_t MMU_TLB_table[] = {
32        /*
33         * DRAM: CS1, Start address 0x00000000, 8M,
34         *      ASID=0x0, APG=0x0, not guarded memory, copyback data cache policy,
35         *      R/W,X for supervisor, no ASID comparison, not cache-inhibited.
36         * EPN          TWC     RPN
37         */
38        { 0x00000200,   0x0D,   0x000001FD }    /* DRAM - PS=PS=8M */
39};
40
41/*
42 * MMU_N_TLB_Table_Entries is defined here because the size of the
43 * MMU_TLB_table is only known in this file.
44 */
45int MMU_N_TLB_Table_Entries = ( sizeof(MMU_TLB_table) / sizeof(MMU_TLB_table[0]) );
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