source: rtems/c/src/lib/libbsp/powerpc/eth_comm/startup/mmu.c @ ee733965

4.104.114.84.95
Last change on this file since ee733965 was ee733965, checked in by Joel Sherrill <joel.sherrill@…>, on Feb 17, 1999 at 8:24:53 PM

Jay Monkman <jmonkman@…> submitted the eth_comm BSP for a PPC860
based board.

  • Property mode set to 100644
File size: 4.8 KB
Line 
1/*
2 *  mmu.c - this file contains functions for initializing the MMU
3 *
4 *  Written by Jay Monkman (jmonkman@frasca.com)
5 */
6
7#include <bsp.h>
8#include <mpc860.h>
9
10/* Macros for handling all the MMU SPRs */
11#define PUT_MI_CTR(r)   __asm__ volatile ("mtspr 0x310,%0\n" ::"r"(r))
12#define GET_MI_CTR(r)   __asm__ volatile ("mfspr %0,0x310\n" :"=r"(r))
13#define PUT_MD_CTR(r)   __asm__ volatile ("mtspr 0x318,%0\n" ::"r"(r))
14#define GET_MD_CTR(r)   __asm__ volatile ("mfspr %0,0x318\n" :"=r"(r))
15#define PUT_M_CASID(r)  __asm__ volatile ("mtspr 0x319,%0\n" ::"r"(r))
16#define GET_M_CASID(r)  __asm__ volatile ("mfspr %0,0x319\n" :"=r"(r))
17#define PUT_MI_EPN(r)   __asm__ volatile ("mtspr 0x313,%0\n" ::"r"(r))
18#define GET_MI_EPN(r)   __asm__ volatile ("mfspr %0,0x313\n" :"=r"(r))
19#define PUT_MI_TWC(r)   __asm__ volatile ("mtspr 0x315,%0\n" ::"r"(r))
20#define GET_MI_TWC(r)   __asm__ volatile ("mfspr %0,0x315\n" :"=r"(r))
21#define PUT_MI_RPN(r)   __asm__ volatile ("mtspr 0x316,%0\n" ::"r"(r))
22#define GET_MI_RPN(r)   __asm__ volatile ("mfspr %0,0x316\n" :"=r"(r))
23#define PUT_MD_EPN(r)   __asm__ volatile ("mtspr 0x313,%0\n" ::"r"(r))
24#define GET_MD_EPN(r)   __asm__ volatile ("mfspr %0,0x313\n" :"=r"(r))
25#define PUT_M_TWB(r)    __asm__ volatile ("mtspr 0x31c,%0\n" ::"r"(r))
26#define GET_M_TWB(r)    __asm__ volatile ("mfspr %0,0x31c\n" :"=r"(r))
27#define PUT_MD_TWC(r)   __asm__ volatile ("mtspr 0x31d,%0\n" ::"r"(r))
28#define GET_MD_TWC(r)   __asm__ volatile ("mfspr %0,0x31d\n" :"=r"(r))
29#define PUT_MD_RPN(r)   __asm__ volatile ("mtspr 0x31e,%0\n" ::"r"(r))
30#define GET_MD_RPN(r)   __asm__ volatile ("mfspr %0,0x31e\n" :"=r"(r))
31#define PUT_MI_AP(r)    __asm__ volatile ("mtspr 0x312,%0\n" ::"r"(r))
32#define GET_MI_AP(r)    __asm__ volatile ("mfspr %0,0x312\n" :"=r"(r))
33#define PUT_MD_AP(r)    __asm__ volatile ("mtspr 0x31a,%0\n" ::"r"(r))
34#define GET_MD_AP(r)    __asm__ volatile ("mfspr %0,0x31a\n" :"=r"(r))
35#define PUT_M_TW(r)     __asm__ volatile ("mtspr 0x31f,%0\n" ::"r"(r))
36#define GET_M_TW(r)     __asm__ volatile ("mfspr %0,0x31f\n" :"=r"(r))
37#define PUT_MI_DCAM(r)  __asm__ volatile ("mtspr 0x330,%0\n" ::"r"(r))
38#define GET_MI_DCAM(r)  __asm__ volatile ("mfspr %0,0x330\n" :"=r"(r))
39#define PUT_MI_DRAM0(r) __asm__ volatile ("mtspr 0x331,%0\n" ::"r"(r))
40#define GET_MI_DRAM0(r) __asm__ volatile ("mfspr %0,0x331\n" :"=r"(r))
41#define PUT_MI_DRAM1(r) __asm__ volatile ("mtspr 0x332,%0\n" ::"r"(r))
42#define GET_MI_DRAM1(r) __asm__ volatile ("mfspr %0,0x332\n" :"=r"(r))
43#define PUT_MD_DCAM(r)  __asm__ volatile ("mtspr 0x338,%0\n" ::"r"(r))
44#define GET_MD_DCAM(r)  __asm__ volatile ("mfspr %0,0x338\n" :"=r"(r))
45#define PUT_MD_DRAM0(r) __asm__ volatile ("mtspr 0x339,%0\n" ::"r"(r))
46#define GET_MD_DRAM0(r) __asm__ volatile ("mfspr %0,0x339\n" :"=r"(r))
47#define PUT_MD_DRAM1(r) __asm__ volatile ("mtspr 0x33a,%0\n" ::"r"(r))
48#define GET_MD_DRAM1(r) __asm__ volatile ("mfspr %0,0x33a\n" :"=r"(r))
49#define PUT_IC_CST(r)   __asm__ volatile ("mtspr 0x230,%0\n" ::"r"(r))
50#define GET_IC_CST(r)   __asm__ volatile ("mfspr %0,0x230\n" :"=r"(r))
51#define PUT_DC_CST(r)   __asm__ volatile ("mtspr 0x238,%0\n" ::"r"(r))
52#define GET_DC_CST(r)   __asm__ volatile ("mfspr %0,0x238\n" :"=r"(r))
53#define PUT_IC_ADR(r)   __asm__ volatile ("mtspr 0x231,%0\n" ::"r"(r))
54#define GET_IC_ADR(r)   __asm__ volatile ("mfspr %0,0x231\n" :"=r"(r))
55#define PUT_IC_DAT(r)   __asm__ volatile ("mtspr 0x232,%0\n" ::"r"(r))
56#define GET_IC_DAT(r)   __asm__ volatile ("mfspr %0,0x232\n" :"=r"(r))
57
58extern rtems_configuration_table BSP_Configuration;
59
60void mmu_init(void)
61{
62  register unsigned long t1, t2;
63
64  /* Let's clear MSR[IR] and MSR[DR] */ 
65  t2 = PPC_MSR_IR | PPC_MSR_DR;
66  __asm__ volatile (
67    "mfmsr    %0\n"
68    "andc     %0, %0, %1\n"
69    "mtmsr    %0\n" :"=r"(t1), "=r"(t2):
70    "1"(t2));
71
72  /* Invalidate the TLBs */
73  __asm__ volatile ("tlbia\n"::);
74  __asm__ volatile ("isync\n"::);
75
76  /* make sure no TLB entries are reserved */
77  t1 = 0;
78  PUT_MI_CTR(t1);
79
80  t1 = M860_MD_CTR_TWAM;   /* 4K pages */
81  /*  PUT_MD_CTR(t1); */
82
83  t1 = M860_MI_EPN_VALID;    /* make entry valid */
84  /*  PUT_MD_EPN(t1); */
85  PUT_MI_EPN(t1);
86
87  t1 = M860_MI_TWC_PS8 | M860_MI_TWC_VALID;   /* 8 MB pages, valid */
88  /*  PUT_MD_TWC(t1); */
89  PUT_MI_TWC(t1);
90
91  t1 = M860_MD_RPN_CHANGE | M860_MD_RPN_F | M860_MD_RPN_16K | 
92       M860_MD_RPN_SHARED | M860_MD_RPN_VALID;
93  /*  PUT_MD_RPN(t1); */
94  PUT_MI_RPN(t1);
95
96  t1 = M860_MI_AP_Kp << 30; 
97  PUT_MI_AP(t1);
98  /*  PUT_MD_AP(t1); */
99 
100  t1 = M860_CACHE_CMD_UNLOCK;
101  /*  PUT_DC_CST(t1); */
102  PUT_IC_CST(t1);
103
104  t1 = M860_CACHE_CMD_INVALIDATE;
105  /*  PUT_DC_CST(t1); */
106  PUT_IC_CST(t1);
107
108  t1 = M860_CACHE_CMD_ENABLE;
109  PUT_IC_CST(t1);
110
111  t1 = M860_CACHE_CMD_SFWT;
112  /*  PUT_DC_CST(t1); */
113  t1 = M860_CACHE_CMD_ENABLE;
114  /*  PUT_DC_CST(t1);*/
115
116
117
118  /* Let's set MSR[IR]  */ 
119  t2 = PPC_MSR_IR;
120  __asm__ volatile (
121    "mfmsr    %0\n"
122    "or       %0, %0, %1\n"
123    "mtmsr    %0\n" :"=r"(t1), "=r"(t2):
124    "1"(t2));
125
126}
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