[ee733965] | 1 | /* |
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| 2 | * mmu.c - this file contains functions for initializing the MMU |
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| 3 | * |
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| 4 | * Written by Jay Monkman (jmonkman@frasca.com) |
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| 5 | */ |
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| 6 | |
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| 7 | #include <bsp.h> |
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| 8 | #include <mpc860.h> |
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| 9 | |
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| 10 | /* Macros for handling all the MMU SPRs */ |
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| 11 | #define PUT_MI_CTR(r) __asm__ volatile ("mtspr 0x310,%0\n" ::"r"(r)) |
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| 12 | #define GET_MI_CTR(r) __asm__ volatile ("mfspr %0,0x310\n" :"=r"(r)) |
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| 13 | #define PUT_MD_CTR(r) __asm__ volatile ("mtspr 0x318,%0\n" ::"r"(r)) |
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| 14 | #define GET_MD_CTR(r) __asm__ volatile ("mfspr %0,0x318\n" :"=r"(r)) |
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| 15 | #define PUT_M_CASID(r) __asm__ volatile ("mtspr 0x319,%0\n" ::"r"(r)) |
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| 16 | #define GET_M_CASID(r) __asm__ volatile ("mfspr %0,0x319\n" :"=r"(r)) |
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| 17 | #define PUT_MI_EPN(r) __asm__ volatile ("mtspr 0x313,%0\n" ::"r"(r)) |
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| 18 | #define GET_MI_EPN(r) __asm__ volatile ("mfspr %0,0x313\n" :"=r"(r)) |
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| 19 | #define PUT_MI_TWC(r) __asm__ volatile ("mtspr 0x315,%0\n" ::"r"(r)) |
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| 20 | #define GET_MI_TWC(r) __asm__ volatile ("mfspr %0,0x315\n" :"=r"(r)) |
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| 21 | #define PUT_MI_RPN(r) __asm__ volatile ("mtspr 0x316,%0\n" ::"r"(r)) |
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| 22 | #define GET_MI_RPN(r) __asm__ volatile ("mfspr %0,0x316\n" :"=r"(r)) |
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| 23 | #define PUT_MD_EPN(r) __asm__ volatile ("mtspr 0x313,%0\n" ::"r"(r)) |
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| 24 | #define GET_MD_EPN(r) __asm__ volatile ("mfspr %0,0x313\n" :"=r"(r)) |
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| 25 | #define PUT_M_TWB(r) __asm__ volatile ("mtspr 0x31c,%0\n" ::"r"(r)) |
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| 26 | #define GET_M_TWB(r) __asm__ volatile ("mfspr %0,0x31c\n" :"=r"(r)) |
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| 27 | #define PUT_MD_TWC(r) __asm__ volatile ("mtspr 0x31d,%0\n" ::"r"(r)) |
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| 28 | #define GET_MD_TWC(r) __asm__ volatile ("mfspr %0,0x31d\n" :"=r"(r)) |
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| 29 | #define PUT_MD_RPN(r) __asm__ volatile ("mtspr 0x31e,%0\n" ::"r"(r)) |
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| 30 | #define GET_MD_RPN(r) __asm__ volatile ("mfspr %0,0x31e\n" :"=r"(r)) |
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| 31 | #define PUT_MI_AP(r) __asm__ volatile ("mtspr 0x312,%0\n" ::"r"(r)) |
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| 32 | #define GET_MI_AP(r) __asm__ volatile ("mfspr %0,0x312\n" :"=r"(r)) |
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| 33 | #define PUT_MD_AP(r) __asm__ volatile ("mtspr 0x31a,%0\n" ::"r"(r)) |
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| 34 | #define GET_MD_AP(r) __asm__ volatile ("mfspr %0,0x31a\n" :"=r"(r)) |
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| 35 | #define PUT_M_TW(r) __asm__ volatile ("mtspr 0x31f,%0\n" ::"r"(r)) |
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| 36 | #define GET_M_TW(r) __asm__ volatile ("mfspr %0,0x31f\n" :"=r"(r)) |
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| 37 | #define PUT_MI_DCAM(r) __asm__ volatile ("mtspr 0x330,%0\n" ::"r"(r)) |
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| 38 | #define GET_MI_DCAM(r) __asm__ volatile ("mfspr %0,0x330\n" :"=r"(r)) |
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| 39 | #define PUT_MI_DRAM0(r) __asm__ volatile ("mtspr 0x331,%0\n" ::"r"(r)) |
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| 40 | #define GET_MI_DRAM0(r) __asm__ volatile ("mfspr %0,0x331\n" :"=r"(r)) |
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| 41 | #define PUT_MI_DRAM1(r) __asm__ volatile ("mtspr 0x332,%0\n" ::"r"(r)) |
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| 42 | #define GET_MI_DRAM1(r) __asm__ volatile ("mfspr %0,0x332\n" :"=r"(r)) |
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| 43 | #define PUT_MD_DCAM(r) __asm__ volatile ("mtspr 0x338,%0\n" ::"r"(r)) |
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| 44 | #define GET_MD_DCAM(r) __asm__ volatile ("mfspr %0,0x338\n" :"=r"(r)) |
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| 45 | #define PUT_MD_DRAM0(r) __asm__ volatile ("mtspr 0x339,%0\n" ::"r"(r)) |
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| 46 | #define GET_MD_DRAM0(r) __asm__ volatile ("mfspr %0,0x339\n" :"=r"(r)) |
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| 47 | #define PUT_MD_DRAM1(r) __asm__ volatile ("mtspr 0x33a,%0\n" ::"r"(r)) |
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| 48 | #define GET_MD_DRAM1(r) __asm__ volatile ("mfspr %0,0x33a\n" :"=r"(r)) |
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| 49 | #define PUT_IC_CST(r) __asm__ volatile ("mtspr 0x230,%0\n" ::"r"(r)) |
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| 50 | #define GET_IC_CST(r) __asm__ volatile ("mfspr %0,0x230\n" :"=r"(r)) |
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| 51 | #define PUT_DC_CST(r) __asm__ volatile ("mtspr 0x238,%0\n" ::"r"(r)) |
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| 52 | #define GET_DC_CST(r) __asm__ volatile ("mfspr %0,0x238\n" :"=r"(r)) |
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| 53 | #define PUT_IC_ADR(r) __asm__ volatile ("mtspr 0x231,%0\n" ::"r"(r)) |
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| 54 | #define GET_IC_ADR(r) __asm__ volatile ("mfspr %0,0x231\n" :"=r"(r)) |
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| 55 | #define PUT_IC_DAT(r) __asm__ volatile ("mtspr 0x232,%0\n" ::"r"(r)) |
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| 56 | #define GET_IC_DAT(r) __asm__ volatile ("mfspr %0,0x232\n" :"=r"(r)) |
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| 57 | |
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| 58 | extern rtems_configuration_table BSP_Configuration; |
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| 59 | |
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| 60 | void mmu_init(void) |
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| 61 | { |
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| 62 | register unsigned long t1, t2; |
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| 63 | |
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| 64 | /* Let's clear MSR[IR] and MSR[DR] */ |
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| 65 | t2 = PPC_MSR_IR | PPC_MSR_DR; |
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| 66 | __asm__ volatile ( |
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| 67 | "mfmsr %0\n" |
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| 68 | "andc %0, %0, %1\n" |
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| 69 | "mtmsr %0\n" :"=r"(t1), "=r"(t2): |
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| 70 | "1"(t2)); |
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| 71 | |
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| 72 | /* Invalidate the TLBs */ |
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| 73 | __asm__ volatile ("tlbia\n"::); |
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| 74 | __asm__ volatile ("isync\n"::); |
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| 75 | |
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| 76 | /* make sure no TLB entries are reserved */ |
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| 77 | t1 = 0; |
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| 78 | PUT_MI_CTR(t1); |
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| 79 | |
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| 80 | t1 = M860_MD_CTR_TWAM; /* 4K pages */ |
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| 81 | /* PUT_MD_CTR(t1); */ |
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| 82 | |
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| 83 | t1 = M860_MI_EPN_VALID; /* make entry valid */ |
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| 84 | /* PUT_MD_EPN(t1); */ |
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| 85 | PUT_MI_EPN(t1); |
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| 86 | |
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| 87 | t1 = M860_MI_TWC_PS8 | M860_MI_TWC_VALID; /* 8 MB pages, valid */ |
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| 88 | /* PUT_MD_TWC(t1); */ |
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| 89 | PUT_MI_TWC(t1); |
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| 90 | |
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| 91 | t1 = M860_MD_RPN_CHANGE | M860_MD_RPN_F | M860_MD_RPN_16K | |
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| 92 | M860_MD_RPN_SHARED | M860_MD_RPN_VALID; |
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| 93 | /* PUT_MD_RPN(t1); */ |
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| 94 | PUT_MI_RPN(t1); |
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| 95 | |
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| 96 | t1 = M860_MI_AP_Kp << 30; |
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| 97 | PUT_MI_AP(t1); |
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| 98 | /* PUT_MD_AP(t1); */ |
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| 99 | |
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| 100 | t1 = M860_CACHE_CMD_UNLOCK; |
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| 101 | /* PUT_DC_CST(t1); */ |
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| 102 | PUT_IC_CST(t1); |
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| 103 | |
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| 104 | t1 = M860_CACHE_CMD_INVALIDATE; |
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| 105 | /* PUT_DC_CST(t1); */ |
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| 106 | PUT_IC_CST(t1); |
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| 107 | |
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| 108 | t1 = M860_CACHE_CMD_ENABLE; |
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| 109 | PUT_IC_CST(t1); |
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| 110 | |
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| 111 | t1 = M860_CACHE_CMD_SFWT; |
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| 112 | /* PUT_DC_CST(t1); */ |
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| 113 | t1 = M860_CACHE_CMD_ENABLE; |
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| 114 | /* PUT_DC_CST(t1);*/ |
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| 115 | |
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| 116 | |
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| 117 | |
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| 118 | /* Let's set MSR[IR] */ |
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| 119 | t2 = PPC_MSR_IR; |
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| 120 | __asm__ volatile ( |
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| 121 | "mfmsr %0\n" |
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| 122 | "or %0, %0, %1\n" |
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| 123 | "mtmsr %0\n" :"=r"(t1), "=r"(t2): |
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| 124 | "1"(t2)); |
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| 125 | |
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| 126 | } |
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