4.104.114.84.95
Last change
on this file since 8ef3818 was
8ef3818,
checked in by Joel Sherrill <joel.sherrill@…>, on 06/12/00 at 19:57:02
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Patch from John Cotton <john.cotton@…>, Charles-Antoine Gauthier
<charles.gauthier@…>, and Darlene A. Stewart
<Darlene.Stewart@…> to add support for a number of very
significant things:
+ BSPs for many variations on the Motorola MBX8xx board series
+ Cache Manager including initial support for m68040
and PowerPC
+ Rework of mpc8xx libcpu code so all mpc8xx CPUs now use
same code base.
+ Rework of eth_comm BSP to utiltize above.
John reports this works on the 821 and 860
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-
Property mode set to
100644
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File size:
1.0 KB
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1 | /* |
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2 | * cpuinit.c - this file contains functions for initializing the CPU |
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3 | * |
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4 | * Written by Jay Monkman (jmonkman@frasca.com) |
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5 | * |
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6 | * $Id$ |
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7 | */ |
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8 | |
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9 | #include <bsp.h> |
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10 | |
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11 | /* Macros for handling all the MMU SPRs */ |
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12 | #define PUT_IC_CST(r) __asm__ volatile ("mtspr 0x230,%0\n" ::"r"(r)) |
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13 | #define GET_IC_CST(r) __asm__ volatile ("mfspr %0,0x230\n" :"=r"(r)) |
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14 | #define PUT_DC_CST(r) __asm__ volatile ("mtspr 0x238,%0\n" ::"r"(r)) |
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15 | #define GET_DC_CST(r) __asm__ volatile ("mfspr %0,0x238\n" :"=r"(r)) |
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16 | |
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17 | void cpu_init(void) |
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18 | { |
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19 | register unsigned long t1, t2; |
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20 | |
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21 | /* Let's clear MSR[IR] and MSR[DR] */ |
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22 | t2 = PPC_MSR_IR | PPC_MSR_DR; |
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23 | __asm__ volatile ( |
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24 | "mfmsr %0\n" |
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25 | "andc %0, %0, %1\n" |
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26 | "mtmsr %0\n" :"=r"(t1), "=r"(t2): |
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27 | "1"(t2)); |
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28 | |
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29 | t1 = M8xx_CACHE_CMD_UNLOCK; |
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30 | /* PUT_DC_CST(t1); */ |
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31 | PUT_IC_CST(t1); |
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32 | |
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33 | t1 = M8xx_CACHE_CMD_INVALIDATE; |
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34 | /* PUT_DC_CST(t1); */ |
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35 | PUT_IC_CST(t1); |
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36 | |
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37 | t1 = M8xx_CACHE_CMD_ENABLE; |
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38 | PUT_IC_CST(t1); |
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39 | |
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40 | t1 = M8xx_CACHE_CMD_SFWT; |
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41 | /* PUT_DC_CST(t1); */ |
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42 | t1 = M8xx_CACHE_CMD_ENABLE; |
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43 | /* PUT_DC_CST(t1);*/ |
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44 | } |
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