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irq_asm.S @ f4e789b5

4.104.114.84.95

Last change on this file since f4e789b5 was f4e789b5, checked in by Joel Sherrill <joel.sherrill@…>, on 09/04/03 at 18:52:21

2003-09-04 Joel Sherrill <joel@…>

canbus/canbus.c, clock/p_clock.c, include/bsp.h, include/canbus.h, include/coverhd.h, irq/irq.c, irq/irq.h, irq/irq_asm.S, irq/irq_init.c, startup/bspstart.c, startup/mmutlbtab.c, startup/setvec.c, vectors/vectors.h, vectors/vectors_init.c: URL for license changed.

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File size: 8.3 KB

Line
1	/*
2	* This file contains the assembly code for the PowerPC
3	* IRQ veneers for RTEMS.
4	*
5	* The license and distribution terms for this file may be
6	* found in found in the file LICENSE in this distribution or at
7	* http://www.rtems.com/license/LICENSE.
8	*
9	* Modified to support the MCP750.
10	* Modifications Copyright (C) 1999 Eric Valette. valette@crf.canon.fr
11	*
12	* Till Straumann <strauman@slac.stanford.edu>, 2003/7:
13	* - store isr nesting level in _ISR_Nest_level rather than
14	* SPRG0 - RTEMS relies on that variable.
15	*
16	* $Id$
17	*/
18
19	#include <asm.h>
20	#include <rtems/score/cpu.h>
21	#include <bsp/vectors.h>
22	#include <libcpu/raw_exception.h>
23
24
25	#define SYNC \
26	sync; \
27	isync
28
29	.text
30	.p2align 5
31
32	PUBLIC_VAR(decrementer_exception_vector_prolog_code)
33
34	SYM (decrementer_exception_vector_prolog_code):
35	/*
36	* let room for exception frame
37	*/
38	stwu r1, - (EXCEPTION_FRAME_END)(r1)
39	stw r4, GPR4_OFFSET(r1)
40	li r4, ASM_DEC_VECTOR
41	ba shared_raw_irq_code_entry
42
43	PUBLIC_VAR (decrementer_exception_vector_prolog_code_size)
44
45	decrementer_exception_vector_prolog_code_size = . - decrementer_exception_vector_prolog_code
46
47	PUBLIC_VAR(external_exception_vector_prolog_code)
48
49	SYM (external_exception_vector_prolog_code):
50	/*
51	* let room for exception frame
52	*/
53	stwu r1, - (EXCEPTION_FRAME_END)(r1)
54	stw r4, GPR4_OFFSET(r1)
55	li r4, ASM_EXT_VECTOR
56	ba shared_raw_irq_code_entry
57
58	PUBLIC_VAR (external_exception_vector_prolog_code_size)
59
60	external_exception_vector_prolog_code_size = . - external_exception_vector_prolog_code
61
62	PUBLIC_VAR(shared_raw_irq_code_entry)
63	PUBLIC_VAR(C_dispatch_irq_handler)
64
65	.p2align 5
66	SYM (shared_raw_irq_code_entry):
67	/*
68	* Entry conditions :
69	* Registers already saved : R1, R4
70	* R1 : points to a location with enough room for the
71	* interrupt frame
72	* R4 : vector number
73	*/
74	/*
75	* Save SRR0/SRR1 As soon As possible as it is the minimal needed
76	* to reenable exception processing
77	*/
78	stw r0, GPR0_OFFSET(r1)
79	stw r2, GPR2_OFFSET(r1)
80	stw r3, GPR3_OFFSET(r1)
81
82	mfsrr0 r0
83	mfsrr1 r2
84	mfmsr r3
85
86	stw r0, SRR0_FRAME_OFFSET(r1)
87	stw r2, SRR1_FRAME_OFFSET(r1)
88	/*
89	* Enable data and instruction address translation, exception recovery
90	*
91	* also, on CPUs with FP, enable FP so that FP context can be
92	* saved and restored (using FP instructions)
93	*/
94	#if (PPC_HAS_FPU == 0)
95	ori r3, r3, MSR_RI \| MSR_IR \| MSR_DR
96	#else
97	ori r3, r3, MSR_RI \| MSR_IR \| MSR_DR \| MSR_FP
98	#endif
99	mtmsr r3
100	SYNC
101	/*
102	* Push C scratch registers on the current stack. It may
103	* actually be the thread stack or the interrupt stack.
104	* Anyway we have to make it in order to be able to call C/C++
105	* functions. Depending on the nesting interrupt level, we will
106	* switch to the right stack later.
107	*/
108	stw r5, GPR5_OFFSET(r1)
109	stw r6, GPR6_OFFSET(r1)
110	stw r7, GPR7_OFFSET(r1)
111	stw r8, GPR8_OFFSET(r1)
112	stw r9, GPR9_OFFSET(r1)
113	stw r10, GPR10_OFFSET(r1)
114	stw r11, GPR11_OFFSET(r1)
115	stw r12, GPR12_OFFSET(r1)
116	stw r13, GPR13_OFFSET(r1)
117
118	mfcr r5
119	mfctr r6
120	mfxer r7
121	mflr r8
122
123	stw r5, EXC_CR_OFFSET(r1)
124	stw r6, EXC_CTR_OFFSET(r1)
125	stw r7, EXC_XER_OFFSET(r1)
126	stw r8, EXC_LR_OFFSET(r1)
127
128	/*
129	* Add some non volatile registers to store information
130	* that will be used when returning from C handler
131	*/
132	stw r14, GPR14_OFFSET(r1)
133	stw r15, GPR15_OFFSET(r1)
134	/*
135	* save current stack pointer location in R14
136	*/
137	addi r14, r1, 0
138	/*
139	* store part of _Thread_Dispatch_disable_level address in R15
140	*/
141	addis r15,0, _Thread_Dispatch_disable_level@ha
142	#if BROKEN_ISR_NEST_LEVEL
143	/*
144	* Get current nesting level in R2
145	*/
146	mfspr r2, SPRG0
147	#else
148	/*
149	* Retrieve current nesting level from _ISR_Nest_level
150	*/
151	lis r7, _ISR_Nest_level@ha
152	lwz r2, _ISR_Nest_level@l(r7)
153	#endif
154	/*
155	* Check if stack switch is necessary
156	*/
157	cmpwi r2,0
158	bne nested
159	mfspr r1, SPRG1
160
161	nested:
162	/*
163	* Start Incrementing nesting level in R2
164	*/
165	addi r2,r2,1
166	/*
167	* Start Incrementing _Thread_Dispatch_disable_level R4 = _Thread_Dispatch_disable_level
168	*/
169	lwz r6,_Thread_Dispatch_disable_level@l(r15)
170	#if BROKEN_ISR_NEST_LEVEL
171	/*
172	* Store new nesting level in SPRG0
173	*/
174	mtspr SPRG0, r2
175	#else
176	/* store new nesting level in _ISR_Nest_level */
177	stw r2, _ISR_Nest_level@l(r7)
178	#endif
179
180	addi r6, r6, 1
181	mfmsr r5
182	/*
183	* store new _Thread_Dispatch_disable_level value
184	*/
185	stw r6, _Thread_Dispatch_disable_level@l(r15)
186	/*
187	* We are now running on the interrupt stack. External and decrementer
188	* exceptions are still disabled. I see no purpose trying to optimize
189	* further assembler code.
190	*/
191	/*
192	* Call C exception handler for decrementer Interrupt frame is passed just
193	* in case...
194	*/
195	addi r3, r14, 0x8
196	bl C_dispatch_irq_handler /* C_dispatch_irq_handler(cpu_interrupt_frame* r3, vector r4) */
197	/*
198	* start decrementing nesting level. Note : do not test result against 0
199	* value as an easy exit condition because if interrupt nesting level > 1
200	* then _Thread_Dispatch_disable_level > 1
201	*/
202	#if BROKEN_ISR_NEST_LEVEL
203	mfspr r2, SPRG0
204	#else
205	lis r7, _ISR_Nest_level@ha
206	lwz r2, _ISR_Nest_level@l(r7)
207	#endif
208	/*
209	* start decrementing _Thread_Dispatch_disable_level
210	*/
211	lwz r3,_Thread_Dispatch_disable_level@l(r15)
212	addi r2, r2, -1 /* Continue decrementing nesting level */
213	addi r3, r3, -1 /* Continue decrementing _Thread_Dispatch_disable_level */
214	#if BROKEN_ISR_NEST_LEVEL
215	mtspr SPRG0, r2 /* End decrementing nesting level */
216	#else
217	stw r2, _ISR_Nest_level@l(r7) /* End decrementing nesting level */
218	#endif
219	stw r3,_Thread_Dispatch_disable_level@l(r15) /* End decrementing _Thread_Dispatch_disable_level */
220	cmpwi r3, 0
221	/*
222	* switch back to original stack (done here just optimize registers
223	* contention. Could have been done before...)
224	*/
225	addi r1, r14, 0
226	bne easy_exit /* if (_Thread_Dispatch_disable_level != 0) goto easy_exit */
227	/*
228	* Here we are running again on the thread system stack.
229	* We have interrupt nesting level = _Thread_Dispatch_disable_level = 0.
230	* Interrupt are still disabled. Time to check if scheduler request to
231	* do something with the current thread...
232	*/
233	addis r4, 0, _Context_Switch_necessary@ha
234	lwz r5, _Context_Switch_necessary@l(r4)
235	cmpwi r5, 0
236	bne switch
237
238	addis r6, 0, _ISR_Signals_to_thread_executing@ha
239	lwz r7, _ISR_Signals_to_thread_executing@l(r6)
240	cmpwi r7, 0
241	li r8, 0
242	beq easy_exit
243	stw r8, _ISR_Signals_to_thread_executing@l(r6)
244	/*
245	* going to call _ThreadProcessSignalsFromIrq
246	* Push a complete exception like frame...
247	*/
248	stmw r16, GPR16_OFFSET(r1)
249	addi r3, r1, 0x8
250	/*
251	* compute SP at exception entry
252	*/
253	addi r2, r1, EXCEPTION_FRAME_END
254	/*
255	* store it at the right place
256	*/
257	stw r2, GPR1_OFFSET(r1)
258	/*
259	* Call High Level signal handling code
260	*/
261	bl _ThreadProcessSignalsFromIrq
262	/*
263	* start restoring exception like frame
264	*/
265	lwz r31, EXC_CTR_OFFSET(r1)
266	lwz r30, EXC_XER_OFFSET(r1)
267	lwz r29, EXC_CR_OFFSET(r1)
268	lwz r28, EXC_LR_OFFSET(r1)
269
270	mtctr r31
271	mtxer r30
272	mtcr r29
273	mtlr r28
274
275	lmw r4, GPR4_OFFSET(r1)
276	lwz r2, GPR2_OFFSET(r1)
277	lwz r0, GPR0_OFFSET(r1)
278
279	/*
280	* Disable data and instruction translation. Make path non recoverable...
281	*/
282	mfmsr r3
283	xori r3, r3, MSR_RI \| MSR_IR \| MSR_DR
284	mtmsr r3
285	SYNC
286	/*
287	* Restore rfi related settings
288	*/
289
290	lwz r3, SRR1_FRAME_OFFSET(r1)
291	mtsrr1 r3
292	lwz r3, SRR0_FRAME_OFFSET(r1)
293	mtsrr0 r3
294
295	lwz r3, GPR3_OFFSET(r1)
296	addi r1,r1, EXCEPTION_FRAME_END
297	SYNC
298	rfi
299
300	switch:
301	bl SYM (_Thread_Dispatch)
302
303	easy_exit:
304	/*
305	* start restoring interrupt frame
306	*/
307	lwz r3, EXC_CTR_OFFSET(r1)
308	lwz r4, EXC_XER_OFFSET(r1)
309	lwz r5, EXC_CR_OFFSET(r1)
310	lwz r6, EXC_LR_OFFSET(r1)
311
312	mtctr r3
313	mtxer r4
314	mtcr r5
315	mtlr r6
316
317	lwz r15, GPR15_OFFSET(r1)
318	lwz r14, GPR14_OFFSET(r1)
319	lwz r13, GPR13_OFFSET(r1)
320	lwz r12, GPR12_OFFSET(r1)
321	lwz r11, GPR11_OFFSET(r1)
322	lwz r10, GPR10_OFFSET(r1)
323	lwz r9, GPR9_OFFSET(r1)
324	lwz r8, GPR8_OFFSET(r1)
325	lwz r7, GPR7_OFFSET(r1)
326	lwz r6, GPR6_OFFSET(r1)
327	lwz r5, GPR5_OFFSET(r1)
328
329	/*
330	* Disable nested exception processing, data and instruction
331	* translation.
332	*/
333	mfmsr r3
334	xori r3, r3, MSR_RI \| MSR_IR \| MSR_DR
335	mtmsr r3
336	SYNC
337	/*
338	* Restore rfi related settings
339	*/
340
341	lwz r4, SRR1_FRAME_OFFSET(r1)
342	lwz r2, SRR0_FRAME_OFFSET(r1)
343	lwz r3, GPR3_OFFSET(r1)
344	lwz r0, GPR0_OFFSET(r1)
345
346	mtsrr1 r4
347	mtsrr0 r2
348	lwz r4, GPR4_OFFSET(r1)
349	lwz r2, GPR2_OFFSET(r1)
350	addi r1,r1, EXCEPTION_FRAME_END
351	SYNC
352	rfi
353

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