[4055e6f8] | 1 | /* |
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| 2 | * This file contains the assembly code for the PowerPC |
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| 3 | * IRQ veneers for RTEMS. |
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| 4 | * |
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| 5 | * The license and distribution terms for this file may be |
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| 6 | * found in found in the file LICENSE in this distribution or at |
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| 7 | * http://www.OARcorp.com/rtems/license.html. |
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| 8 | * |
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| 9 | * Modified to support the MCP750. |
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| 10 | * Modifications Copyright (C) 1999 Eric Valette. valette@crf.canon.fr |
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| 11 | * |
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| 12 | * |
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| 13 | * $Id$ |
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| 14 | */ |
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| 15 | |
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| 16 | #include <bsp/vectors.h> |
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| 17 | #include <libcpu/cpu.h> |
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| 18 | #include <libcpu/raw_exception.h> |
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| 19 | #include <rtems/score/cpuopts.h> /* for PPC_HAS_FPU */ |
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| 20 | #include "asm.h" |
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| 21 | |
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| 22 | |
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| 23 | #define SYNC \ |
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| 24 | sync; \ |
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| 25 | isync |
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| 26 | |
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| 27 | .text |
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| 28 | .p2align 5 |
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| 29 | |
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| 30 | PUBLIC_VAR(decrementer_exception_vector_prolog_code) |
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| 31 | |
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| 32 | SYM (decrementer_exception_vector_prolog_code): |
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| 33 | /* |
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| 34 | * let room for exception frame |
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| 35 | */ |
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| 36 | stwu r1, - (EXCEPTION_FRAME_END)(r1) |
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| 37 | stw r4, GPR4_OFFSET(r1) |
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| 38 | li r4, ASM_DEC_VECTOR |
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| 39 | ba shared_raw_irq_code_entry |
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| 40 | |
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| 41 | PUBLIC_VAR (decrementer_exception_vector_prolog_code_size) |
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| 42 | |
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| 43 | decrementer_exception_vector_prolog_code_size = . - decrementer_exception_vector_prolog_code |
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| 44 | |
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| 45 | PUBLIC_VAR(external_exception_vector_prolog_code) |
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| 46 | |
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| 47 | SYM (external_exception_vector_prolog_code): |
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| 48 | /* |
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| 49 | * let room for exception frame |
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| 50 | */ |
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| 51 | stwu r1, - (EXCEPTION_FRAME_END)(r1) |
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| 52 | stw r4, GPR4_OFFSET(r1) |
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| 53 | li r4, ASM_EXT_VECTOR |
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| 54 | ba shared_raw_irq_code_entry |
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| 55 | |
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| 56 | PUBLIC_VAR (external_exception_vector_prolog_code_size) |
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| 57 | |
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| 58 | external_exception_vector_prolog_code_size = . - external_exception_vector_prolog_code |
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| 59 | |
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| 60 | PUBLIC_VAR(shared_raw_irq_code_entry) |
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| 61 | PUBLIC_VAR(C_dispatch_irq_handler) |
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| 62 | |
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| 63 | .p2align 5 |
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| 64 | SYM (shared_raw_irq_code_entry): |
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| 65 | /* |
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| 66 | * Entry conditions : |
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| 67 | * Registers already saved : R1, R4 |
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| 68 | * R1 : points to a location with enough room for the |
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| 69 | * interrupt frame |
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| 70 | * R4 : vector number |
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| 71 | */ |
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| 72 | /* |
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| 73 | * Save SRR0/SRR1 As soon As possible as it is the minimal needed |
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| 74 | * to reenable exception processing |
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| 75 | */ |
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| 76 | stw r0, GPR0_OFFSET(r1) |
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| 77 | stw r2, GPR2_OFFSET(r1) |
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| 78 | stw r3, GPR3_OFFSET(r1) |
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| 79 | |
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| 80 | mfsrr0 r0 |
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| 81 | mfsrr1 r2 |
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| 82 | mfmsr r3 |
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| 83 | |
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| 84 | stw r0, SRR0_FRAME_OFFSET(r1) |
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| 85 | stw r2, SRR1_FRAME_OFFSET(r1) |
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| 86 | /* |
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| 87 | * Enable data and instruction address translation, exception recovery |
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| 88 | * |
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| 89 | * also, on CPUs with FP, enable FP so that FP context can be |
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| 90 | * saved and restored (using FP instructions) |
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| 91 | */ |
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| 92 | #if (PPC_HAS_FPU == 0) |
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| 93 | ori r3, r3, MSR_RI | MSR_IR | MSR_DR |
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| 94 | #else |
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| 95 | ori r3, r3, MSR_RI | MSR_IR | MSR_DR | MSR_FP |
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| 96 | #endif |
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| 97 | mtmsr r3 |
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| 98 | SYNC |
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| 99 | /* |
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| 100 | * Push C scratch registers on the current stack. It may |
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| 101 | * actually be the thread stack or the interrupt stack. |
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| 102 | * Anyway we have to make it in order to be able to call C/C++ |
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| 103 | * functions. Depending on the nesting interrupt level, we will |
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| 104 | * switch to the right stack later. |
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| 105 | */ |
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| 106 | stw r5, GPR5_OFFSET(r1) |
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| 107 | stw r6, GPR6_OFFSET(r1) |
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| 108 | stw r7, GPR7_OFFSET(r1) |
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| 109 | stw r8, GPR8_OFFSET(r1) |
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| 110 | stw r9, GPR9_OFFSET(r1) |
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| 111 | stw r10, GPR10_OFFSET(r1) |
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| 112 | stw r11, GPR11_OFFSET(r1) |
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| 113 | stw r12, GPR12_OFFSET(r1) |
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| 114 | stw r13, GPR13_OFFSET(r1) |
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| 115 | |
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| 116 | mfcr r5 |
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| 117 | mfctr r6 |
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| 118 | mfxer r7 |
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| 119 | mflr r8 |
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| 120 | |
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| 121 | stw r5, EXC_CR_OFFSET(r1) |
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| 122 | stw r6, EXC_CTR_OFFSET(r1) |
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| 123 | stw r7, EXC_XER_OFFSET(r1) |
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| 124 | stw r8, EXC_LR_OFFSET(r1) |
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| 125 | |
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| 126 | /* |
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| 127 | * Add some non volatile registers to store information |
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| 128 | * that will be used when returning from C handler |
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| 129 | */ |
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| 130 | stw r14, GPR14_OFFSET(r1) |
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| 131 | stw r15, GPR15_OFFSET(r1) |
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| 132 | /* |
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| 133 | * save current stack pointer location in R14 |
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| 134 | */ |
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| 135 | addi r14, r1, 0 |
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| 136 | /* |
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| 137 | * store part of _Thread_Dispatch_disable_level address in R15 |
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| 138 | */ |
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| 139 | addis r15,0, _Thread_Dispatch_disable_level@ha |
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| 140 | /* |
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| 141 | * Get current nesting level in R2 |
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| 142 | */ |
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| 143 | mfspr r2, SPRG0 |
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| 144 | /* |
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| 145 | * Check if stack switch is necessary |
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| 146 | */ |
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| 147 | cmpwi r2,0 |
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| 148 | bne nested |
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| 149 | mfspr r1, SPRG1 |
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| 150 | |
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| 151 | nested: |
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| 152 | /* |
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| 153 | * Start Incrementing nesting level in R2 |
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| 154 | */ |
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| 155 | addi r2,r2,1 |
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| 156 | /* |
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| 157 | * Start Incrementing _Thread_Dispatch_disable_level R4 = _Thread_Dispatch_disable_level |
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| 158 | */ |
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| 159 | lwz r6,_Thread_Dispatch_disable_level@l(r15) |
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| 160 | /* |
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| 161 | * store new nesting level in SPRG0 |
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| 162 | */ |
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| 163 | mtspr SPRG0, r2 |
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| 164 | |
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| 165 | addi r6, r6, 1 |
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| 166 | mfmsr r5 |
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| 167 | /* |
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| 168 | * store new _Thread_Dispatch_disable_level value |
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| 169 | */ |
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| 170 | stw r6, _Thread_Dispatch_disable_level@l(r15) |
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| 171 | /* |
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| 172 | * We are now running on the interrupt stack. External and decrementer |
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| 173 | * exceptions are still disabled. I see no purpose trying to optimize |
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| 174 | * further assembler code. |
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| 175 | */ |
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| 176 | /* |
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| 177 | * Call C exception handler for decrementer Interrupt frame is passed just |
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| 178 | * in case... |
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| 179 | */ |
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| 180 | addi r3, r14, 0x8 |
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| 181 | bl C_dispatch_irq_handler /* C_dispatch_irq_handler(cpu_interrupt_frame* r3, vector r4) */ |
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| 182 | /* |
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| 183 | * start decrementing nesting level. Note : do not test result against 0 |
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| 184 | * value as an easy exit condition because if interrupt nesting level > 1 |
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| 185 | * then _Thread_Dispatch_disable_level > 1 |
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| 186 | */ |
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| 187 | mfspr r2, SPRG0 |
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| 188 | /* |
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| 189 | * start decrementing _Thread_Dispatch_disable_level |
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| 190 | */ |
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| 191 | lwz r3,_Thread_Dispatch_disable_level@l(r15) |
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| 192 | addi r2, r2, -1 /* Continue decrementing nesting level */ |
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| 193 | addi r3, r3, -1 /* Continue decrementing _Thread_Dispatch_disable_level */ |
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| 194 | mtspr SPRG0, r2 /* End decrementing nesting level */ |
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| 195 | stw r3,_Thread_Dispatch_disable_level@l(r15) /* End decrementing _Thread_Dispatch_disable_level */ |
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| 196 | cmpwi r3, 0 |
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| 197 | /* |
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| 198 | * switch back to original stack (done here just optimize registers |
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| 199 | * contention. Could have been done before...) |
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| 200 | */ |
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| 201 | addi r1, r14, 0 |
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| 202 | bne easy_exit /* if (_Thread_Dispatch_disable_level != 0) goto easy_exit */ |
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| 203 | /* |
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| 204 | * Here we are running again on the thread system stack. |
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| 205 | * We have interrupt nesting level = _Thread_Dispatch_disable_level = 0. |
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| 206 | * Interrupt are still disabled. Time to check if scheduler request to |
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| 207 | * do something with the current thread... |
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| 208 | */ |
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| 209 | addis r4, 0, _Context_Switch_necessary@ha |
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| 210 | lwz r5, _Context_Switch_necessary@l(r4) |
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| 211 | cmpwi r5, 0 |
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| 212 | bne switch |
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| 213 | |
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| 214 | addis r6, 0, _ISR_Signals_to_thread_executing@ha |
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| 215 | lwz r7, _ISR_Signals_to_thread_executing@l(r6) |
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| 216 | cmpwi r7, 0 |
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| 217 | li r8, 0 |
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| 218 | beq easy_exit |
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| 219 | stw r8, _ISR_Signals_to_thread_executing@l(r6) |
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| 220 | /* |
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| 221 | * going to call _ThreadProcessSignalsFromIrq |
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| 222 | * Push a complete exception like frame... |
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| 223 | */ |
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| 224 | stmw r16, GPR16_OFFSET(r1) |
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| 225 | addi r3, r1, 0x8 |
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| 226 | /* |
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| 227 | * compute SP at exception entry |
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| 228 | */ |
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| 229 | addi r2, r1, EXCEPTION_FRAME_END |
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| 230 | /* |
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| 231 | * store it at the right place |
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| 232 | */ |
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| 233 | stw r2, GPR1_OFFSET(r1) |
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| 234 | /* |
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| 235 | * Call High Level signal handling code |
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| 236 | */ |
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| 237 | bl _ThreadProcessSignalsFromIrq |
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| 238 | /* |
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| 239 | * start restoring exception like frame |
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| 240 | */ |
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| 241 | lwz r31, EXC_CTR_OFFSET(r1) |
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| 242 | lwz r30, EXC_XER_OFFSET(r1) |
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| 243 | lwz r29, EXC_CR_OFFSET(r1) |
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| 244 | lwz r28, EXC_LR_OFFSET(r1) |
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| 245 | |
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| 246 | mtctr r31 |
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| 247 | mtxer r30 |
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| 248 | mtcr r29 |
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| 249 | mtlr r28 |
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| 250 | |
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| 251 | lmw r4, GPR4_OFFSET(r1) |
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| 252 | lwz r2, GPR2_OFFSET(r1) |
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| 253 | lwz r0, GPR0_OFFSET(r1) |
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| 254 | |
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| 255 | /* |
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| 256 | * Disable data and instruction translation. Make path non recoverable... |
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| 257 | */ |
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| 258 | mfmsr r3 |
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| 259 | xori r3, r3, MSR_RI | MSR_IR | MSR_DR |
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| 260 | mtmsr r3 |
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| 261 | SYNC |
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| 262 | /* |
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| 263 | * Restore rfi related settings |
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| 264 | */ |
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| 265 | |
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| 266 | lwz r3, SRR1_FRAME_OFFSET(r1) |
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| 267 | mtsrr1 r3 |
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| 268 | lwz r3, SRR0_FRAME_OFFSET(r1) |
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| 269 | mtsrr0 r3 |
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| 270 | |
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| 271 | lwz r3, GPR3_OFFSET(r1) |
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| 272 | addi r1,r1, EXCEPTION_FRAME_END |
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| 273 | SYNC |
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| 274 | rfi |
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| 275 | |
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| 276 | switch: |
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| 277 | bl SYM (_Thread_Dispatch) |
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| 278 | |
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| 279 | easy_exit: |
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| 280 | /* |
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| 281 | * start restoring interrupt frame |
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| 282 | */ |
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| 283 | lwz r3, EXC_CTR_OFFSET(r1) |
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| 284 | lwz r4, EXC_XER_OFFSET(r1) |
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| 285 | lwz r5, EXC_CR_OFFSET(r1) |
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| 286 | lwz r6, EXC_LR_OFFSET(r1) |
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| 287 | |
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| 288 | mtctr r3 |
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| 289 | mtxer r4 |
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| 290 | mtcr r5 |
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| 291 | mtlr r6 |
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| 292 | |
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| 293 | lwz r15, GPR15_OFFSET(r1) |
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| 294 | lwz r14, GPR14_OFFSET(r1) |
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| 295 | lwz r13, GPR13_OFFSET(r1) |
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| 296 | lwz r12, GPR12_OFFSET(r1) |
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| 297 | lwz r11, GPR11_OFFSET(r1) |
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| 298 | lwz r10, GPR10_OFFSET(r1) |
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| 299 | lwz r9, GPR9_OFFSET(r1) |
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| 300 | lwz r8, GPR8_OFFSET(r1) |
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| 301 | lwz r7, GPR7_OFFSET(r1) |
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| 302 | lwz r6, GPR6_OFFSET(r1) |
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| 303 | lwz r5, GPR5_OFFSET(r1) |
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| 304 | |
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| 305 | /* |
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| 306 | * Disable nested exception processing, data and instruction |
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| 307 | * translation. |
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| 308 | */ |
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| 309 | mfmsr r3 |
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| 310 | xori r3, r3, MSR_RI | MSR_IR | MSR_DR |
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| 311 | mtmsr r3 |
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| 312 | SYNC |
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| 313 | /* |
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| 314 | * Restore rfi related settings |
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| 315 | */ |
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| 316 | |
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| 317 | lwz r4, SRR1_FRAME_OFFSET(r1) |
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| 318 | lwz r2, SRR0_FRAME_OFFSET(r1) |
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| 319 | lwz r3, GPR3_OFFSET(r1) |
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| 320 | lwz r0, GPR0_OFFSET(r1) |
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| 321 | |
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| 322 | mtsrr1 r4 |
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| 323 | mtsrr0 r2 |
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| 324 | lwz r4, GPR4_OFFSET(r1) |
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| 325 | lwz r2, GPR2_OFFSET(r1) |
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| 326 | addi r1,r1, EXCEPTION_FRAME_END |
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| 327 | SYNC |
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| 328 | rfi |
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| 329 | |
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