1 | /* |
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2 | * |
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3 | * This file contains the implementation of the function described in irq.h |
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4 | * |
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5 | * Copyright (C) 1998, 1999 valette@crf.canon.fr |
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6 | * |
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7 | * The license and distribution terms for this file may be |
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8 | * found in found in the file LICENSE in this distribution or at |
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9 | * http://www.rtems.com/license/LICENSE. |
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10 | * |
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11 | * $Id$ |
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12 | */ |
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13 | |
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14 | #include <rtems/system.h> |
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15 | #include <bsp.h> |
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16 | #include <bsp/irq.h> |
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17 | #include <rtems/score/thread.h> |
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18 | #include <rtems/score/apiext.h> |
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19 | #include <libcpu/raw_exception.h> |
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20 | #include <bsp/vectors.h> |
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21 | #include <bsp/8xx_immap.h> |
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22 | #include <bsp/commproc.h> |
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23 | |
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24 | /* |
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25 | * default handler connected on each irq after bsp initialization |
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26 | */ |
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27 | static rtems_irq_connect_data default_rtems_entry; |
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28 | |
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29 | /* |
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30 | * location used to store initial tables used for interrupt |
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31 | * management. |
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32 | */ |
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33 | static rtems_irq_global_settings* internal_config; |
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34 | static rtems_irq_connect_data* rtems_hdl_tbl; |
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35 | |
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36 | /* |
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37 | * Check if symbolic IRQ name is an SIU IRQ |
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38 | */ |
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39 | static inline int is_siu_irq(const rtems_irq_symbolic_name irqLine) |
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40 | { |
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41 | return (((int) irqLine <= BSP_SIU_IRQ_MAX_OFFSET) & |
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42 | ((int) irqLine >= BSP_SIU_IRQ_LOWEST_OFFSET) |
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43 | ); |
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44 | } |
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45 | |
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46 | /* |
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47 | * Check if symbolic IRQ name is an CPM IRQ |
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48 | */ |
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49 | static inline int is_cpm_irq(const rtems_irq_symbolic_name irqLine) |
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50 | { |
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51 | return (((int) irqLine <= BSP_CPM_IRQ_MAX_OFFSET) & |
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52 | ((int) irqLine >= BSP_CPM_IRQ_LOWEST_OFFSET) |
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53 | ); |
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54 | } |
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55 | |
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56 | /* |
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57 | * Check if symbolic IRQ name is a Processor IRQ |
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58 | */ |
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59 | static inline int is_processor_irq(const rtems_irq_symbolic_name irqLine) |
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60 | { |
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61 | return (((int) irqLine <= BSP_PROCESSOR_IRQ_MAX_OFFSET) & |
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62 | ((int) irqLine >= BSP_PROCESSOR_IRQ_LOWEST_OFFSET) |
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63 | ); |
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64 | } |
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65 | |
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66 | /* |
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67 | * masks used to mask off the interrupts. For exmaple, for ILVL2, the |
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68 | * mask is used to mask off interrupts ILVL2, IRQ3, ILVL3, ... IRQ7 |
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69 | * and ILVL7. |
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70 | * |
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71 | */ |
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72 | const static unsigned int SIU_IvectMask[BSP_SIU_IRQ_NUMBER] = |
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73 | { |
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74 | /* IRQ0 ILVL0 IRQ1 ILVL1 */ |
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75 | 0x00000000, 0x80000000, 0xC0000000, 0xE0000000, |
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76 | |
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77 | /* IRQ2 ILVL2 IRQ3 ILVL3 */ |
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78 | 0xF0000000, 0xF8000000, 0xFC000000, 0xFE000000, |
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79 | |
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80 | /* IRQ4 ILVL4 IRQ5 ILVL5 */ |
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81 | 0xFF000000, 0xFF800000, 0xFFC00000, 0xFFE00000, |
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82 | |
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83 | /* IRQ6 ILVL6 IRQ7 ILVL7 */ |
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84 | 0xFFF00000, 0xFFF80000, 0xFFFC0000, 0xFFFE0000 |
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85 | }; |
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86 | |
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87 | /* |
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88 | * ------------------------ RTEMS Irq helper functions ---------------- |
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89 | */ |
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90 | |
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91 | /* |
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92 | * Caution : this function assumes the variable "internal_config" |
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93 | * is already set and that the tables it contains are still valid |
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94 | * and accessible. |
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95 | */ |
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96 | static void compute_SIU_IvectMask_from_prio () |
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97 | { |
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98 | /* |
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99 | * In theory this is feasible. No time to code it yet. See i386/shared/irq.c |
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100 | * for an example based on 8259 controller mask. The actual masks defined |
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101 | * correspond to the priorities defined for the SIU in irq_init.c. |
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102 | */ |
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103 | } |
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104 | |
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105 | /* |
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106 | * This function check that the value given for the irq line |
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107 | * is valid. |
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108 | */ |
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109 | |
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110 | static int isValidInterrupt(int irq) |
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111 | { |
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112 | if ( (irq < BSP_LOWEST_OFFSET) || (irq > BSP_MAX_OFFSET) || (irq == BSP_CPM_INTERRUPT) ) |
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113 | return 0; |
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114 | return 1; |
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115 | } |
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116 | |
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117 | int BSP_irq_enable_at_cpm(const rtems_irq_symbolic_name irqLine) |
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118 | { |
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119 | int cpm_irq_index; |
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120 | |
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121 | if (!is_cpm_irq(irqLine)) |
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122 | return 1; |
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123 | |
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124 | cpm_irq_index = ((int) (irqLine) - BSP_CPM_IRQ_LOWEST_OFFSET); |
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125 | ((volatile immap_t *)IMAP_ADDR)->im_cpic.cpic_cimr |= (1 << cpm_irq_index); |
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126 | |
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127 | return 0; |
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128 | } |
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129 | |
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130 | int BSP_irq_disable_at_cpm(const rtems_irq_symbolic_name irqLine) |
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131 | { |
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132 | int cpm_irq_index; |
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133 | |
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134 | if (!is_cpm_irq(irqLine)) |
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135 | return 1; |
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136 | |
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137 | cpm_irq_index = ((int) (irqLine) - BSP_CPM_IRQ_LOWEST_OFFSET); |
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138 | ((volatile immap_t *)IMAP_ADDR)->im_cpic.cpic_cimr &= ~(1 << cpm_irq_index); |
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139 | |
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140 | return 0; |
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141 | } |
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142 | |
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143 | int BSP_irq_enabled_at_cpm(const rtems_irq_symbolic_name irqLine) |
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144 | { |
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145 | int cpm_irq_index; |
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146 | |
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147 | if (!is_cpm_irq(irqLine)) |
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148 | return 0; |
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149 | |
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150 | cpm_irq_index = ((int) (irqLine) - BSP_CPM_IRQ_LOWEST_OFFSET); |
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151 | return (((volatile immap_t *)IMAP_ADDR)->im_cpic.cpic_cimr & (1 << cpm_irq_index)); |
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152 | } |
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153 | |
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154 | int BSP_irq_enable_at_siu(const rtems_irq_symbolic_name irqLine) |
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155 | { |
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156 | int siu_irq_index; |
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157 | |
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158 | if (!is_siu_irq(irqLine)) |
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159 | return 1; |
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160 | |
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161 | siu_irq_index = ((int) (irqLine) - BSP_SIU_IRQ_LOWEST_OFFSET); |
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162 | ppc_cached_irq_mask |= (1 << (31-siu_irq_index)); |
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163 | ((volatile immap_t *)IMAP_ADDR)->im_siu_conf.sc_simask = ppc_cached_irq_mask; |
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164 | |
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165 | return 0; |
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166 | } |
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167 | |
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168 | int BSP_irq_disable_at_siu(const rtems_irq_symbolic_name irqLine) |
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169 | { |
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170 | int siu_irq_index; |
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171 | |
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172 | if (!is_siu_irq(irqLine)) |
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173 | return 1; |
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174 | |
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175 | siu_irq_index = ((int) (irqLine) - BSP_SIU_IRQ_LOWEST_OFFSET); |
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176 | ppc_cached_irq_mask &= ~(1 << (31-siu_irq_index)); |
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177 | ((volatile immap_t *)IMAP_ADDR)->im_siu_conf.sc_simask = ppc_cached_irq_mask; |
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178 | |
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179 | return 0; |
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180 | } |
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181 | |
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182 | int BSP_irq_enabled_at_siu (const rtems_irq_symbolic_name irqLine) |
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183 | { |
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184 | int siu_irq_index; |
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185 | |
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186 | if (!is_siu_irq(irqLine)) |
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187 | return 0; |
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188 | |
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189 | siu_irq_index = ((int) (irqLine) - BSP_SIU_IRQ_LOWEST_OFFSET); |
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190 | return ppc_cached_irq_mask & (1 << (31-siu_irq_index)); |
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191 | } |
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192 | |
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193 | /* |
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194 | * ------------------------ RTEMS Single Irq Handler Mngt Routines ---------------- |
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195 | */ |
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196 | |
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197 | int BSP_install_rtems_irq_handler (const rtems_irq_connect_data* irq) |
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198 | { |
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199 | unsigned int level; |
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200 | |
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201 | if (!isValidInterrupt(irq->name)) { |
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202 | return 0; |
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203 | } |
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204 | /* |
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205 | * Check if default handler is actually connected. If not issue an error. |
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206 | * You must first get the current handler via i386_get_current_idt_entry |
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207 | * and then disconnect it using i386_delete_idt_entry. |
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208 | * RATIONALE : to always have the same transition by forcing the user |
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209 | * to get the previous handler before accepting to disconnect. |
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210 | */ |
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211 | if (rtems_hdl_tbl[irq->name].hdl != default_rtems_entry.hdl) { |
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212 | return 0; |
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213 | } |
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214 | |
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215 | _CPU_ISR_Disable(level); |
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216 | |
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217 | /* |
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218 | * store the data provided by user |
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219 | */ |
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220 | rtems_hdl_tbl[irq->name] = *irq; |
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221 | |
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222 | if (is_cpm_irq(irq->name)) { |
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223 | /* |
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224 | * Enable interrupt at PIC level |
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225 | */ |
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226 | BSP_irq_enable_at_cpm (irq->name); |
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227 | } |
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228 | |
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229 | if (is_siu_irq(irq->name)) { |
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230 | /* |
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231 | * Enable interrupt at SIU level |
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232 | */ |
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233 | BSP_irq_enable_at_siu (irq->name); |
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234 | } |
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235 | |
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236 | if (is_processor_irq(irq->name)) { |
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237 | /* |
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238 | * Should Enable exception at processor level but not needed. Will restore |
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239 | * EE flags at the end of the routine anyway. |
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240 | */ |
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241 | } |
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242 | /* |
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243 | * Enable interrupt on device |
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244 | */ |
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245 | irq->on(irq); |
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246 | |
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247 | _CPU_ISR_Enable(level); |
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248 | |
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249 | return 1; |
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250 | } |
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251 | |
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252 | int BSP_get_current_rtems_irq_handler (rtems_irq_connect_data* irq) |
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253 | { |
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254 | if (!isValidInterrupt(irq->name)) { |
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255 | return 0; |
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256 | } |
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257 | *irq = rtems_hdl_tbl[irq->name]; |
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258 | return 1; |
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259 | } |
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260 | |
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261 | int BSP_remove_rtems_irq_handler (const rtems_irq_connect_data* irq) |
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262 | { |
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263 | unsigned int level; |
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264 | |
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265 | if (!isValidInterrupt(irq->name)) { |
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266 | return 0; |
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267 | } |
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268 | /* |
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269 | * Check if default handler is actually connected. If not issue an error. |
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270 | * You must first get the current handler via i386_get_current_idt_entry |
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271 | * and then disconnect it using i386_delete_idt_entry. |
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272 | * RATIONALE : to always have the same transition by forcing the user |
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273 | * to get the previous handler before accepting to disconnect. |
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274 | */ |
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275 | if (rtems_hdl_tbl[irq->name].hdl != irq->hdl) { |
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276 | return 0; |
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277 | } |
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278 | _CPU_ISR_Disable(level); |
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279 | |
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280 | if (is_cpm_irq(irq->name)) { |
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281 | /* |
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282 | * disable interrupt at PIC level |
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283 | */ |
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284 | BSP_irq_disable_at_cpm (irq->name); |
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285 | } |
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286 | if (is_siu_irq(irq->name)) { |
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287 | /* |
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288 | * disable interrupt at OPENPIC level |
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289 | */ |
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290 | BSP_irq_disable_at_siu (irq->name); |
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291 | } |
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292 | if (is_processor_irq(irq->name)) { |
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293 | /* |
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294 | * disable exception at processor level |
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295 | */ |
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296 | } |
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297 | |
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298 | /* |
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299 | * Disable interrupt on device |
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300 | */ |
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301 | irq->off(irq); |
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302 | |
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303 | /* |
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304 | * restore the default irq value |
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305 | */ |
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306 | rtems_hdl_tbl[irq->name] = default_rtems_entry; |
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307 | |
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308 | _CPU_ISR_Enable(level); |
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309 | |
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310 | return 1; |
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311 | } |
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312 | |
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313 | /* |
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314 | * ------------------------ RTEMS Global Irq Handler Mngt Routines ---------------- |
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315 | */ |
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316 | |
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317 | int BSP_rtems_irq_mngt_set(rtems_irq_global_settings* config) |
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318 | { |
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319 | int i; |
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320 | unsigned int level; |
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321 | /* |
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322 | * Store various code accelerators |
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323 | */ |
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324 | internal_config = config; |
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325 | default_rtems_entry = config->defaultEntry; |
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326 | rtems_hdl_tbl = config->irqHdlTbl; |
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327 | |
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328 | _CPU_ISR_Disable(level); |
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329 | /* |
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330 | * start with CPM IRQ |
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331 | */ |
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332 | for (i=BSP_CPM_IRQ_LOWEST_OFFSET; i < BSP_CPM_IRQ_LOWEST_OFFSET + BSP_CPM_IRQ_NUMBER ; i++) { |
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333 | if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) { |
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334 | BSP_irq_enable_at_cpm (i); |
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335 | rtems_hdl_tbl[i].on(&rtems_hdl_tbl[i]); |
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336 | } |
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337 | else { |
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338 | rtems_hdl_tbl[i].off(&rtems_hdl_tbl[i]); |
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339 | BSP_irq_disable_at_cpm (i); |
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340 | } |
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341 | } |
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342 | |
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343 | /* |
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344 | * continue with PCI IRQ |
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345 | */ |
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346 | /* |
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347 | * set up internal tables used by rtems interrupt prologue |
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348 | */ |
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349 | compute_SIU_IvectMask_from_prio (); |
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350 | |
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351 | for (i=BSP_SIU_IRQ_LOWEST_OFFSET; i < BSP_SIU_IRQ_LOWEST_OFFSET + BSP_SIU_IRQ_NUMBER ; i++) { |
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352 | if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) { |
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353 | BSP_irq_enable_at_siu (i); |
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354 | rtems_hdl_tbl[i].on(&rtems_hdl_tbl[i]); |
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355 | } |
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356 | else { |
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357 | rtems_hdl_tbl[i].off(&rtems_hdl_tbl[i]); |
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358 | BSP_irq_disable_at_siu (i); |
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359 | } |
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360 | } |
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361 | /* |
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362 | * Must enable CPM interrupt on SIU. CPM on SIU Interrupt level has already been |
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363 | * set up in BSP_CPM_irq_init. |
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364 | */ |
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365 | ((volatile immap_t *)IMAP_ADDR)->im_cpic.cpic_cicr |= CICR_IEN; |
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366 | BSP_irq_enable_at_siu (BSP_CPM_INTERRUPT); |
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367 | /* |
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368 | * finish with Processor exceptions handled like IRQ |
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369 | */ |
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370 | for (i=BSP_PROCESSOR_IRQ_LOWEST_OFFSET; i < BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER; i++) { |
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371 | if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) { |
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372 | rtems_hdl_tbl[i].on(&rtems_hdl_tbl[i]); |
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373 | } |
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374 | else { |
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375 | rtems_hdl_tbl[i].off(&rtems_hdl_tbl[i]); |
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376 | } |
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377 | } |
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378 | _CPU_ISR_Enable(level); |
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379 | return 1; |
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380 | } |
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381 | |
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382 | int BSP_rtems_irq_mngt_get(rtems_irq_global_settings** config) |
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383 | { |
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384 | *config = internal_config; |
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385 | return 0; |
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386 | } |
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387 | |
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388 | #ifdef DISPATCH_HANDLER_STAT |
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389 | volatile unsigned int maxLoop = 0; |
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390 | #endif |
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391 | |
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392 | /* |
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393 | * High level IRQ handler called from shared_raw_irq_code_entry |
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394 | */ |
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395 | void C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum) |
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396 | { |
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397 | register unsigned int irq; |
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398 | register unsigned cpmIntr; /* boolean */ |
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399 | register unsigned oldMask; /* old siu pic masks */ |
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400 | register unsigned msr; |
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401 | register unsigned new_msr; |
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402 | #ifdef DISPATCH_HANDLER_STAT |
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403 | unsigned loopCounter; |
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404 | #endif |
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405 | /* |
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406 | * Handle decrementer interrupt |
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407 | */ |
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408 | if (excNum == ASM_DEC_VECTOR) { |
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409 | _CPU_MSR_GET(msr); |
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410 | new_msr = msr | MSR_EE; |
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411 | _CPU_MSR_SET(new_msr); |
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412 | |
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413 | rtems_hdl_tbl[BSP_DECREMENTER].hdl(); |
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414 | |
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415 | _CPU_MSR_SET(msr); |
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416 | return; |
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417 | } |
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418 | /* |
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419 | * Handle external interrupt generated by SIU on PPC core |
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420 | */ |
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421 | #ifdef DISPATCH_HANDLER_STAT |
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422 | loopCounter = 0; |
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423 | #endif |
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424 | while (1) { |
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425 | if ((ppc_cached_irq_mask & ((volatile immap_t *)IMAP_ADDR)->im_siu_conf.sc_sipend) == 0) { |
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426 | #ifdef DISPATCH_HANDLER_STAT |
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427 | if (loopCounter > maxLoop) maxLoop = loopCounter; |
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428 | #endif |
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429 | break; |
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430 | } |
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431 | irq = (((volatile immap_t *)IMAP_ADDR)->im_siu_conf.sc_sivec >> 26); |
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432 | cpmIntr = (irq == BSP_CPM_INTERRUPT); |
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433 | /* |
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434 | * Disable the interrupt of the same and lower priority. |
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435 | */ |
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436 | oldMask = ppc_cached_irq_mask; |
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437 | ppc_cached_irq_mask = oldMask & SIU_IvectMask[irq]; |
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438 | ((volatile immap_t *)IMAP_ADDR)->im_siu_conf.sc_simask = ppc_cached_irq_mask; |
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439 | /* |
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440 | * Acknowledge current interrupt. This has no effect on internal level interrupt. |
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441 | */ |
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442 | ((volatile immap_t *)IMAP_ADDR)->im_siu_conf.sc_sipend = (1 << (31 - irq)); |
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443 | |
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444 | if (cpmIntr) { |
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445 | /* |
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446 | * We will reenable the SIU CPM interrupt to allow nesting of CPM interrupt. |
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447 | * We must before acknowledege the current irq at CPM level to avoid trigerring |
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448 | * the interrupt again. |
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449 | */ |
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450 | /* |
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451 | * Acknowledge and get the vector. |
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452 | */ |
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453 | ((volatile immap_t *)IMAP_ADDR)->im_cpic.cpic_civr = 1; |
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454 | irq = (((volatile immap_t *)IMAP_ADDR)->im_cpic.cpic_civr >> 11); |
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455 | /* |
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456 | * transform IRQ to normalized irq table index. |
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457 | */ |
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458 | irq += BSP_CPM_IRQ_LOWEST_OFFSET; |
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459 | /* |
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460 | * Unmask CPM interrupt at SIU level |
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461 | */ |
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462 | ppc_cached_irq_mask |= (1 << (31 - BSP_CPM_INTERRUPT)); |
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463 | ((volatile immap_t *)IMAP_ADDR)->im_siu_conf.sc_simask = ppc_cached_irq_mask; |
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464 | } |
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465 | _CPU_MSR_GET(msr); |
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466 | new_msr = msr | MSR_EE; |
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467 | _CPU_MSR_SET(new_msr); |
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468 | |
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469 | rtems_hdl_tbl[irq].hdl(); |
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470 | |
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471 | _CPU_MSR_SET(msr); |
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472 | |
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473 | if (cpmIntr) { |
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474 | irq -= BSP_CPM_IRQ_LOWEST_OFFSET; |
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475 | ((volatile immap_t *)IMAP_ADDR)->im_cpic.cpic_cisr = (1 << irq); |
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476 | } |
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477 | ppc_cached_irq_mask |= (oldMask & ~(SIU_IvectMask[irq])); |
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478 | ((volatile immap_t *)IMAP_ADDR)->im_siu_conf.sc_simask = ppc_cached_irq_mask; |
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479 | #ifdef DISPATCH_HANDLER_STAT |
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480 | ++ loopCounter; |
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481 | #endif |
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482 | } |
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483 | } |
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484 | |
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485 | void _ThreadProcessSignalsFromIrq (BSP_Exception_frame* ctx) |
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486 | { |
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487 | /* |
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488 | * Process pending signals that have not already been |
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489 | * processed by _Thread_Displatch. This happens quite |
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490 | * unfrequently : the ISR must have posted an action |
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491 | * to the current running thread. |
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492 | */ |
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493 | if ( _Thread_Do_post_task_switch_extension || |
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494 | _Thread_Executing->do_post_task_switch_extension ) { |
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495 | _Thread_Executing->do_post_task_switch_extension = FALSE; |
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496 | _API_extensions_Run_postswitch(); |
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497 | } |
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498 | /* |
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499 | * I plan to process other thread related events here. |
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500 | * This will include DEBUG session requested from keyboard... |
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501 | */ |
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502 | } |
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