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source: rtems/c/src/lib/libbsp/powerpc/eth_comm/include/commproc.h @ 4055e6f8

4.104.114.84.95

Last change on this file since 4055e6f8 was 4055e6f8, checked in by Joel Sherrill <joel.sherrill@…>, on 04/16/01 at 20:18:03

2001-04-11 Eric Valette <valette@…>

clock/.cvsignore, clock/Makefile.am, clock/p_clock.c, include/8xx_immap.h, include/commproc.h, irq/.cvsignore, irq/Makefile.am, irq/irq.c, irq/irq.h, irq/irq_asm.S, irq/irq_init.c, vectors/.cvsignore, vectors/Makefile.am, vectors/vectors.S, vectors/vectors.h, vectors/vectors_init.c: New file.
Switch the eth_comm BSP to use the "new exception processing model."

Property mode set to 100644

File size: 19.9 KB

Line
1
2	/*
3	* MPC8xx Communication Processor Module.
4	* Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
5	*
6	* This file contains structures and information for the communication
7	* processor channels. Some CPM control and status is available
8	* throught the MPC8xx internal memory map. See immap.h for details.
9	* This file only contains what I need for the moment, not the total
10	* CPM capabilities. I (or someone else) will add definitions as they
11	* are needed. -- Dan
12	*
13	* On the MBX board, EPPC-Bug loads CPM microcode into the first 512
14	* bytes of the DP RAM and relocates the I2C parameter area to the
15	* IDMA1 space. The remaining DP RAM is available for buffer descriptors
16	* or other use.
17	*/
18	#ifndef __CPM_8XX__
19	#define __CPM_8XX__
20
21	#include <bsp/8xx_immap.h>
22
23	/* CPM Command register.
24	*/
25	#define CPM_CR_RST ((ushort)0x8000)
26	#define CPM_CR_OPCODE ((ushort)0x0f00)
27	#define CPM_CR_CHAN ((ushort)0x00f0)
28	#define CPM_CR_FLG ((ushort)0x0001)
29
30	/* Some commands (there are more...later)
31	*/
32	#define CPM_CR_INIT_TRX ((ushort)0x0000)
33	#define CPM_CR_INIT_RX ((ushort)0x0001)
34	#define CPM_CR_INIT_TX ((ushort)0x0002)
35	#define CPM_CR_STOP_TX ((ushort)0x0004)
36	#define CPM_CR_RESTART_TX ((ushort)0x0006)
37	#define CPM_CR_SET_GADDR ((ushort)0x0008)
38
39	/* Channel numbers.
40	*/
41	#define CPM_CR_CH_SCC1 ((ushort)0x0000)
42	#define CPM_CR_CH_I2C ((ushort)0x0001) /* I2C and IDMA1 */
43	#define CPM_CR_CH_SCC2 ((ushort)0x0004)
44	#define CPM_CR_CH_SPI ((ushort)0x0005) /* SPI / IDMA2 / Timers */
45	#define CPM_CR_CH_SCC3 ((ushort)0x0008)
46	#define CPM_CR_CH_SMC1 ((ushort)0x0009) /* SMC1 / DSP1 */
47	#define CPM_CR_CH_SCC4 ((ushort)0x000c)
48	#define CPM_CR_CH_SMC2 ((ushort)0x000d) /* SMC2 / DSP2 */
49
50	#define mk_cr_cmd(CH, CMD) ((CMD << 8) \| (CH << 4))
51
52	/* The dual ported RAM is multi-functional. Some areas can be (and are
53	* being) used for microcode. There is an area that can only be used
54	* as data ram for buffer descriptors, which is all we use right now.
55	* Currently the first 512 and last 256 bytes are used for microcode.
56	*/
57	#define CPM_DATAONLY_BASE ((uint)0x0800)
58	#define CPM_DATAONLY_SIZE ((uint)0x0700)
59	#define CPM_DP_NOSPACE ((uint)0x7fffffff)
60
61	/* Export the base address of the communication processor registers
62	* and dual port ram.
63	*/
64	extern cpm8xx_t cpmp; / Pointer to comm processor */
65	uint m8xx_cpm_dpalloc(uint size);
66	uint m8xx_cpm_hostalloc(uint size);
67	void m8xx_cpm_setbrg(uint brg, uint rate);
68
69	/* Buffer descriptors used by many of the CPM protocols.
70	*/
71	typedef struct cpm_buf_desc {
72	ushort cbd_sc; /* Status and Control */
73	ushort cbd_datlen; /* Data length in buffer */
74	uint cbd_bufaddr; /* Buffer address in host memory */
75	} cbd_t;
76
77	#define BD_SC_EMPTY ((ushort)0x8000) /* Recieve is empty */
78	#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */
79	#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */
80	#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
81	#define BD_SC_CM ((ushort)0x0200) /* Continous mode */
82	#define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */
83	#define BD_SC_P ((ushort)0x0100) /* xmt preamble */
84	#define BD_SC_BR ((ushort)0x0020) /* Break received */
85	#define BD_SC_FR ((ushort)0x0010) /* Framing error */
86	#define BD_SC_PR ((ushort)0x0008) /* Parity error */
87	#define BD_SC_OV ((ushort)0x0002) /* Overrun */
88	#define BD_SC_CD ((ushort)0x0001) /* ?? */
89
90	/* Parameter RAM offsets.
91	*/
92	#define PROFF_SCC1 ((uint)0x0000)
93	#define PROFF_SCC2 ((uint)0x0100)
94	#define PROFF_SCC3 ((uint)0x0200)
95	#define PROFF_SMC1 ((uint)0x0280)
96	#define PROFF_SCC4 ((uint)0x0300)
97	#define PROFF_SMC2 ((uint)0x0380)
98
99	/* Define enough so I can at least use the serial port as a UART.
100	*/
101	typedef struct smc_uart {
102	ushort smc_rbase; /* Rx Buffer descriptor base address */
103	ushort smc_tbase; /* Tx Buffer descriptor base address */
104	u_char smc_rfcr; /* Rx function code */
105	u_char smc_tfcr; /* Tx function code */
106	ushort smc_mrblr; /* Max receive buffer length */
107	uint smc_rstate; /* Internal */
108	uint smc_idp; /* Internal */
109	ushort smc_rbptr; /* Internal */
110	ushort smc_ibc; /* Internal */
111	uint smc_rxtmp; /* Internal */
112	uint smc_tstate; /* Internal */
113	uint smc_tdp; /* Internal */
114	ushort smc_tbptr; /* Internal */
115	ushort smc_tbc; /* Internal */
116	uint smc_txtmp; /* Internal */
117	ushort smc_maxidl; /* Maximum idle characters */
118	ushort smc_tmpidl; /* Temporary idle counter */
119	ushort smc_brklen; /* Last received break length */
120	ushort smc_brkec; /* rcv'd break condition counter */
121	ushort smc_brkcr; /* xmt break count register */
122	ushort smc_rmask; /* Temporary bit mask */
123	} smc_uart_t;
124
125	/* Function code bits.
126	*/
127	#define SMC_EB ((u_char)0x10) /* Set big endian byte order */
128
129	/* SMC uart mode register.
130	*/
131	#define SMCMR_REN ((ushort)0x0001)
132	#define SMCMR_TEN ((ushort)0x0002)
133	#define SMCMR_DM ((ushort)0x000c)
134	#define SMCMR_SM_GCI ((ushort)0x0000)
135	#define SMCMR_SM_UART ((ushort)0x0020)
136	#define SMCMR_SM_TRANS ((ushort)0x0030)
137	#define SMCMR_SM_MASK ((ushort)0x0030)
138	#define SMCMR_PM_EVEN ((ushort)0x0100) /* Even parity, else odd */
139	#define SMCMR_PEN ((ushort)0x0200) /* Parity enable */
140	#define SMCMR_SL ((ushort)0x0400) /* Two stops, else one */
141	#define SMCR_CLEN_MASK ((ushort)0x7800) /* Character length */
142	#define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK)
143
144	/* SMC Event and Mask register.
145	*/
146	#define SMCM_TXE ((unsigned char)0x10)
147	#define SMCM_BSY ((unsigned char)0x04)
148	#define SMCM_TX ((unsigned char)0x02)
149	#define SMCM_RX ((unsigned char)0x01)
150
151	/* Baud rate generators.
152	*/
153	#define CPM_BRG_RST ((uint)0x00020000)
154	#define CPM_BRG_EN ((uint)0x00010000)
155	#define CPM_BRG_EXTC_INT ((uint)0x00000000)
156	#define CPM_BRG_EXTC_CLK2 ((uint)0x00004000)
157	#define CPM_BRG_EXTC_CLK6 ((uint)0x00008000)
158	#define CPM_BRG_ATB ((uint)0x00002000)
159	#define CPM_BRG_CD_MASK ((uint)0x00001ffe)
160	#define CPM_BRG_DIV16 ((uint)0x00000001)
161
162	/* SCCs.
163	*/
164	#define SCC_GSMRH_IRP ((uint)0x00040000)
165	#define SCC_GSMRH_GDE ((uint)0x00010000)
166	#define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000)
167	#define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000)
168	#define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000)
169	#define SCC_GSMRH_REVD ((uint)0x00002000)
170	#define SCC_GSMRH_TRX ((uint)0x00001000)
171	#define SCC_GSMRH_TTX ((uint)0x00000800)
172	#define SCC_GSMRH_CDP ((uint)0x00000400)
173	#define SCC_GSMRH_CTSP ((uint)0x00000200)
174	#define SCC_GSMRH_CDS ((uint)0x00000100)
175	#define SCC_GSMRH_CTSS ((uint)0x00000080)
176	#define SCC_GSMRH_TFL ((uint)0x00000040)
177	#define SCC_GSMRH_RFW ((uint)0x00000020)
178	#define SCC_GSMRH_TXSY ((uint)0x00000010)
179	#define SCC_GSMRH_SYNL16 ((uint)0x0000000c)
180	#define SCC_GSMRH_SYNL8 ((uint)0x00000008)
181	#define SCC_GSMRH_SYNL4 ((uint)0x00000004)
182	#define SCC_GSMRH_RTSM ((uint)0x00000002)
183	#define SCC_GSMRH_RSYN ((uint)0x00000001)
184
185	#define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */
186	#define SCC_GSMRL_EDGE_NONE ((uint)0x60000000)
187	#define SCC_GSMRL_EDGE_NEG ((uint)0x40000000)
188	#define SCC_GSMRL_EDGE_POS ((uint)0x20000000)
189	#define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000)
190	#define SCC_GSMRL_TCI ((uint)0x10000000)
191	#define SCC_GSMRL_TSNC_3 ((uint)0x0c000000)
192	#define SCC_GSMRL_TSNC_4 ((uint)0x08000000)
193	#define SCC_GSMRL_TSNC_14 ((uint)0x04000000)
194	#define SCC_GSMRL_TSNC_INF ((uint)0x00000000)
195	#define SCC_GSMRL_RINV ((uint)0x02000000)
196	#define SCC_GSMRL_TINV ((uint)0x01000000)
197	#define SCC_GSMRL_TPL_128 ((uint)0x00c00000)
198	#define SCC_GSMRL_TPL_64 ((uint)0x00a00000)
199	#define SCC_GSMRL_TPL_48 ((uint)0x00800000)
200	#define SCC_GSMRL_TPL_32 ((uint)0x00600000)
201	#define SCC_GSMRL_TPL_16 ((uint)0x00400000)
202	#define SCC_GSMRL_TPL_8 ((uint)0x00200000)
203	#define SCC_GSMRL_TPL_NONE ((uint)0x00000000)
204	#define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000)
205	#define SCC_GSMRL_TPP_01 ((uint)0x00100000)
206	#define SCC_GSMRL_TPP_10 ((uint)0x00080000)
207	#define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000)
208	#define SCC_GSMRL_TEND ((uint)0x00040000)
209	#define SCC_GSMRL_TDCR_32 ((uint)0x00030000)
210	#define SCC_GSMRL_TDCR_16 ((uint)0x00020000)
211	#define SCC_GSMRL_TDCR_8 ((uint)0x00010000)
212	#define SCC_GSMRL_TDCR_1 ((uint)0x00000000)
213	#define SCC_GSMRL_RDCR_32 ((uint)0x0000c000)
214	#define SCC_GSMRL_RDCR_16 ((uint)0x00008000)
215	#define SCC_GSMRL_RDCR_8 ((uint)0x00004000)
216	#define SCC_GSMRL_RDCR_1 ((uint)0x00000000)
217	#define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000)
218	#define SCC_GSMRL_RENC_MANCH ((uint)0x00002000)
219	#define SCC_GSMRL_RENC_FM0 ((uint)0x00001000)
220	#define SCC_GSMRL_RENC_NRZI ((uint)0x00000800)
221	#define SCC_GSMRL_RENC_NRZ ((uint)0x00000000)
222	#define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600)
223	#define SCC_GSMRL_TENC_MANCH ((uint)0x00000400)
224	#define SCC_GSMRL_TENC_FM0 ((uint)0x00000200)
225	#define SCC_GSMRL_TENC_NRZI ((uint)0x00000100)
226	#define SCC_GSMRL_TENC_NRZ ((uint)0x00000000)
227	#define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */
228	#define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080)
229	#define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040)
230	#define SCC_GSMRL_DIAG_NORM ((uint)0x00000000)
231	#define SCC_GSMRL_ENR ((uint)0x00000020)
232	#define SCC_GSMRL_ENT ((uint)0x00000010)
233	#define SCC_GSMRL_MODE_ENET ((uint)0x0000000c)
234	#define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009)
235	#define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008)
236	#define SCC_GSMRL_MODE_V14 ((uint)0x00000007)
237	#define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006)
238	#define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005)
239	#define SCC_GSMRL_MODE_UART ((uint)0x00000004)
240	#define SCC_GSMRL_MODE_SS7 ((uint)0x00000003)
241	#define SCC_GSMRL_MODE_ATALK ((uint)0x00000002)
242	#define SCC_GSMRL_MODE_HDLC ((uint)0x00000000)
243
244	#define SCC_TODR_TOD ((ushort)0x8000)
245
246	/* SCC Event and Mask register.
247	*/
248	#define SCCM_TXE ((unsigned char)0x10)
249	#define SCCM_BSY ((unsigned char)0x04)
250	#define SCCM_TX ((unsigned char)0x02)
251	#define SCCM_RX ((unsigned char)0x01)
252
253	typedef struct scc_param {
254	ushort scc_rbase; /* Rx Buffer descriptor base address */
255	ushort scc_tbase; /* Tx Buffer descriptor base address */
256	u_char scc_rfcr; /* Rx function code */
257	u_char scc_tfcr; /* Tx function code */
258	ushort scc_mrblr; /* Max receive buffer length */
259	uint scc_rstate; /* Internal */
260	uint scc_idp; /* Internal */
261	ushort scc_rbptr; /* Internal */
262	ushort scc_ibc; /* Internal */
263	uint scc_rxtmp; /* Internal */
264	uint scc_tstate; /* Internal */
265	uint scc_tdp; /* Internal */
266	ushort scc_tbptr; /* Internal */
267	ushort scc_tbc; /* Internal */
268	uint scc_txtmp; /* Internal */
269	uint scc_rcrc; /* Internal */
270	uint scc_tcrc; /* Internal */
271	} sccp_t;
272
273	/* Function code bits.
274	*/
275	#define SCC_EB ((u_char)0x10) /* Set big endian byte order */
276
277	/* CPM Ethernet through SCC1.
278	*/
279	typedef struct scc_enet {
280	sccp_t sen_genscc;
281	uint sen_cpres; /* Preset CRC */
282	uint sen_cmask; /* Constant mask for CRC */
283	uint sen_crcec; /* CRC Error counter */
284	uint sen_alec; /* alignment error counter */
285	uint sen_disfc; /* discard frame counter */
286	ushort sen_pads; /* Tx short frame pad character */
287	ushort sen_retlim; /* Retry limit threshold */
288	ushort sen_retcnt; /* Retry limit counter */
289	ushort sen_maxflr; /* maximum frame length register */
290	ushort sen_minflr; /* minimum frame length register */
291	ushort sen_maxd1; /* maximum DMA1 length */
292	ushort sen_maxd2; /* maximum DMA2 length */
293	ushort sen_maxd; /* Rx max DMA */
294	ushort sen_dmacnt; /* Rx DMA counter */
295	ushort sen_maxb; /* Max BD byte count */
296	ushort sen_gaddr1; /* Group address filter */
297	ushort sen_gaddr2;
298	ushort sen_gaddr3;
299	ushort sen_gaddr4;
300	uint sen_tbuf0data0; /* Save area 0 - current frame */
301	uint sen_tbuf0data1; /* Save area 1 - current frame */
302	uint sen_tbuf0rba; /* Internal */
303	uint sen_tbuf0crc; /* Internal */
304	ushort sen_tbuf0bcnt; /* Internal */
305	ushort sen_paddrh; /* physical address (MSB) */
306	ushort sen_paddrm;
307	ushort sen_paddrl; /* physical address (LSB) */
308	ushort sen_pper; /* persistence */
309	ushort sen_rfbdptr; /* Rx first BD pointer */
310	ushort sen_tfbdptr; /* Tx first BD pointer */
311	ushort sen_tlbdptr; /* Tx last BD pointer */
312	uint sen_tbuf1data0; /* Save area 0 - current frame */
313	uint sen_tbuf1data1; /* Save area 1 - current frame */
314	uint sen_tbuf1rba; /* Internal */
315	uint sen_tbuf1crc; /* Internal */
316	ushort sen_tbuf1bcnt; /* Internal */
317	ushort sen_txlen; /* Tx Frame length counter */
318	ushort sen_iaddr1; /* Individual address filter */
319	ushort sen_iaddr2;
320	ushort sen_iaddr3;
321	ushort sen_iaddr4;
322	ushort sen_boffcnt; /* Backoff counter */
323
324	/* NOTE: Some versions of the manual have the following items
325	* incorrectly documented. Below is the proper order.
326	*/
327	ushort sen_taddrh; /* temp address (MSB) */
328	ushort sen_taddrm;
329	ushort sen_taddrl; /* temp address (LSB) */
330	} scc_enet_t;
331
332	/* Bits in parallel I/O port registers that have to be set/cleared
333	* to configure the pins for SCC1 use. The TCLK and RCLK seem unique
334	* to the MBX860 board. Any two of the four available clocks could be
335	* used, and the MPC860 cookbook manual has an example using different
336	* clock pins.
337	*/
338	#define PA_ENET_RXD ((ushort)0x0001)
339	#define PA_ENET_TXD ((ushort)0x0002)
340	#define PA_ENET_TCLK ((ushort)0x0200)
341	#define PA_ENET_RCLK ((ushort)0x0800)
342	#define PC_ENET_TENA ((ushort)0x0001)
343	#define PC_ENET_CLSN ((ushort)0x0010)
344	#define PC_ENET_RENA ((ushort)0x0020)
345
346	/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to
347	* SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
348	*/
349	#define SICR_ENET_MASK ((uint)0x000000ff)
350	#define SICR_ENET_CLKRT ((uint)0x0000003d)
351
352	/* SCC Event register as used by Ethernet.
353	*/
354	#define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */
355	#define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */
356	#define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */
357	#define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */
358	#define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */
359	#define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */
360
361	/* SCC Mode Register (PMSR) as used by Ethernet.
362	*/
363	#define SCC_PMSR_HBC ((ushort)0x8000) /* Enable heartbeat */
364	#define SCC_PMSR_FC ((ushort)0x4000) /* Force collision */
365	#define SCC_PMSR_RSH ((ushort)0x2000) /* Receive short frames */
366	#define SCC_PMSR_IAM ((ushort)0x1000) /* Check individual hash */
367	#define SCC_PMSR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */
368	#define SCC_PMSR_PRO ((ushort)0x0200) /* Promiscuous mode */
369	#define SCC_PMSR_BRO ((ushort)0x0100) /* Catch broadcast pkts */
370	#define SCC_PMSR_SBT ((ushort)0x0080) /* Special backoff timer */
371	#define SCC_PMSR_LPB ((ushort)0x0040) /* Set Loopback mode */
372	#define SCC_PMSR_SIP ((ushort)0x0020) /* Sample Input Pins */
373	#define SCC_PMSR_LCW ((ushort)0x0010) /* Late collision window */
374	#define SCC_PMSR_NIB22 ((ushort)0x000a) /* Start frame search */
375	#define SCC_PMSR_FDE ((ushort)0x0001) /* Full duplex enable */
376
377	/* Buffer descriptor control/status used by Ethernet receive.
378	*/
379	#define BD_ENET_RX_EMPTY ((ushort)0x8000)
380	#define BD_ENET_RX_WRAP ((ushort)0x2000)
381	#define BD_ENET_RX_INTR ((ushort)0x1000)
382	#define BD_ENET_RX_LAST ((ushort)0x0800)
383	#define BD_ENET_RX_FIRST ((ushort)0x0400)
384	#define BD_ENET_RX_MISS ((ushort)0x0100)
385	#define BD_ENET_RX_LG ((ushort)0x0020)
386	#define BD_ENET_RX_NO ((ushort)0x0010)
387	#define BD_ENET_RX_SH ((ushort)0x0008)
388	#define BD_ENET_RX_CR ((ushort)0x0004)
389	#define BD_ENET_RX_OV ((ushort)0x0002)
390	#define BD_ENET_RX_CL ((ushort)0x0001)
391	#define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */
392
393	/* Buffer descriptor control/status used by Ethernet transmit.
394	*/
395	#define BD_ENET_TX_READY ((ushort)0x8000)
396	#define BD_ENET_TX_PAD ((ushort)0x4000)
397	#define BD_ENET_TX_WRAP ((ushort)0x2000)
398	#define BD_ENET_TX_INTR ((ushort)0x1000)
399	#define BD_ENET_TX_LAST ((ushort)0x0800)
400	#define BD_ENET_TX_TC ((ushort)0x0400)
401	#define BD_ENET_TX_DEF ((ushort)0x0200)
402	#define BD_ENET_TX_HB ((ushort)0x0100)
403	#define BD_ENET_TX_LC ((ushort)0x0080)
404	#define BD_ENET_TX_RL ((ushort)0x0040)
405	#define BD_ENET_TX_RCMASK ((ushort)0x003c)
406	#define BD_ENET_TX_UN ((ushort)0x0002)
407	#define BD_ENET_TX_CSL ((ushort)0x0001)
408	#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */
409
410	/* SCC as UART
411	*/
412	typedef struct scc_uart {
413	sccp_t scc_genscc;
414	uint scc_res1; /* Reserved */
415	uint scc_res2; /* Reserved */
416	ushort scc_maxidl; /* Maximum idle chars */
417	ushort scc_idlc; /* temp idle counter */
418	ushort scc_brkcr; /* Break count register */
419	ushort scc_parec; /* receive parity error counter */
420	ushort scc_frmec; /* receive framing error counter */
421	ushort scc_nosec; /* receive noise counter */
422	ushort scc_brkec; /* receive break condition counter */
423	ushort scc_brkln; /* last received break length */
424	ushort scc_uaddr1; /* UART address character 1 */
425	ushort scc_uaddr2; /* UART address character 2 */
426	ushort scc_rtemp; /* Temp storage */
427	ushort scc_toseq; /* Transmit out of sequence char */
428	ushort scc_char1; /* control character 1 */
429	ushort scc_char2; /* control character 2 */
430	ushort scc_char3; /* control character 3 */
431	ushort scc_char4; /* control character 4 */
432	ushort scc_char5; /* control character 5 */
433	ushort scc_char6; /* control character 6 */
434	ushort scc_char7; /* control character 7 */
435	ushort scc_char8; /* control character 8 */
436	ushort scc_rccm; /* receive control character mask */
437	ushort scc_rccr; /* receive control character register */
438	ushort scc_rlbc; /* receive last break character */
439	} scc_uart_t;
440
441	/* SCC Event and Mask registers when it is used as a UART.
442	*/
443	#define UART_SCCM_GLR ((ushort)0x1000)
444	#define UART_SCCM_GLT ((ushort)0x0800)
445	#define UART_SCCM_AB ((ushort)0x0200)
446	#define UART_SCCM_IDL ((ushort)0x0100)
447	#define UART_SCCM_GRA ((ushort)0x0080)
448	#define UART_SCCM_BRKE ((ushort)0x0040)
449	#define UART_SCCM_BRKS ((ushort)0x0020)
450	#define UART_SCCM_CCR ((ushort)0x0008)
451	#define UART_SCCM_BSY ((ushort)0x0004)
452	#define UART_SCCM_TX ((ushort)0x0002)
453	#define UART_SCCM_RX ((ushort)0x0001)
454
455	/* The SCC PMSR when used as a UART.
456	*/
457	#define SCU_PMSR_FLC ((ushort)0x8000)
458	#define SCU_PMSR_SL ((ushort)0x4000)
459	#define SCU_PMSR_CL ((ushort)0x3000)
460	#define SCU_PMSR_UM ((ushort)0x0c00)
461	#define SCU_PMSR_FRZ ((ushort)0x0200)
462	#define SCU_PMSR_RZS ((ushort)0x0100)
463	#define SCU_PMSR_SYN ((ushort)0x0080)
464	#define SCU_PMSR_DRT ((ushort)0x0040)
465	#define SCU_PMSR_PEN ((ushort)0x0010)
466	#define SCU_PMSR_RPM ((ushort)0x000c)
467	#define SCU_PMSR_REVP ((ushort)0x0008)
468	#define SCU_PMSR_TPM ((ushort)0x0003)
469	#define SCU_PMSR_TEVP ((ushort)0x0003)
470
471	/* CPM Transparent mode SCC.
472	*/
473	typedef struct scc_trans {
474	sccp_t st_genscc;
475	uint st_cpres; /* Preset CRC */
476	uint st_cmask; /* Constant mask for CRC */
477	} scc_trans_t;
478
479	/* CPM interrupts. There are nearly 32 interrupts generated by CPM
480	* channels or devices. All of these are presented to the PPC core
481	* as a single interrupt. The CPM interrupt handler dispatches its
482	* own handlers, in a similar fashion to the PPC core handler. We
483	* use the table as defined in the manuals (i.e. no special high
484	* priority and SCC1 == SCCa, etc...).
485	*/
486	#define CPMVEC_NR 32
487	#define CPMVEC_PIO_PC15 ((ushort)0x1f)
488	#define CPMVEC_SCC1 ((ushort)0x1e)
489	#define CPMVEC_SCC2 ((ushort)0x1d)
490	#define CPMVEC_SCC3 ((ushort)0x1c)
491	#define CPMVEC_SCC4 ((ushort)0x1b)
492	#define CPMVEC_PIO_PC14 ((ushort)0x1a)
493	#define CPMVEC_TIMER1 ((ushort)0x19)
494	#define CPMVEC_PIO_PC13 ((ushort)0x18)
495	#define CPMVEC_PIO_PC12 ((ushort)0x17)
496	#define CPMVEC_SDMA_CB_ERR ((ushort)0x16)
497	#define CPMVEC_IDMA1 ((ushort)0x15)
498	#define CPMVEC_IDMA2 ((ushort)0x14)
499	#define CPMVEC_TIMER2 ((ushort)0x12)
500	#define CPMVEC_RISCTIMER ((ushort)0x11)
501	#define CPMVEC_I2C ((ushort)0x10)
502	#define CPMVEC_PIO_PC11 ((ushort)0x0f)
503	#define CPMVEC_PIO_PC10 ((ushort)0x0e)
504	#define CPMVEC_TIMER3 ((ushort)0x0c)
505	#define CPMVEC_PIO_PC9 ((ushort)0x0b)
506	#define CPMVEC_PIO_PC8 ((ushort)0x0a)
507	#define CPMVEC_PIO_PC7 ((ushort)0x09)
508	#define CPMVEC_TIMER4 ((ushort)0x07)
509	#define CPMVEC_PIO_PC6 ((ushort)0x06)
510	#define CPMVEC_SPI ((ushort)0x05)
511	#define CPMVEC_SMC1 ((ushort)0x04)
512	#define CPMVEC_SMC2 ((ushort)0x03)
513	#define CPMVEC_PIO_PC5 ((ushort)0x02)
514	#define CPMVEC_PIO_PC4 ((ushort)0x01)
515	#define CPMVEC_ERROR ((ushort)0x00)
516
517	extern void cpm_install_handler(int vec, void (handler)(void ), void *dev_id);
518
519	/* CPM interrupt configuration vector.
520	*/
521	#define CICR_SCD_SCC4 ((uint)0x00c00000) /* SCC4 @ SCCd */
522	#define CICR_SCC_SCC3 ((uint)0x00200000) /* SCC3 @ SCCc */
523	#define CICR_SCB_SCC2 ((uint)0x00040000) /* SCC2 @ SCCb */
524	#define CICR_SCA_SCC1 ((uint)0x00000000) /* SCC1 @ SCCa */
525	#define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrrupt */
526	#define CICR_HP_MASK ((uint)0x00001f00) /* Hi-pri int. */
527	#define CICR_IEN ((uint)0x00000080) /* Int. enable */
528	#define CICR_SPS ((uint)0x00000001) /* SCC Spread */
529	#endif /* __CPM_8XX__ */

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