1 | /* |
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2 | * This routine starts the application. It includes application, |
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3 | * board, and monitor specific initialization and configuration. |
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4 | * The generic CPU dependent initialization has been performed |
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5 | * before this routine is invoked. |
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6 | * |
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7 | * COPYRIGHT (c) 1989-2007. |
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8 | * On-Line Applications Research Corporation (OAR). |
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9 | * |
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10 | * The license and distribution terms for this file may be |
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11 | * found in the file LICENSE in this distribution or at |
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12 | * http://www.rtems.com/license/LICENSE. |
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13 | * |
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14 | * $Id$ |
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15 | */ |
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16 | |
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17 | #include <string.h> |
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18 | |
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19 | #include <rtems/libio.h> |
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20 | #include <rtems/libcsupport.h> |
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21 | #include <bsp/consoleIo.h> |
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22 | #include <libcpu/spr.h> |
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23 | #include <bsp/residual.h> |
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24 | #include <bsp/pci.h> |
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25 | #include <bsp/openpic.h> |
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26 | #include <bsp/irq.h> |
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27 | #include <bsp/VME.h> |
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28 | #include <bsp.h> |
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29 | #include <libcpu/bat.h> |
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30 | #include <libcpu/pte121.h> |
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31 | #include <libcpu/cpuIdent.h> |
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32 | #include <bsp/vectors.h> |
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33 | #include <rtems/powerpc/powerpc.h> |
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34 | |
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35 | extern unsigned long __rtems_end[]; |
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36 | extern void L1_caches_enables(); |
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37 | extern unsigned get_L2CR(); |
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38 | extern void set_L2CR(unsigned); |
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39 | extern void bsp_cleanup(void); |
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40 | extern Triv121PgTbl BSP_pgtbl_setup(); |
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41 | extern void BSP_pgtbl_activate(); |
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42 | extern void BSP_vme_config(); |
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43 | extern void ShowBATS(); |
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44 | unsigned int rsPMCQ1Init(); |
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45 | |
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46 | uint32_t bsp_clicks_per_usec; |
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47 | |
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48 | SPR_RW(SPRG0) |
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49 | SPR_RW(SPRG1) |
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50 | |
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51 | uint8_t LightIdx = 0; |
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52 | |
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53 | void BSP_Increment_Light(){ |
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54 | uint8_t data; |
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55 | data = *GENERAL_REGISTER1; |
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56 | data &= 0xf0; |
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57 | data |= LightIdx++; |
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58 | *GENERAL_REGISTER1 = data; |
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59 | } |
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60 | |
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61 | void BSP_Fatal_Fault_Light() { |
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62 | uint8_t data; |
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63 | data = *GENERAL_REGISTER1; |
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64 | data &= 0xf0; |
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65 | data |= 0x7; |
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66 | while(1) |
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67 | *GENERAL_REGISTER1 = data; |
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68 | } |
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69 | |
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70 | void write_to_Q2ram(int offset, unsigned int data ) |
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71 | { |
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72 | printk("0x%x ==> %d\n", offset, data ); |
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73 | #if 0 |
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74 | unsigned int *ptr = 0x82000000; |
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75 | ptr += offset; |
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76 | *ptr = data; |
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77 | #endif |
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78 | } |
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79 | |
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80 | /* |
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81 | * Vital Board data Start using DATA RESIDUAL |
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82 | */ |
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83 | |
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84 | uint32_t VME_Slot1 = FALSE; |
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85 | |
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86 | /* |
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87 | * Total memory. |
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88 | * Note: RAM_END is defined in linkcmds. We want to verify that the application |
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89 | * is only using 10M of memory, and we do this by only accounting for this |
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90 | * much memory. |
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91 | */ |
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92 | extern int RAM_END; |
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93 | unsigned int BSP_mem_size = (unsigned int)&RAM_END; |
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94 | |
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95 | /* |
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96 | * PCI Bus Frequency |
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97 | */ |
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98 | unsigned int BSP_bus_frequency; |
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99 | |
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100 | /* |
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101 | * processor clock frequency |
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102 | */ |
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103 | unsigned int BSP_processor_frequency; |
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104 | |
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105 | /* |
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106 | * Time base divisior (how many tick for 1 second). |
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107 | */ |
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108 | unsigned int BSP_time_base_divisor = 1000; /* XXX - Just a guess */ |
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109 | |
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110 | /* |
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111 | * system init stack and soft ir stack size |
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112 | */ |
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113 | #define INIT_STACK_SIZE 0x1000 |
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114 | #define INTR_STACK_SIZE CONFIGURE_INTERRUPT_STACK_MEMORY |
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115 | |
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116 | void BSP_panic(char *s) |
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117 | { |
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118 | printk("%s PANIC %s\n",_RTEMS_version, s); |
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119 | __asm__ __volatile ("sc"); |
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120 | } |
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121 | |
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122 | void _BSP_Fatal_error(unsigned int v) |
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123 | { |
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124 | printk("%s PANIC ERROR %x\n",_RTEMS_version, v); |
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125 | __asm__ __volatile ("sc"); |
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126 | } |
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127 | |
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128 | /* |
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129 | * The original table from the application and our copy of it with |
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130 | * some changes. |
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131 | */ |
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132 | |
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133 | extern rtems_configuration_table Configuration; |
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134 | |
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135 | rtems_configuration_table BSP_Configuration; |
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136 | |
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137 | rtems_cpu_table Cpu_table; |
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138 | |
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139 | char *rtems_progname; |
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140 | |
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141 | int BSP_FLASH_Disable_writes( |
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142 | uint32_t area |
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143 | ) |
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144 | { |
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145 | unsigned char data; |
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146 | |
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147 | data = *GENERAL_REGISTER1; |
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148 | data |= DISABLE_USER_FLASH; |
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149 | *GENERAL_REGISTER1 = data; |
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150 | |
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151 | return RTEMS_SUCCESSFUL; |
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152 | } |
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153 | |
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154 | int BSP_FLASH_Enable_writes( |
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155 | uint32_t area /* IN */ |
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156 | ) |
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157 | { |
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158 | unsigned char data; |
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159 | |
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160 | data = *GENERAL_REGISTER1; |
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161 | data &= (~DISABLE_USER_FLASH); |
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162 | *GENERAL_REGISTER1 = data; |
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163 | |
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164 | return RTEMS_SUCCESSFUL; |
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165 | } |
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166 | |
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167 | void BSP_FLASH_set_page( |
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168 | uint8_t page |
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169 | ) |
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170 | { |
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171 | unsigned char data; |
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172 | |
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173 | /* Set the flash page register. */ |
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174 | data = *GENERAL_REGISTER2; |
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175 | data &= ~(BSP_FLASH_PAGE_MASK); |
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176 | data |= 0x80 | (page << BSP_FLASH_PAGE_SHIFT); |
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177 | *GENERAL_REGISTER2 = data; |
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178 | } |
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179 | |
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180 | /* |
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181 | * Use the shared implementations of the following routines |
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182 | */ |
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183 | |
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184 | void bsp_postdriver_hook(void); |
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185 | void bsp_libc_init( void *, uint32_t, int ); |
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186 | |
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187 | /* |
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188 | * Function: bsp_pretasking_hook |
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189 | * Created: 95/03/10 |
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190 | * |
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191 | * Description: |
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192 | * BSP pretasking hook. Called just before drivers are initialized. |
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193 | * Used to setup libc and install any BSP extensions. |
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194 | * |
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195 | * NOTES: |
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196 | * Must not use libc (to do io) from here, since drivers are |
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197 | * not yet initialized. |
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198 | * |
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199 | */ |
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200 | |
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201 | void bsp_pretasking_hook(void) |
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202 | { |
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203 | uint32_t heap_start; |
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204 | uint32_t heap_size; |
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205 | uint32_t heap_sbrk_spared; |
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206 | |
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207 | extern uint32_t _bsp_sbrk_init(uint32_t, uint32_t*); |
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208 | |
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209 | heap_start = ((uint32_t) __rtems_end) +INIT_STACK_SIZE + INTR_STACK_SIZE; |
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210 | if (heap_start & (CPU_ALIGNMENT-1)) |
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211 | heap_start = (heap_start + CPU_ALIGNMENT) & ~(CPU_ALIGNMENT-1); |
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212 | |
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213 | heap_size = (BSP_mem_size - heap_start) - BSP_Configuration.work_space_size; |
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214 | |
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215 | heap_sbrk_spared=_bsp_sbrk_init(heap_start, &heap_size); |
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216 | |
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217 | #ifdef SHOW_MORE_INIT_SETTINGS |
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218 | printk(" HEAP start %x size %x (%x bytes spared for sbrk)\n", |
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219 | heap_start, heap_size, heap_sbrk_spared); |
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220 | #endif |
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221 | |
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222 | bsp_libc_init((void *) 0, heap_size, heap_sbrk_spared); |
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223 | rsPMCQ1Init(); |
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224 | |
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225 | #ifdef RTEMS_DEBUG |
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226 | rtems_debug_enable( RTEMS_DEBUG_ALL_MASK ); |
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227 | #endif |
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228 | } |
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229 | |
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230 | void zero_bss() |
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231 | { |
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232 | /* prevent these from being accessed in the short data areas */ |
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233 | extern unsigned long __bss_start[], __SBSS_START__[], __SBSS_END__[]; |
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234 | extern unsigned long __SBSS2_START__[], __SBSS2_END__[]; |
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235 | memset(__SBSS_START__, 0, ((unsigned) __SBSS_END__) - ((unsigned)__SBSS_START__)); |
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236 | memset(__SBSS2_START__, 0, ((unsigned) __SBSS2_END__) - ((unsigned)__SBSS2_START__)); |
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237 | memset(__bss_start, 0, ((unsigned) __rtems_end) - ((unsigned)__bss_start)); |
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238 | } |
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239 | |
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240 | void save_boot_params(RESIDUAL* r3, void *r4, void* r5, char *additional_boot_options) |
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241 | { |
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242 | #if 0 |
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243 | residualCopy = *r3; |
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244 | strncpy(loaderParam, additional_boot_options, MAX_LOADER_ADD_PARM); |
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245 | loaderParam[MAX_LOADER_ADD_PARM - 1] ='\0'; |
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246 | #endif |
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247 | } |
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248 | |
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249 | unsigned int EUMBBAR; |
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250 | |
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251 | unsigned int get_eumbbar() { |
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252 | register int a, e; |
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253 | |
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254 | asm volatile( "lis %0,0xfec0; ori %0,%0,0x0000": "=r" (a) ); |
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255 | asm volatile("sync"); |
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256 | |
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257 | asm volatile("lis %0,0x8000; ori %0,%0,0x0078": "=r"(e) ); |
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258 | asm volatile("stwbrx %0,0x0,%1": "=r"(e): "r"(a)); |
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259 | asm volatile("sync"); |
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260 | |
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261 | asm volatile("lis %0,0xfee0; ori %0,%0,0x0000": "=r" (a) ); |
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262 | asm volatile("sync"); |
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263 | |
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264 | asm volatile("lwbrx %0,0x0,%1": "=r" (e): "r" (a)); |
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265 | asm volatile("isync"); |
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266 | return e; |
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267 | } |
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268 | |
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269 | void Read_ep1a_config_registers( ppc_cpu_id_t myCpu ) { |
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270 | unsigned char value; |
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271 | |
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272 | /* |
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273 | * Print out the board and revision. |
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274 | */ |
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275 | |
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276 | printk("Board: "); |
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277 | printk( get_ppc_cpu_type_name(myCpu) ); |
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278 | |
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279 | value = *BOARD_REVISION_REGISTER2 & HARDWARE_ID_MASK; |
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280 | if ( value == HARDWARE_ID_PPC5_EP1A ) |
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281 | printk(" EP1A "); |
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282 | else if ( value == HARDWARE_ID_EP1B ) |
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283 | printk(" EP1B "); |
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284 | else |
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285 | printk(" Unknown "); |
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286 | |
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287 | value = *BOARD_REVISION_REGISTER2&0x1; |
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288 | printk("Board ID %08x", value); |
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289 | if(value == 0x0){ |
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290 | VME_Slot1 = TRUE; |
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291 | printk("VME Slot 1\n"); |
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292 | } |
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293 | else{ |
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294 | VME_Slot1 = FALSE; |
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295 | printk("\n"); |
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296 | } |
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297 | |
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298 | printk("Revision: "); |
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299 | value = *BOARD_REVISION_REGISTER1; |
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300 | printk("%d%c\n\n", value>>4, 'A'+(value&BUILD_REVISION_MASK) ); |
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301 | |
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302 | /* |
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303 | * Get the CPU, XXX frequency |
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304 | */ |
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305 | value = *EQUIPMENT_PRESENT_REGISTER2 & PLL_CFG_MASK; |
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306 | switch( value ) { |
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307 | case MHZ_33_66_200: /* PCI, MEM, & CPU Frequency */ |
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308 | BSP_processor_frequency = 200000000; |
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309 | BSP_bus_frequency = 33000000; |
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310 | break; |
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311 | case MHZ_33_100_200: /* PCI, MEM, & CPU Frequency */ |
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312 | BSP_processor_frequency = 200000000; |
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313 | BSP_bus_frequency = 33000000; |
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314 | break; |
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315 | case MHZ_33_66_266: /* PCI, MEM, & CPU Frequency */ |
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316 | BSP_processor_frequency = 266000000; |
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317 | BSP_bus_frequency = 33000000; |
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318 | break; |
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319 | case MHZ_33_66_333: /* PCI, MEM, & CPU Frequency */ |
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320 | BSP_processor_frequency = 333000000; |
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321 | BSP_bus_frequency = 33000000; |
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322 | break; |
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323 | case MHZ_33_100_333: /* PCI, MEM, & CPU Frequency */ |
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324 | BSP_processor_frequency = 333000000; |
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325 | BSP_bus_frequency = 33000000; |
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326 | break; |
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327 | case MHZ_33_100_350: /* PCI, MEM, & CPU Frequency */ |
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328 | BSP_processor_frequency = 350000000; |
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329 | BSP_bus_frequency = 33000000; |
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330 | break; |
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331 | default: |
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332 | printk("ERROR: Unknown Processor frequency 0x%02x please fill in bspstart.c\n",value); |
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333 | BSP_processor_frequency = 350000000; |
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334 | BSP_bus_frequency = 33000000; |
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335 | break; |
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336 | } |
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337 | } |
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338 | |
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339 | /* |
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340 | * bsp_start |
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341 | * |
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342 | * This routine does the bulk of the system initialization. |
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343 | */ |
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344 | |
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345 | void bsp_start( void ) |
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346 | { |
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347 | unsigned char *stack; |
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348 | register uint32_t intrStack; |
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349 | register uint32_t *intrStackPtr; |
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350 | unsigned char *work_space_start; |
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351 | ppc_cpu_id_t myCpu; |
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352 | ppc_cpu_revision_t myCpuRevision; |
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353 | Triv121PgTbl pt=0; /* R = e; */ |
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354 | |
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355 | /* |
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356 | * Get CPU identification dynamically. Note that the get_ppc_cpu_type() function |
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357 | * store the result in global variables so that it can be used latter... |
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358 | */ |
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359 | BSP_Increment_Light(); |
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360 | myCpu = get_ppc_cpu_type(); |
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361 | myCpuRevision = get_ppc_cpu_revision(); |
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362 | |
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363 | EUMBBAR = get_eumbbar(); |
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364 | printk("EUMBBAR 0x%08x\n", EUMBBAR ); |
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365 | |
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366 | /* |
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367 | * Note this sets BSP_processor_frequency based upon register settings. |
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368 | * It must be done prior to setting up hooks. |
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369 | */ |
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370 | Read_ep1a_config_registers( myCpu ); |
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371 | |
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372 | /* |
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373 | * Set up our hooks |
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374 | * Make sure libc_init is done before drivers initialized so that |
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375 | * they can use atexit() |
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376 | */ |
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377 | |
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378 | Cpu_table.pretasking_hook = bsp_pretasking_hook; /* init libc, etc. */ |
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379 | Cpu_table.postdriver_hook = bsp_postdriver_hook; |
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380 | Cpu_table.interrupt_stack_size = CONFIGURE_INTERRUPT_STACK_MEMORY; |
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381 | |
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382 | bsp_clicks_per_usec = BSP_processor_frequency/(BSP_time_base_divisor * 1000); |
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383 | |
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384 | ShowBATS(); |
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385 | #if 0 /* XXX - Add back in cache enable when we get this up and running!! */ |
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386 | /* |
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387 | * enables L1 Cache. Note that the L1_caches_enables() codes checks for |
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388 | * relevant CPU type so that the reason why there is no use of myCpu... |
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389 | */ |
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390 | L1_caches_enables(); |
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391 | #endif |
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392 | |
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393 | /* |
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394 | * the initial stack has aready been set to this value in start.S |
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395 | * so there is no need to set it in r1 again... It is just for info |
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396 | * so that It can be printed without accessing R1. |
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397 | */ |
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398 | stack = ((unsigned char*) __rtems_end) + INIT_STACK_SIZE - PPC_MINIMUM_STACK_FRAME_SIZE; |
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399 | |
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400 | /* tag the bottom (T. Straumann 6/36/2001 <strauman@slac.stanford.edu>) */ |
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401 | *((uint32_t *)stack) = 0; |
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402 | |
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403 | /* |
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404 | * Initialize the interrupt related settings |
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405 | * SPRG1 = software managed IRQ stack |
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406 | * |
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407 | * This could be done latter (e.g in IRQ_INIT) but it helps to understand |
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408 | * some settings below... |
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409 | */ |
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410 | intrStack = ((uint32_t) __rtems_end) + |
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411 | INIT_STACK_SIZE + INTR_STACK_SIZE - PPC_MINIMUM_STACK_FRAME_SIZE; |
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412 | |
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413 | /* make sure it's properly aligned */ |
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414 | intrStack &= ~(CPU_STACK_ALIGNMENT-1); |
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415 | |
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416 | /* tag the bottom (T. Straumann 6/36/2001 <strauman@slac.stanford.edu>) */ |
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417 | intrStackPtr = (uint32_t*) intrStack; |
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418 | *intrStackPtr = 0; |
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419 | |
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420 | _write_SPRG1((unsigned int)intrStack); |
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421 | |
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422 | /* signal them that we have fixed PR288 - eventually, this should go away */ |
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423 | _write_SPRG0(PPC_BSP_HAS_FIXED_PR288); |
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424 | |
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425 | /* |
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426 | * Initialize default raw exception hanlders. See vectors/vectors_init.c |
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427 | */ |
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428 | initialize_exceptions(); |
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429 | |
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430 | /* |
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431 | * Init MMU block address translation to enable hardware |
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432 | * access |
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433 | */ |
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434 | setdbat(1, 0xf0000000, 0xf0000000, 0x10000000, IO_PAGE); |
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435 | setdbat(3, 0x90000000, 0x90000000, 0x10000000, IO_PAGE); |
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436 | |
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437 | |
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438 | #ifdef SHOW_MORE_INIT_SETTINGS |
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439 | printk("Going to start PCI buses scanning and initialization\n"); |
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440 | #endif |
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441 | pci_initialize(); |
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442 | |
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443 | #ifdef SHOW_MORE_INIT_SETTINGS |
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444 | printk("Number of PCI buses found is : %d\n", pci_bus_count()); |
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445 | #endif |
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446 | #ifdef TEST_RAW_EXCEPTION_CODE |
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447 | printk("Testing exception handling Part 1\n"); |
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448 | |
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449 | /* |
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450 | * Cause a software exception |
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451 | */ |
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452 | __asm__ __volatile ("sc"); |
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453 | |
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454 | /* |
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455 | * Check we can still catch exceptions and returned coorectly. |
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456 | */ |
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457 | printk("Testing exception handling Part 2\n"); |
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458 | __asm__ __volatile ("sc"); |
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459 | #endif |
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460 | |
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461 | #ifdef SHOW_MORE_INIT_SETTINGS |
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462 | printk("BSP_Configuration.work_space_size = %x\n", BSP_Configuration.work_space_size); |
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463 | #endif |
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464 | work_space_start = |
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465 | (unsigned char *)BSP_mem_size - BSP_Configuration.work_space_size; |
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466 | |
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467 | if ( work_space_start <= ((unsigned char *)__rtems_end) + INIT_STACK_SIZE + INTR_STACK_SIZE) { |
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468 | printk( "bspstart: Not enough RAM!!!\n" ); |
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469 | bsp_cleanup(); |
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470 | } |
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471 | |
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472 | BSP_Configuration.work_space_start = work_space_start; |
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473 | |
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474 | /* |
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475 | * Initalize RTEMS IRQ system |
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476 | */ |
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477 | BSP_rtems_irq_mng_init(0); |
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478 | |
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479 | /* Activate the page table mappings only after |
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480 | * initializing interrupts because the irq_mng_init() |
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481 | * routine needs to modify the text |
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482 | */ |
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483 | if (pt) { |
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484 | #ifdef SHOW_MORE_INIT_SETTINGS |
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485 | printk("Page table setup finished; will activate it NOW...\n"); |
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486 | #endif |
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487 | BSP_pgtbl_activate(pt); |
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488 | } |
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489 | |
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490 | /* |
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491 | * Initialize VME bridge - needs working PCI |
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492 | * and IRQ subsystems... |
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493 | */ |
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494 | #ifdef SHOW_MORE_INIT_SETTINGS |
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495 | printk("Going to initialize VME bridge\n"); |
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496 | #endif |
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497 | /* VME initialization is in a separate file so apps which don't use |
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498 | * VME or want a different configuration may link against a customized |
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499 | * routine. |
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500 | */ |
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501 | BSP_vme_config(); |
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502 | |
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503 | #ifdef SHOW_MORE_INIT_SETTINGS |
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504 | ShowBATS(); |
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505 | printk("Exit from bspstart\n"); |
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506 | #endif |
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507 | } |
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