1 | /* |
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2 | * This routine starts the application. It includes application, |
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3 | * board, and monitor specific initialization and configuration. |
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4 | * The generic CPU dependent initialization has been performed |
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5 | * before this routine is invoked. |
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6 | * |
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7 | * COPYRIGHT (c) 1989-2007. |
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8 | * On-Line Applications Research Corporation (OAR). |
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9 | * |
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10 | * The license and distribution terms for this file may be |
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11 | * found in the file LICENSE in this distribution or at |
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12 | * http://www.rtems.org/license/LICENSE. |
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13 | */ |
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14 | |
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15 | #warning The interrupt disable mask is now stored in SPRG0, please verify that this is compatible to this BSP (see also bootcard.c). |
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16 | |
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17 | #include <bsp/consoleIo.h> |
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18 | #include <libcpu/spr.h> |
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19 | #include <bsp/residual.h> |
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20 | #include <bsp/pci.h> |
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21 | #include <bsp/openpic.h> |
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22 | #include <bsp/irq.h> |
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23 | #include <bsp/VME.h> |
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24 | #include <bsp.h> |
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25 | #include <libcpu/bat.h> |
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26 | #include <libcpu/pte121.h> |
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27 | #include <libcpu/cpuIdent.h> |
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28 | #include <bsp/vectors.h> |
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29 | #include <rtems/powerpc/powerpc.h> |
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30 | #include <rtems/counter.h> |
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31 | |
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32 | extern unsigned long __bss_start[], __SBSS_START__[], __SBSS_END__[]; |
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33 | extern unsigned long __SBSS2_START__[], __SBSS2_END__[]; |
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34 | |
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35 | extern unsigned long __rtems_end[]; |
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36 | extern void L1_caches_enables(void); |
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37 | extern unsigned get_L2CR(void); |
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38 | extern void set_L2CR(unsigned); |
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39 | extern Triv121PgTbl BSP_pgtbl_setup(void); |
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40 | extern void BSP_pgtbl_activate(Triv121PgTbl); |
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41 | extern void BSP_vme_config(void); |
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42 | extern void ShowBATS(void); |
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43 | unsigned int rsPMCQ1Init(void); |
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44 | |
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45 | uint32_t bsp_clicks_per_usec; |
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46 | |
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47 | SPR_RW(SPRG1) |
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48 | |
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49 | uint8_t LightIdx = 0; |
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50 | |
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51 | extern int RAM_END; |
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52 | unsigned int BSP_mem_size = (unsigned int)&RAM_END; |
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53 | |
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54 | void BSP_Increment_Light(void){ |
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55 | uint8_t data; |
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56 | data = *GENERAL_REGISTER1; |
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57 | data &= 0xf0; |
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58 | data |= LightIdx++; |
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59 | *GENERAL_REGISTER1 = data; |
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60 | } |
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61 | |
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62 | void BSP_Fatal_Fault_Light(void) { |
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63 | uint8_t data; |
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64 | data = *GENERAL_REGISTER1; |
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65 | data &= 0xf0; |
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66 | data |= 0x7; |
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67 | while(1) |
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68 | *GENERAL_REGISTER1 = data; |
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69 | } |
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70 | |
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71 | void write_to_Q2ram(int offset, unsigned int data ) |
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72 | { |
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73 | printk("0x%x ==> %d\n", offset, data ); |
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74 | #if 0 |
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75 | unsigned int *ptr = 0x82000000; |
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76 | ptr += offset; |
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77 | *ptr = data; |
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78 | #endif |
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79 | } |
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80 | |
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81 | /* |
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82 | * Vital Board data Start using DATA RESIDUAL |
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83 | */ |
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84 | |
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85 | uint32_t VME_Slot1 = FALSE; |
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86 | |
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87 | /* |
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88 | * PCI Bus Frequency |
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89 | */ |
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90 | unsigned int BSP_bus_frequency; |
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91 | |
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92 | /* |
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93 | * processor clock frequency |
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94 | */ |
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95 | unsigned int BSP_processor_frequency; |
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96 | |
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97 | /* |
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98 | * Time base divisior (how many tick for 1 second). |
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99 | */ |
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100 | unsigned int BSP_time_base_divisor = 1000; /* XXX - Just a guess */ |
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101 | |
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102 | void BSP_panic(char *s) |
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103 | { |
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104 | printk("%s PANIC %s\n",_RTEMS_version, s); |
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105 | __asm__ __volatile ("sc"); |
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106 | } |
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107 | |
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108 | void _BSP_Fatal_error(unsigned int v) |
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109 | { |
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110 | printk("%s PANIC ERROR %x\n",_RTEMS_version, v); |
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111 | __asm__ __volatile ("sc"); |
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112 | } |
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113 | |
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114 | int BSP_FLASH_Disable_writes( |
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115 | uint32_t area |
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116 | ) |
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117 | { |
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118 | unsigned char data; |
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119 | |
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120 | data = *GENERAL_REGISTER1; |
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121 | data |= DISABLE_USER_FLASH; |
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122 | *GENERAL_REGISTER1 = data; |
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123 | |
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124 | return RTEMS_SUCCESSFUL; |
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125 | } |
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126 | |
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127 | int BSP_FLASH_Enable_writes( |
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128 | uint32_t area /* IN */ |
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129 | ) |
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130 | { |
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131 | unsigned char data; |
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132 | |
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133 | data = *GENERAL_REGISTER1; |
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134 | data &= (~DISABLE_USER_FLASH); |
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135 | *GENERAL_REGISTER1 = data; |
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136 | |
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137 | return RTEMS_SUCCESSFUL; |
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138 | } |
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139 | |
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140 | void BSP_FLASH_set_page( |
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141 | uint8_t page |
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142 | ) |
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143 | { |
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144 | unsigned char data; |
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145 | |
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146 | /* Set the flash page register. */ |
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147 | data = *GENERAL_REGISTER2; |
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148 | data &= ~(BSP_FLASH_PAGE_MASK); |
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149 | data |= 0x80 | (page << BSP_FLASH_PAGE_SHIFT); |
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150 | *GENERAL_REGISTER2 = data; |
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151 | } |
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152 | |
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153 | /* |
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154 | * bsp_pretasking_hook |
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155 | * |
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156 | * BSP pretasking hook. Called just before drivers are initialized. |
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157 | */ |
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158 | void bsp_pretasking_hook(void) |
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159 | { |
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160 | rsPMCQ1Init(); |
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161 | } |
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162 | |
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163 | void zero_bss(void) |
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164 | { |
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165 | memset(__SBSS_START__, 0, ((unsigned) __SBSS_END__) - ((unsigned)__SBSS_START__)); |
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166 | memset(__SBSS2_START__, 0, ((unsigned) __SBSS2_END__) - ((unsigned)__SBSS2_START__)); |
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167 | memset(__bss_start, 0, ((unsigned) __rtems_end) - ((unsigned)__bss_start)); |
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168 | } |
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169 | |
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170 | char * save_boot_params(RESIDUAL* r3, void *r4, void* r5, char *additional_boot_options) |
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171 | { |
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172 | #if 0 |
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173 | residualCopy = *r3; |
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174 | strncpy(loaderParam, additional_boot_options, MAX_LOADER_ADD_PARM); |
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175 | loaderParam[MAX_LOADER_ADD_PARM - 1] ='\0'; |
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176 | return loaderParam; |
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177 | #endif |
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178 | return 0; |
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179 | } |
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180 | |
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181 | unsigned int EUMBBAR; |
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182 | |
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183 | unsigned int get_eumbbar(void) { |
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184 | register int a, e; |
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185 | |
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186 | __asm__ volatile( "lis %0,0xfec0; ori %0,%0,0x0000": "=r" (a) ); |
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187 | __asm__ volatile("sync"); |
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188 | |
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189 | __asm__ volatile("lis %0,0x8000; ori %0,%0,0x0078": "=r"(e) ); |
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190 | __asm__ volatile("stwbrx %0,0x0,%1": "=r"(e): "r"(a)); |
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191 | __asm__ volatile("sync"); |
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192 | |
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193 | __asm__ volatile("lis %0,0xfee0; ori %0,%0,0x0000": "=r" (a) ); |
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194 | __asm__ volatile("sync"); |
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195 | |
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196 | __asm__ volatile("lwbrx %0,0x0,%1": "=r" (e): "r" (a)); |
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197 | __asm__ volatile("isync"); |
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198 | return e; |
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199 | } |
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200 | |
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201 | void Read_ep1a_config_registers( ppc_cpu_id_t myCpu ) { |
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202 | unsigned char value; |
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203 | |
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204 | /* |
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205 | * Print out the board and revision. |
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206 | */ |
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207 | |
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208 | printk("Board: "); |
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209 | printk( get_ppc_cpu_type_name(myCpu) ); |
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210 | |
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211 | value = *BOARD_REVISION_REGISTER2 & HARDWARE_ID_MASK; |
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212 | if ( value == HARDWARE_ID_PPC5_EP1A ) |
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213 | printk(" EP1A "); |
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214 | else if ( value == HARDWARE_ID_EP1B ) |
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215 | printk(" EP1B "); |
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216 | else |
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217 | printk(" Unknown "); |
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218 | |
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219 | value = *BOARD_REVISION_REGISTER2&0x1; |
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220 | printk("Board ID %08x", value); |
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221 | if(value == 0x0){ |
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222 | VME_Slot1 = TRUE; |
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223 | printk("VME Slot 1\n"); |
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224 | } |
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225 | else{ |
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226 | VME_Slot1 = FALSE; |
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227 | printk("\n"); |
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228 | } |
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229 | |
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230 | printk("Revision: "); |
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231 | value = *BOARD_REVISION_REGISTER1; |
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232 | printk("%d%c\n\n", value>>4, 'A'+(value&BUILD_REVISION_MASK) ); |
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233 | |
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234 | /* |
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235 | * Get the CPU, XXX frequency |
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236 | */ |
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237 | value = *EQUIPMENT_PRESENT_REGISTER2 & PLL_CFG_MASK; |
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238 | switch( value ) { |
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239 | case MHZ_33_66_200: /* PCI, MEM, & CPU Frequency */ |
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240 | BSP_processor_frequency = 200000000; |
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241 | BSP_bus_frequency = 33000000; |
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242 | break; |
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243 | case MHZ_33_100_200: /* PCI, MEM, & CPU Frequency */ |
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244 | BSP_processor_frequency = 200000000; |
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245 | BSP_bus_frequency = 33000000; |
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246 | break; |
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247 | case MHZ_33_66_266: /* PCI, MEM, & CPU Frequency */ |
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248 | BSP_processor_frequency = 266000000; |
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249 | BSP_bus_frequency = 33000000; |
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250 | break; |
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251 | case MHZ_33_66_333: /* PCI, MEM, & CPU Frequency */ |
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252 | BSP_processor_frequency = 333000000; |
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253 | BSP_bus_frequency = 33000000; |
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254 | break; |
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255 | case MHZ_33_100_333: /* PCI, MEM, & CPU Frequency */ |
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256 | BSP_processor_frequency = 333000000; |
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257 | BSP_bus_frequency = 33000000; |
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258 | break; |
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259 | case MHZ_33_100_350: /* PCI, MEM, & CPU Frequency */ |
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260 | BSP_processor_frequency = 350000000; |
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261 | BSP_bus_frequency = 33000000; |
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262 | break; |
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263 | default: |
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264 | printk("ERROR: Unknown Processor frequency 0x%02x please fill in bspstart.c\n",value); |
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265 | BSP_processor_frequency = 350000000; |
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266 | BSP_bus_frequency = 33000000; |
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267 | break; |
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268 | } |
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269 | } |
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270 | |
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271 | /* |
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272 | * bsp_start |
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273 | * |
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274 | * This routine does the bulk of the system initialization. |
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275 | */ |
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276 | |
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277 | void bsp_start( void ) |
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278 | { |
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279 | uintptr_t intrStackStart; |
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280 | uintptr_t intrStackSize; |
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281 | ppc_cpu_id_t myCpu; |
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282 | ppc_cpu_revision_t myCpuRevision; |
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283 | Triv121PgTbl pt=0; /* R = e; */ |
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284 | |
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285 | /* |
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286 | * Get CPU identification dynamically. Note that the get_ppc_cpu_type() |
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287 | * function store the result in global variables so that it can be used |
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288 | * latter... |
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289 | */ |
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290 | BSP_Increment_Light(); |
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291 | myCpu = get_ppc_cpu_type(); |
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292 | myCpuRevision = get_ppc_cpu_revision(); |
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293 | |
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294 | EUMBBAR = get_eumbbar(); |
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295 | printk("EUMBBAR 0x%08x\n", EUMBBAR ); |
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296 | |
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297 | /* |
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298 | * Note this sets BSP_processor_frequency based upon register settings. |
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299 | * It must be done prior to setting up hooks. |
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300 | */ |
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301 | Read_ep1a_config_registers( myCpu ); |
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302 | |
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303 | bsp_clicks_per_usec = BSP_processor_frequency/(BSP_time_base_divisor * 1000); |
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304 | rtems_counter_initialize_converter( |
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305 | BSP_processor_frequency / (BSP_time_base_divisor / 1000) |
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306 | ); |
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307 | |
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308 | ShowBATS(); |
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309 | #if 0 /* XXX - Add back in cache enable when we get this up and running!! */ |
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310 | /* |
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311 | * enables L1 Cache. Note that the L1_caches_enables() codes checks for |
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312 | * relevant CPU type so that the reason why there is no use of myCpu... |
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313 | */ |
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314 | L1_caches_enables(); |
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315 | #endif |
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316 | |
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317 | /* |
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318 | * Initialize the interrupt related settings. |
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319 | */ |
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320 | intrStackStart = (uintptr_t) __rtems_end; |
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321 | intrStackSize = rtems_configuration_get_interrupt_stack_size(); |
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322 | |
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323 | /* |
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324 | * Initialize default raw exception hanlders. |
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325 | */ |
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326 | ppc_exc_initialize(intrStackStart, intrStackSize); |
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327 | |
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328 | /* |
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329 | * Init MMU block address translation to enable hardware |
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330 | * access |
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331 | */ |
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332 | setdbat(1, 0xf0000000, 0xf0000000, 0x10000000, IO_PAGE); |
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333 | setdbat(3, 0x90000000, 0x90000000, 0x10000000, IO_PAGE); |
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334 | |
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335 | |
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336 | #ifdef SHOW_MORE_INIT_SETTINGS |
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337 | printk("Going to start PCI buses scanning and initialization\n"); |
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338 | #endif |
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339 | pci_initialize(); |
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340 | |
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341 | #ifdef SHOW_MORE_INIT_SETTINGS |
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342 | printk("Number of PCI buses found is : %d\n", pci_bus_count()); |
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343 | #endif |
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344 | #ifdef TEST_RAW_EXCEPTION_CODE |
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345 | printk("Testing exception handling Part 1\n"); |
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346 | |
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347 | /* |
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348 | * Cause a software exception |
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349 | */ |
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350 | __asm__ __volatile ("sc"); |
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351 | |
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352 | /* |
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353 | * Check we can still catch exceptions and returned coorectly. |
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354 | */ |
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355 | printk("Testing exception handling Part 2\n"); |
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356 | __asm__ __volatile ("sc"); |
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357 | #endif |
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358 | |
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359 | /* |
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360 | * Initalize RTEMS IRQ system |
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361 | */ |
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362 | BSP_rtems_irq_mng_init(0); |
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363 | |
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364 | /* Activate the page table mappings only after |
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365 | * initializing interrupts because the irq_mng_init() |
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366 | * routine needs to modify the text |
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367 | */ |
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368 | if (pt) { |
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369 | #ifdef SHOW_MORE_INIT_SETTINGS |
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370 | printk("Page table setup finished; will activate it NOW...\n"); |
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371 | #endif |
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372 | BSP_pgtbl_activate(pt); |
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373 | } |
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374 | |
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375 | /* |
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376 | * Initialize VME bridge - needs working PCI |
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377 | * and IRQ subsystems... |
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378 | */ |
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379 | #ifdef SHOW_MORE_INIT_SETTINGS |
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380 | printk("Going to initialize VME bridge\n"); |
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381 | #endif |
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382 | /* VME initialization is in a separate file so apps which don't use |
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383 | * VME or want a different configuration may link against a customized |
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384 | * routine. |
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385 | */ |
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386 | BSP_vme_config(); |
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387 | |
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388 | #ifdef SHOW_MORE_INIT_SETTINGS |
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389 | ShowBATS(); |
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390 | printk("Exit from bspstart\n"); |
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391 | #endif |
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392 | } |
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