source: rtems/c/src/lib/libbsp/powerpc/ep1a/startup/bspstart.c @ b1e8a58

4.11
Last change on this file since b1e8a58 was b1e8a58, checked in by Sebastian Huber <sebastian.huber@…>, on Nov 14, 2012 at 8:57:55 AM

bsps/powerpc: Exception initialization error is fatal

  • Property mode set to 100644
File size: 9.4 KB
Line 
1/*
2 *  This routine starts the application.  It includes application,
3 *  board, and monitor specific initialization and configuration.
4 *  The generic CPU dependent initialization has been performed
5 *  before this routine is invoked.
6 *
7 *  COPYRIGHT (c) 1989-2007.
8 *  On-Line Applications Research Corporation (OAR).
9 *
10 *  The license and distribution terms for this file may be
11 *  found in the file LICENSE in this distribution or at
12 *  http://www.rtems.com/license/LICENSE.
13 */
14
15#warning The interrupt disable mask is now stored in SPRG0, please verify that this is compatible to this BSP (see also bootcard.c).
16
17#include <bsp/consoleIo.h>
18#include <libcpu/spr.h>
19#include <bsp/residual.h>
20#include <bsp/pci.h>
21#include <bsp/openpic.h>
22#include <bsp/irq.h>
23#include <bsp/VME.h>
24#include <bsp.h>
25#include <libcpu/bat.h>
26#include <libcpu/pte121.h>
27#include <libcpu/cpuIdent.h>
28#include <bsp/vectors.h>
29#include <rtems/powerpc/powerpc.h>
30
31extern unsigned long __bss_start[], __SBSS_START__[], __SBSS_END__[];
32extern unsigned long __SBSS2_START__[], __SBSS2_END__[];
33
34extern unsigned long __rtems_end[];
35extern void L1_caches_enables(void);
36extern unsigned get_L2CR(void);
37extern void set_L2CR(unsigned);
38extern Triv121PgTbl BSP_pgtbl_setup(void);
39extern void BSP_pgtbl_activate(Triv121PgTbl);
40extern void BSP_vme_config(void);
41extern void ShowBATS(void);
42unsigned int rsPMCQ1Init(void);
43
44uint32_t bsp_clicks_per_usec;
45
46SPR_RW(SPRG1)
47
48uint8_t LightIdx = 0;
49
50extern int RAM_END;
51unsigned int BSP_mem_size = (unsigned int)&RAM_END;
52
53void BSP_Increment_Light(void){
54  uint8_t data;
55  data = *GENERAL_REGISTER1;
56  data &= 0xf0;
57  data |= LightIdx++;
58  *GENERAL_REGISTER1 = data;
59}
60
61void BSP_Fatal_Fault_Light(void) {
62  uint8_t data;
63  data = *GENERAL_REGISTER1;
64  data &= 0xf0;
65  data |= 0x7;
66  while(1)
67    *GENERAL_REGISTER1 = data;
68}
69
70void write_to_Q2ram(int offset, unsigned int data )
71{
72printk("0x%x ==> %d\n", offset, data );
73#if 0
74  unsigned int *ptr = 0x82000000;
75  ptr += offset;
76  *ptr = data;
77#endif
78}
79
80/*
81 * Vital Board data Start using DATA RESIDUAL
82 */
83
84uint32_t VME_Slot1 = FALSE;
85
86/*
87 * PCI Bus Frequency
88 */
89unsigned int BSP_bus_frequency;
90
91/*
92 * processor clock frequency
93 */
94unsigned int BSP_processor_frequency;
95
96/*
97 * Time base divisior (how many tick for 1 second).
98 */
99unsigned int BSP_time_base_divisor = 1000;  /* XXX - Just a guess */
100
101void BSP_panic(char *s)
102{
103  printk("%s PANIC %s\n",_RTEMS_version, s);
104  __asm__ __volatile ("sc");
105}
106
107void _BSP_Fatal_error(unsigned int v)
108{
109  printk("%s PANIC ERROR %x\n",_RTEMS_version, v);
110  __asm__ __volatile ("sc");
111}
112
113int BSP_FLASH_Disable_writes(
114  uint32_t    area
115)
116{
117  unsigned char    data;
118
119  data = *GENERAL_REGISTER1;
120  data |= DISABLE_USER_FLASH;
121  *GENERAL_REGISTER1 = data;
122
123  return RTEMS_SUCCESSFUL;
124}
125
126int BSP_FLASH_Enable_writes(
127 uint32_t               area                           /* IN  */
128)
129{
130  unsigned char    data;
131
132  data = *GENERAL_REGISTER1;
133  data &= (~DISABLE_USER_FLASH);
134  *GENERAL_REGISTER1 = data;
135
136  return RTEMS_SUCCESSFUL;
137}
138
139void BSP_FLASH_set_page(
140  uint8_t  page
141)
142{
143  unsigned char  data;
144
145  /* Set the flash page register. */
146  data = *GENERAL_REGISTER2;
147  data &= ~(BSP_FLASH_PAGE_MASK);
148  data |= 0x80 | (page << BSP_FLASH_PAGE_SHIFT);
149  *GENERAL_REGISTER2 = data;
150}
151
152/*
153 *  bsp_pretasking_hook
154 *
155 *  BSP pretasking hook.  Called just before drivers are initialized.
156 */
157void bsp_pretasking_hook(void)
158{
159  rsPMCQ1Init();
160}
161
162void zero_bss(void)
163{
164  memset(__SBSS_START__, 0, ((unsigned) __SBSS_END__) - ((unsigned)__SBSS_START__));
165  memset(__SBSS2_START__, 0, ((unsigned) __SBSS2_END__) - ((unsigned)__SBSS2_START__));
166  memset(__bss_start, 0, ((unsigned) __rtems_end) - ((unsigned)__bss_start));
167}
168
169char * save_boot_params(RESIDUAL* r3, void *r4, void* r5, char *additional_boot_options)
170{
171#if 0
172  residualCopy = *r3;
173  strncpy(loaderParam, additional_boot_options, MAX_LOADER_ADD_PARM);
174  loaderParam[MAX_LOADER_ADD_PARM - 1] ='\0';
175  return loaderParam;
176#endif
177  return 0;
178}
179
180unsigned int EUMBBAR;
181
182unsigned int get_eumbbar(void) {
183  register int a, e;
184
185  __asm__ volatile( "lis %0,0xfec0; ori  %0,%0,0x0000": "=r" (a) );
186  __asm__ volatile("sync");
187
188  __asm__ volatile("lis %0,0x8000; ori %0,%0,0x0078": "=r"(e) );
189  __asm__ volatile("stwbrx  %0,0x0,%1": "=r"(e): "r"(a));
190  __asm__ volatile("sync");
191
192  __asm__ volatile("lis %0,0xfee0; ori %0,%0,0x0000": "=r" (a) );
193  __asm__ volatile("sync");
194
195  __asm__ volatile("lwbrx %0,0x0,%1": "=r" (e): "r" (a));
196  __asm__ volatile("isync");
197  return e;
198}
199
200void Read_ep1a_config_registers( ppc_cpu_id_t myCpu ) {
201  unsigned char value;
202
203  /*
204   * Print out the board and revision.
205   */
206
207  printk("Board:  ");
208  printk( get_ppc_cpu_type_name(myCpu) );
209
210  value = *BOARD_REVISION_REGISTER2 & HARDWARE_ID_MASK;
211  if ( value == HARDWARE_ID_PPC5_EP1A )
212    printk("  EP1A     ");
213  else if ( value == HARDWARE_ID_EP1B )
214    printk("  EP1B     ");
215  else
216    printk("  Unknown  ");
217
218  value = *BOARD_REVISION_REGISTER2&0x1;
219  printk("Board ID %08x", value);
220  if(value == 0x0){
221    VME_Slot1 = TRUE;
222    printk("VME Slot 1\n");
223  }
224  else{
225    VME_Slot1 = FALSE;
226    printk("\n");
227  }
228
229  printk("Revision: ");
230  value = *BOARD_REVISION_REGISTER1;
231  printk("%d%c\n\n", value>>4, 'A'+(value&BUILD_REVISION_MASK) );
232
233  /*
234   * Get the CPU, XXX frequency
235   */
236  value = *EQUIPMENT_PRESENT_REGISTER2 & PLL_CFG_MASK;
237  switch( value ) {
238    case MHZ_33_66_200:     /* PCI, MEM, & CPU Frequency */
239      BSP_processor_frequency = 200000000;
240      BSP_bus_frequency       =  33000000;
241      break;
242    case MHZ_33_100_200:   /* PCI, MEM, & CPU Frequency */
243      BSP_processor_frequency = 200000000;
244      BSP_bus_frequency       =  33000000;
245      break;
246    case MHZ_33_66_266:    /* PCI, MEM, & CPU Frequency */
247      BSP_processor_frequency = 266000000;
248      BSP_bus_frequency       =  33000000;
249      break;
250    case MHZ_33_66_333:   /* PCI, MEM, & CPU Frequency */
251      BSP_processor_frequency = 333000000;
252      BSP_bus_frequency       =  33000000;
253      break;
254    case MHZ_33_100_333:   /* PCI, MEM, & CPU Frequency */
255      BSP_processor_frequency = 333000000;
256      BSP_bus_frequency       =  33000000;
257      break;
258    case MHZ_33_100_350:   /* PCI, MEM, & CPU Frequency */
259      BSP_processor_frequency = 350000000;
260      BSP_bus_frequency       =  33000000;
261      break;
262    default:
263      printk("ERROR: Unknown Processor frequency 0x%02x please fill in bspstart.c\n",value);
264      BSP_processor_frequency = 350000000;
265      BSP_bus_frequency       =  33000000;
266      break;
267  }
268}
269
270/*
271 *  bsp_start
272 *
273 *  This routine does the bulk of the system initialization.
274 */
275
276void bsp_start( void )
277{
278  uintptr_t intrStackStart;
279  uintptr_t intrStackSize;
280  ppc_cpu_id_t myCpu;
281  ppc_cpu_revision_t myCpuRevision;
282  Triv121PgTbl  pt=0;   /*  R = e; */
283
284  /*
285   * Get CPU identification dynamically. Note that the get_ppc_cpu_type()
286   * function store the result in global variables so that it can be used
287   * latter...
288   */
289  BSP_Increment_Light();
290  myCpu         = get_ppc_cpu_type();
291  myCpuRevision = get_ppc_cpu_revision();
292
293  EUMBBAR = get_eumbbar();
294  printk("EUMBBAR 0x%08x\n", EUMBBAR );
295
296  /*
297   * Note this sets BSP_processor_frequency based upon register settings.
298   * It must be done prior to setting up hooks.
299   */
300  Read_ep1a_config_registers( myCpu );
301
302  bsp_clicks_per_usec = BSP_processor_frequency/(BSP_time_base_divisor * 1000);
303
304ShowBATS();
305#if 0   /* XXX - Add back in cache enable when we get this up and running!! */
306  /*
307   * enables L1 Cache. Note that the L1_caches_enables() codes checks for
308   * relevant CPU type so that the reason why there is no use of myCpu...
309   */
310  L1_caches_enables();
311#endif
312
313  /*
314   * Initialize the interrupt related settings.
315   */
316  intrStackStart = (uintptr_t) __rtems_end;
317  intrStackSize = rtems_configuration_get_interrupt_stack_size();
318
319  /*
320   * Initialize default raw exception hanlders.
321   */
322  ppc_exc_initialize(
323    PPC_INTERRUPT_DISABLE_MASK_DEFAULT,
324    intrStackStart,
325    intrStackSize
326  );
327
328  /*
329   * Init MMU block address translation to enable hardware
330   * access
331   */
332  setdbat(1, 0xf0000000, 0xf0000000, 0x10000000, IO_PAGE);
333  setdbat(3, 0x90000000, 0x90000000, 0x10000000, IO_PAGE);
334
335
336#ifdef SHOW_MORE_INIT_SETTINGS
337  printk("Going to start PCI buses scanning and initialization\n");
338#endif
339  pci_initialize();
340
341#ifdef SHOW_MORE_INIT_SETTINGS
342  printk("Number of PCI buses found is : %d\n", pci_bus_count());
343#endif
344#ifdef TEST_RAW_EXCEPTION_CODE
345  printk("Testing exception handling Part 1\n");
346
347  /*
348   * Cause a software exception
349   */
350  __asm__ __volatile ("sc");
351
352  /*
353   * Check we can still catch exceptions and returned coorectly.
354   */
355  printk("Testing exception handling Part 2\n");
356  __asm__ __volatile ("sc");
357#endif
358
359  /*
360   * Initalize RTEMS IRQ system
361   */
362  BSP_rtems_irq_mng_init(0);
363
364  /* Activate the page table mappings only after
365   * initializing interrupts because the irq_mng_init()
366   * routine needs to modify the text
367   */
368  if (pt) {
369#ifdef  SHOW_MORE_INIT_SETTINGS
370    printk("Page table setup finished; will activate it NOW...\n");
371#endif
372    BSP_pgtbl_activate(pt);
373  }
374
375  /*
376   * Initialize VME bridge - needs working PCI
377   * and IRQ subsystems...
378   */
379#ifdef SHOW_MORE_INIT_SETTINGS
380  printk("Going to initialize VME bridge\n");
381#endif
382  /* VME initialization is in a separate file so apps which don't use
383   * VME or want a different configuration may link against a customized
384   * routine.
385   */
386  BSP_vme_config();
387
388#ifdef SHOW_MORE_INIT_SETTINGS
389  ShowBATS();
390  printk("Exit from bspstart\n");
391#endif
392}
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