source: rtems/c/src/lib/libbsp/powerpc/ep1a/startup/bspstart.c @ 7ac87aee

4.115
Last change on this file since 7ac87aee was 7ac87aee, checked in by Joel Sherrill <joel.sherrill@…>, on Oct 7, 2014 at 10:31:59 PM

powerpc/ep1a/startup/bspstart.c: Add include of <bsp/bootcard.h> to fix warning and clean up

  • Property mode set to 100644
File size: 9.3 KB
Line 
1/*
2 *  This routine does the bulk of the system initialization.
3 */
4
5/*
6 *  COPYRIGHT (c) 1989-2007.
7 *  On-Line Applications Research Corporation (OAR).
8 *
9 *  The license and distribution terms for this file may be
10 *  found in the file LICENSE in this distribution or at
11 *  http://www.rtems.org/license/LICENSE.
12 */
13
14#warning The interrupt disable mask is now stored in SPRG0, please verify that this is compatible to this BSP (see also bootcard.c).
15
16#include <bsp/consoleIo.h>
17#include <bsp/bootcard.h>
18#include <libcpu/spr.h>
19#include <bsp/residual.h>
20#include <bsp/pci.h>
21#include <bsp/openpic.h>
22#include <bsp/irq.h>
23#include <bsp/VME.h>
24#include <bsp.h>
25#include <libcpu/bat.h>
26#include <libcpu/pte121.h>
27#include <libcpu/cpuIdent.h>
28#include <bsp/vectors.h>
29#include <rtems/powerpc/powerpc.h>
30#include <rtems/counter.h>
31
32extern unsigned long __bss_start[], __SBSS_START__[], __SBSS_END__[];
33extern unsigned long __SBSS2_START__[], __SBSS2_END__[];
34
35extern unsigned long __rtems_end[];
36extern void L1_caches_enables(void);
37extern unsigned get_L2CR(void);
38extern void set_L2CR(unsigned);
39extern Triv121PgTbl BSP_pgtbl_setup(void);
40extern void BSP_pgtbl_activate(Triv121PgTbl);
41extern void BSP_vme_config(void);
42extern void ShowBATS(void);
43unsigned int rsPMCQ1Init(void);
44
45uint32_t bsp_clicks_per_usec;
46
47SPR_RW(SPRG1)
48
49uint8_t LightIdx = 0;
50
51extern int RAM_END;
52unsigned int BSP_mem_size = (unsigned int)&RAM_END;
53
54void BSP_Increment_Light(void){
55  uint8_t data;
56  data = *GENERAL_REGISTER1;
57  data &= 0xf0;
58  data |= LightIdx++;
59  *GENERAL_REGISTER1 = data;
60}
61
62void BSP_Fatal_Fault_Light(void) {
63  uint8_t data;
64  data = *GENERAL_REGISTER1;
65  data &= 0xf0;
66  data |= 0x7;
67  while(1)
68    *GENERAL_REGISTER1 = data;
69}
70
71void write_to_Q2ram(int offset, unsigned int data )
72{
73printk("0x%x ==> %d\n", offset, data );
74#if 0
75  unsigned int *ptr = 0x82000000;
76  ptr += offset;
77  *ptr = data;
78#endif
79}
80
81/*
82 * Vital Board data Start using DATA RESIDUAL
83 */
84
85uint32_t VME_Slot1 = FALSE;
86
87/*
88 * PCI Bus Frequency
89 */
90unsigned int BSP_bus_frequency;
91
92/*
93 * processor clock frequency
94 */
95unsigned int BSP_processor_frequency;
96
97/*
98 * Time base divisior (how many tick for 1 second).
99 */
100unsigned int BSP_time_base_divisor = 1000;  /* XXX - Just a guess */
101
102void BSP_panic(char *s)
103{
104  printk("%s PANIC %s\n",_RTEMS_version, s);
105  __asm__ __volatile ("sc");
106}
107
108void _BSP_Fatal_error(unsigned int v)
109{
110  printk("%s PANIC ERROR %x\n",_RTEMS_version, v);
111  __asm__ __volatile ("sc");
112}
113
114int BSP_FLASH_Disable_writes(
115  uint32_t    area
116)
117{
118  unsigned char    data;
119
120  data = *GENERAL_REGISTER1;
121  data |= DISABLE_USER_FLASH;
122  *GENERAL_REGISTER1 = data;
123
124  return RTEMS_SUCCESSFUL;
125}
126
127int BSP_FLASH_Enable_writes(
128 uint32_t               area                           /* IN  */
129)
130{
131  unsigned char    data;
132
133  data = *GENERAL_REGISTER1;
134  data &= (~DISABLE_USER_FLASH);
135  *GENERAL_REGISTER1 = data;
136
137  return RTEMS_SUCCESSFUL;
138}
139
140void BSP_FLASH_set_page(
141  uint8_t  page
142)
143{
144  unsigned char  data;
145
146  /* Set the flash page register. */
147  data = *GENERAL_REGISTER2;
148  data &= ~(BSP_FLASH_PAGE_MASK);
149  data |= 0x80 | (page << BSP_FLASH_PAGE_SHIFT);
150  *GENERAL_REGISTER2 = data;
151}
152
153/*
154 *  bsp_pretasking_hook
155 *
156 *  BSP pretasking hook.  Called just before drivers are initialized.
157 */
158void bsp_pretasking_hook(void)
159{
160  rsPMCQ1Init();
161}
162
163void zero_bss(void)
164{
165  memset(__SBSS_START__, 0, ((unsigned) __SBSS_END__) - ((unsigned)__SBSS_START__));
166  memset(__SBSS2_START__, 0, ((unsigned) __SBSS2_END__) - ((unsigned)__SBSS2_START__));
167  memset(__bss_start, 0, ((unsigned) __rtems_end) - ((unsigned)__bss_start));
168}
169
170char * save_boot_params(RESIDUAL* r3, void *r4, void* r5, char *additional_boot_options)
171{
172#if 0
173  residualCopy = *r3;
174  strncpy(loaderParam, additional_boot_options, MAX_LOADER_ADD_PARM);
175  loaderParam[MAX_LOADER_ADD_PARM - 1] ='\0';
176  return loaderParam;
177#endif
178  return 0;
179}
180
181unsigned int EUMBBAR;
182
183unsigned int get_eumbbar(void) {
184  register int a, e;
185
186  __asm__ volatile( "lis %0,0xfec0; ori  %0,%0,0x0000": "=r" (a) );
187  __asm__ volatile("sync");
188
189  __asm__ volatile("lis %0,0x8000; ori %0,%0,0x0078": "=r"(e) );
190  __asm__ volatile("stwbrx  %0,0x0,%1": "=r"(e): "r"(a));
191  __asm__ volatile("sync");
192
193  __asm__ volatile("lis %0,0xfee0; ori %0,%0,0x0000": "=r" (a) );
194  __asm__ volatile("sync");
195
196  __asm__ volatile("lwbrx %0,0x0,%1": "=r" (e): "r" (a));
197  __asm__ volatile("isync");
198  return e;
199}
200
201void Read_ep1a_config_registers( ppc_cpu_id_t myCpu ) {
202  unsigned char value;
203
204  /*
205   * Print out the board and revision.
206   */
207
208  printk("Board:  ");
209  printk( get_ppc_cpu_type_name(myCpu) );
210
211  value = *BOARD_REVISION_REGISTER2 & HARDWARE_ID_MASK;
212  if ( value == HARDWARE_ID_PPC5_EP1A )
213    printk("  EP1A     ");
214  else if ( value == HARDWARE_ID_EP1B )
215    printk("  EP1B     ");
216  else
217    printk("  Unknown  ");
218
219  value = *BOARD_REVISION_REGISTER2&0x1;
220  printk("Board ID %08x", value);
221  if(value == 0x0){
222    VME_Slot1 = TRUE;
223    printk("VME Slot 1\n");
224  }
225  else{
226    VME_Slot1 = FALSE;
227    printk("\n");
228  }
229
230  printk("Revision: ");
231  value = *BOARD_REVISION_REGISTER1;
232  printk("%d%c\n\n", value>>4, 'A'+(value&BUILD_REVISION_MASK) );
233
234  /*
235   * Get the CPU, XXX frequency
236   */
237  value = *EQUIPMENT_PRESENT_REGISTER2 & PLL_CFG_MASK;
238  switch( value ) {
239    case MHZ_33_66_200:     /* PCI, MEM, & CPU Frequency */
240      BSP_processor_frequency = 200000000;
241      BSP_bus_frequency       =  33000000;
242      break;
243    case MHZ_33_100_200:   /* PCI, MEM, & CPU Frequency */
244      BSP_processor_frequency = 200000000;
245      BSP_bus_frequency       =  33000000;
246      break;
247    case MHZ_33_66_266:    /* PCI, MEM, & CPU Frequency */
248      BSP_processor_frequency = 266000000;
249      BSP_bus_frequency       =  33000000;
250      break;
251    case MHZ_33_66_333:   /* PCI, MEM, & CPU Frequency */
252      BSP_processor_frequency = 333000000;
253      BSP_bus_frequency       =  33000000;
254      break;
255    case MHZ_33_100_333:   /* PCI, MEM, & CPU Frequency */
256      BSP_processor_frequency = 333000000;
257      BSP_bus_frequency       =  33000000;
258      break;
259    case MHZ_33_100_350:   /* PCI, MEM, & CPU Frequency */
260      BSP_processor_frequency = 350000000;
261      BSP_bus_frequency       =  33000000;
262      break;
263    default:
264      printk("ERROR: Unknown Processor frequency 0x%02x please fill in bspstart.c\n",value);
265      BSP_processor_frequency = 350000000;
266      BSP_bus_frequency       =  33000000;
267      break;
268  }
269}
270
271/*
272 *  bsp_start
273 *
274 *  This routine does the bulk of the system initialization.
275 */
276
277void bsp_start( void )
278{
279  uintptr_t intrStackStart;
280  uintptr_t intrStackSize;
281  ppc_cpu_id_t myCpu;
282  ppc_cpu_revision_t myCpuRevision;
283  Triv121PgTbl  pt=0;   /*  R = e; */
284
285  /*
286   * Get CPU identification dynamically. Note that the get_ppc_cpu_type()
287   * function store the result in global variables so that it can be used
288   * latter...
289   */
290  BSP_Increment_Light();
291  myCpu         = get_ppc_cpu_type();
292  myCpuRevision = get_ppc_cpu_revision();
293
294  EUMBBAR = get_eumbbar();
295  printk("EUMBBAR 0x%08x\n", EUMBBAR );
296
297  /*
298   * Note this sets BSP_processor_frequency based upon register settings.
299   * It must be done prior to setting up hooks.
300   */
301  Read_ep1a_config_registers( myCpu );
302
303  bsp_clicks_per_usec = BSP_processor_frequency/(BSP_time_base_divisor * 1000);
304  rtems_counter_initialize_converter(
305    BSP_processor_frequency / (BSP_time_base_divisor / 1000)
306  );
307
308ShowBATS();
309#if 0   /* XXX - Add back in cache enable when we get this up and running!! */
310  /*
311   * enables L1 Cache. Note that the L1_caches_enables() codes checks for
312   * relevant CPU type so that the reason why there is no use of myCpu...
313   */
314  L1_caches_enables();
315#endif
316
317  /*
318   * Initialize the interrupt related settings.
319   */
320  intrStackStart = (uintptr_t) __rtems_end;
321  intrStackSize = rtems_configuration_get_interrupt_stack_size();
322
323  /*
324   * Initialize default raw exception hanlders.
325   */
326  ppc_exc_initialize(intrStackStart, intrStackSize);
327
328  /*
329   * Init MMU block address translation to enable hardware
330   * access
331   */
332  setdbat(1, 0xf0000000, 0xf0000000, 0x10000000, IO_PAGE);
333  setdbat(3, 0x90000000, 0x90000000, 0x10000000, IO_PAGE);
334
335
336#ifdef SHOW_MORE_INIT_SETTINGS
337  printk("Going to start PCI buses scanning and initialization\n");
338#endif
339  pci_initialize();
340
341#ifdef SHOW_MORE_INIT_SETTINGS
342  printk("Number of PCI buses found is : %d\n", pci_bus_count());
343#endif
344#ifdef TEST_RAW_EXCEPTION_CODE
345  printk("Testing exception handling Part 1\n");
346
347  /*
348   * Cause a software exception
349   */
350  __asm__ __volatile ("sc");
351
352  /*
353   * Check we can still catch exceptions and returned coorectly.
354   */
355  printk("Testing exception handling Part 2\n");
356  __asm__ __volatile ("sc");
357#endif
358
359  /*
360   * Initalize RTEMS IRQ system
361   */
362  BSP_rtems_irq_mng_init(0);
363
364  /* Activate the page table mappings only after
365   * initializing interrupts because the irq_mng_init()
366   * routine needs to modify the text
367   */
368  if (pt) {
369#ifdef  SHOW_MORE_INIT_SETTINGS
370    printk("Page table setup finished; will activate it NOW...\n");
371#endif
372    BSP_pgtbl_activate(pt);
373  }
374
375  /*
376   * Initialize VME bridge - needs working PCI
377   * and IRQ subsystems...
378   */
379#ifdef SHOW_MORE_INIT_SETTINGS
380  printk("Going to initialize VME bridge\n");
381#endif
382  /* VME initialization is in a separate file so apps which don't use
383   * VME or want a different configuration may link against a customized
384   * routine.
385   */
386  BSP_vme_config();
387
388#ifdef SHOW_MORE_INIT_SETTINGS
389  ShowBATS();
390  printk("Exit from bspstart\n");
391#endif
392}
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