1 | /* |
---|
2 | * This routine starts the application. It includes application, |
---|
3 | * board, and monitor specific initialization and configuration. |
---|
4 | * The generic CPU dependent initialization has been performed |
---|
5 | * before this routine is invoked. |
---|
6 | * |
---|
7 | * COPYRIGHT (c) 1989-2007. |
---|
8 | * On-Line Applications Research Corporation (OAR). |
---|
9 | * |
---|
10 | * The license and distribution terms for this file may be |
---|
11 | * found in the file LICENSE in this distribution or at |
---|
12 | * http://www.rtems.com/license/LICENSE. |
---|
13 | * |
---|
14 | * $Id$ |
---|
15 | */ |
---|
16 | |
---|
17 | #warning The interrupt disable mask is now stored in SPRG0, please verify that this is compatible to this BSP (see also bootcard.c). |
---|
18 | |
---|
19 | #include <bsp/consoleIo.h> |
---|
20 | #include <libcpu/spr.h> |
---|
21 | #include <bsp/residual.h> |
---|
22 | #include <bsp/pci.h> |
---|
23 | #include <bsp/openpic.h> |
---|
24 | #include <bsp/irq.h> |
---|
25 | #include <bsp/VME.h> |
---|
26 | #include <bsp.h> |
---|
27 | #include <libcpu/bat.h> |
---|
28 | #include <libcpu/pte121.h> |
---|
29 | #include <libcpu/cpuIdent.h> |
---|
30 | #include <bsp/vectors.h> |
---|
31 | #include <rtems/powerpc/powerpc.h> |
---|
32 | |
---|
33 | extern unsigned long __bss_start[], __SBSS_START__[], __SBSS_END__[]; |
---|
34 | extern unsigned long __SBSS2_START__[], __SBSS2_END__[]; |
---|
35 | |
---|
36 | extern unsigned long __rtems_end[]; |
---|
37 | extern void L1_caches_enables(void); |
---|
38 | extern unsigned get_L2CR(void); |
---|
39 | extern void set_L2CR(unsigned); |
---|
40 | extern Triv121PgTbl BSP_pgtbl_setup(void); |
---|
41 | extern void BSP_pgtbl_activate(Triv121PgTbl); |
---|
42 | extern void BSP_vme_config(void); |
---|
43 | extern void ShowBATS(void); |
---|
44 | unsigned int rsPMCQ1Init(void); |
---|
45 | |
---|
46 | uint32_t bsp_clicks_per_usec; |
---|
47 | |
---|
48 | SPR_RW(SPRG1) |
---|
49 | |
---|
50 | uint8_t LightIdx = 0; |
---|
51 | |
---|
52 | extern int RAM_END; |
---|
53 | unsigned int BSP_mem_size = (unsigned int)&RAM_END; |
---|
54 | |
---|
55 | void BSP_Increment_Light(void){ |
---|
56 | uint8_t data; |
---|
57 | data = *GENERAL_REGISTER1; |
---|
58 | data &= 0xf0; |
---|
59 | data |= LightIdx++; |
---|
60 | *GENERAL_REGISTER1 = data; |
---|
61 | } |
---|
62 | |
---|
63 | void BSP_Fatal_Fault_Light(void) { |
---|
64 | uint8_t data; |
---|
65 | data = *GENERAL_REGISTER1; |
---|
66 | data &= 0xf0; |
---|
67 | data |= 0x7; |
---|
68 | while(1) |
---|
69 | *GENERAL_REGISTER1 = data; |
---|
70 | } |
---|
71 | |
---|
72 | void write_to_Q2ram(int offset, unsigned int data ) |
---|
73 | { |
---|
74 | printk("0x%x ==> %d\n", offset, data ); |
---|
75 | #if 0 |
---|
76 | unsigned int *ptr = 0x82000000; |
---|
77 | ptr += offset; |
---|
78 | *ptr = data; |
---|
79 | #endif |
---|
80 | } |
---|
81 | |
---|
82 | /* |
---|
83 | * Vital Board data Start using DATA RESIDUAL |
---|
84 | */ |
---|
85 | |
---|
86 | uint32_t VME_Slot1 = FALSE; |
---|
87 | |
---|
88 | /* |
---|
89 | * PCI Bus Frequency |
---|
90 | */ |
---|
91 | unsigned int BSP_bus_frequency; |
---|
92 | |
---|
93 | /* |
---|
94 | * processor clock frequency |
---|
95 | */ |
---|
96 | unsigned int BSP_processor_frequency; |
---|
97 | |
---|
98 | /* |
---|
99 | * Time base divisior (how many tick for 1 second). |
---|
100 | */ |
---|
101 | unsigned int BSP_time_base_divisor = 1000; /* XXX - Just a guess */ |
---|
102 | |
---|
103 | void BSP_panic(char *s) |
---|
104 | { |
---|
105 | printk("%s PANIC %s\n",_RTEMS_version, s); |
---|
106 | __asm__ __volatile ("sc"); |
---|
107 | } |
---|
108 | |
---|
109 | void _BSP_Fatal_error(unsigned int v) |
---|
110 | { |
---|
111 | printk("%s PANIC ERROR %x\n",_RTEMS_version, v); |
---|
112 | __asm__ __volatile ("sc"); |
---|
113 | } |
---|
114 | |
---|
115 | int BSP_FLASH_Disable_writes( |
---|
116 | uint32_t area |
---|
117 | ) |
---|
118 | { |
---|
119 | unsigned char data; |
---|
120 | |
---|
121 | data = *GENERAL_REGISTER1; |
---|
122 | data |= DISABLE_USER_FLASH; |
---|
123 | *GENERAL_REGISTER1 = data; |
---|
124 | |
---|
125 | return RTEMS_SUCCESSFUL; |
---|
126 | } |
---|
127 | |
---|
128 | int BSP_FLASH_Enable_writes( |
---|
129 | uint32_t area /* IN */ |
---|
130 | ) |
---|
131 | { |
---|
132 | unsigned char data; |
---|
133 | |
---|
134 | data = *GENERAL_REGISTER1; |
---|
135 | data &= (~DISABLE_USER_FLASH); |
---|
136 | *GENERAL_REGISTER1 = data; |
---|
137 | |
---|
138 | return RTEMS_SUCCESSFUL; |
---|
139 | } |
---|
140 | |
---|
141 | void BSP_FLASH_set_page( |
---|
142 | uint8_t page |
---|
143 | ) |
---|
144 | { |
---|
145 | unsigned char data; |
---|
146 | |
---|
147 | /* Set the flash page register. */ |
---|
148 | data = *GENERAL_REGISTER2; |
---|
149 | data &= ~(BSP_FLASH_PAGE_MASK); |
---|
150 | data |= 0x80 | (page << BSP_FLASH_PAGE_SHIFT); |
---|
151 | *GENERAL_REGISTER2 = data; |
---|
152 | } |
---|
153 | |
---|
154 | /* |
---|
155 | * bsp_pretasking_hook |
---|
156 | * |
---|
157 | * BSP pretasking hook. Called just before drivers are initialized. |
---|
158 | */ |
---|
159 | void bsp_pretasking_hook(void) |
---|
160 | { |
---|
161 | rsPMCQ1Init(); |
---|
162 | } |
---|
163 | |
---|
164 | void zero_bss(void) |
---|
165 | { |
---|
166 | memset(__SBSS_START__, 0, ((unsigned) __SBSS_END__) - ((unsigned)__SBSS_START__)); |
---|
167 | memset(__SBSS2_START__, 0, ((unsigned) __SBSS2_END__) - ((unsigned)__SBSS2_START__)); |
---|
168 | memset(__bss_start, 0, ((unsigned) __rtems_end) - ((unsigned)__bss_start)); |
---|
169 | } |
---|
170 | |
---|
171 | char * save_boot_params(RESIDUAL* r3, void *r4, void* r5, char *additional_boot_options) |
---|
172 | { |
---|
173 | #if 0 |
---|
174 | residualCopy = *r3; |
---|
175 | strncpy(loaderParam, additional_boot_options, MAX_LOADER_ADD_PARM); |
---|
176 | loaderParam[MAX_LOADER_ADD_PARM - 1] ='\0'; |
---|
177 | return loaderParam; |
---|
178 | #endif |
---|
179 | return 0; |
---|
180 | } |
---|
181 | |
---|
182 | unsigned int EUMBBAR; |
---|
183 | |
---|
184 | unsigned int get_eumbbar(void) { |
---|
185 | register int a, e; |
---|
186 | |
---|
187 | asm volatile( "lis %0,0xfec0; ori %0,%0,0x0000": "=r" (a) ); |
---|
188 | asm volatile("sync"); |
---|
189 | |
---|
190 | asm volatile("lis %0,0x8000; ori %0,%0,0x0078": "=r"(e) ); |
---|
191 | asm volatile("stwbrx %0,0x0,%1": "=r"(e): "r"(a)); |
---|
192 | asm volatile("sync"); |
---|
193 | |
---|
194 | asm volatile("lis %0,0xfee0; ori %0,%0,0x0000": "=r" (a) ); |
---|
195 | asm volatile("sync"); |
---|
196 | |
---|
197 | asm volatile("lwbrx %0,0x0,%1": "=r" (e): "r" (a)); |
---|
198 | asm volatile("isync"); |
---|
199 | return e; |
---|
200 | } |
---|
201 | |
---|
202 | void Read_ep1a_config_registers( ppc_cpu_id_t myCpu ) { |
---|
203 | unsigned char value; |
---|
204 | |
---|
205 | /* |
---|
206 | * Print out the board and revision. |
---|
207 | */ |
---|
208 | |
---|
209 | printk("Board: "); |
---|
210 | printk( get_ppc_cpu_type_name(myCpu) ); |
---|
211 | |
---|
212 | value = *BOARD_REVISION_REGISTER2 & HARDWARE_ID_MASK; |
---|
213 | if ( value == HARDWARE_ID_PPC5_EP1A ) |
---|
214 | printk(" EP1A "); |
---|
215 | else if ( value == HARDWARE_ID_EP1B ) |
---|
216 | printk(" EP1B "); |
---|
217 | else |
---|
218 | printk(" Unknown "); |
---|
219 | |
---|
220 | value = *BOARD_REVISION_REGISTER2&0x1; |
---|
221 | printk("Board ID %08x", value); |
---|
222 | if(value == 0x0){ |
---|
223 | VME_Slot1 = TRUE; |
---|
224 | printk("VME Slot 1\n"); |
---|
225 | } |
---|
226 | else{ |
---|
227 | VME_Slot1 = FALSE; |
---|
228 | printk("\n"); |
---|
229 | } |
---|
230 | |
---|
231 | printk("Revision: "); |
---|
232 | value = *BOARD_REVISION_REGISTER1; |
---|
233 | printk("%d%c\n\n", value>>4, 'A'+(value&BUILD_REVISION_MASK) ); |
---|
234 | |
---|
235 | /* |
---|
236 | * Get the CPU, XXX frequency |
---|
237 | */ |
---|
238 | value = *EQUIPMENT_PRESENT_REGISTER2 & PLL_CFG_MASK; |
---|
239 | switch( value ) { |
---|
240 | case MHZ_33_66_200: /* PCI, MEM, & CPU Frequency */ |
---|
241 | BSP_processor_frequency = 200000000; |
---|
242 | BSP_bus_frequency = 33000000; |
---|
243 | break; |
---|
244 | case MHZ_33_100_200: /* PCI, MEM, & CPU Frequency */ |
---|
245 | BSP_processor_frequency = 200000000; |
---|
246 | BSP_bus_frequency = 33000000; |
---|
247 | break; |
---|
248 | case MHZ_33_66_266: /* PCI, MEM, & CPU Frequency */ |
---|
249 | BSP_processor_frequency = 266000000; |
---|
250 | BSP_bus_frequency = 33000000; |
---|
251 | break; |
---|
252 | case MHZ_33_66_333: /* PCI, MEM, & CPU Frequency */ |
---|
253 | BSP_processor_frequency = 333000000; |
---|
254 | BSP_bus_frequency = 33000000; |
---|
255 | break; |
---|
256 | case MHZ_33_100_333: /* PCI, MEM, & CPU Frequency */ |
---|
257 | BSP_processor_frequency = 333000000; |
---|
258 | BSP_bus_frequency = 33000000; |
---|
259 | break; |
---|
260 | case MHZ_33_100_350: /* PCI, MEM, & CPU Frequency */ |
---|
261 | BSP_processor_frequency = 350000000; |
---|
262 | BSP_bus_frequency = 33000000; |
---|
263 | break; |
---|
264 | default: |
---|
265 | printk("ERROR: Unknown Processor frequency 0x%02x please fill in bspstart.c\n",value); |
---|
266 | BSP_processor_frequency = 350000000; |
---|
267 | BSP_bus_frequency = 33000000; |
---|
268 | break; |
---|
269 | } |
---|
270 | } |
---|
271 | |
---|
272 | /* |
---|
273 | * bsp_start |
---|
274 | * |
---|
275 | * This routine does the bulk of the system initialization. |
---|
276 | */ |
---|
277 | |
---|
278 | void bsp_start( void ) |
---|
279 | { |
---|
280 | rtems_status_code sc = RTEMS_SUCCESSFUL; |
---|
281 | uintptr_t intrStackStart; |
---|
282 | uintptr_t intrStackSize; |
---|
283 | ppc_cpu_id_t myCpu; |
---|
284 | ppc_cpu_revision_t myCpuRevision; |
---|
285 | Triv121PgTbl pt=0; /* R = e; */ |
---|
286 | |
---|
287 | /* |
---|
288 | * Get CPU identification dynamically. Note that the get_ppc_cpu_type() |
---|
289 | * function store the result in global variables so that it can be used |
---|
290 | * latter... |
---|
291 | */ |
---|
292 | BSP_Increment_Light(); |
---|
293 | myCpu = get_ppc_cpu_type(); |
---|
294 | myCpuRevision = get_ppc_cpu_revision(); |
---|
295 | |
---|
296 | EUMBBAR = get_eumbbar(); |
---|
297 | printk("EUMBBAR 0x%08x\n", EUMBBAR ); |
---|
298 | |
---|
299 | /* |
---|
300 | * Note this sets BSP_processor_frequency based upon register settings. |
---|
301 | * It must be done prior to setting up hooks. |
---|
302 | */ |
---|
303 | Read_ep1a_config_registers( myCpu ); |
---|
304 | |
---|
305 | bsp_clicks_per_usec = BSP_processor_frequency/(BSP_time_base_divisor * 1000); |
---|
306 | |
---|
307 | ShowBATS(); |
---|
308 | #if 0 /* XXX - Add back in cache enable when we get this up and running!! */ |
---|
309 | /* |
---|
310 | * enables L1 Cache. Note that the L1_caches_enables() codes checks for |
---|
311 | * relevant CPU type so that the reason why there is no use of myCpu... |
---|
312 | */ |
---|
313 | L1_caches_enables(); |
---|
314 | #endif |
---|
315 | |
---|
316 | /* |
---|
317 | * Initialize the interrupt related settings. |
---|
318 | */ |
---|
319 | intrStackStart = (uintptr_t) __rtems_end; |
---|
320 | intrStackSize = rtems_configuration_get_interrupt_stack_size(); |
---|
321 | |
---|
322 | /* |
---|
323 | * Initialize default raw exception hanlders. |
---|
324 | */ |
---|
325 | sc = ppc_exc_initialize( |
---|
326 | PPC_INTERRUPT_DISABLE_MASK_DEFAULT, |
---|
327 | intrStackStart, |
---|
328 | intrStackSize |
---|
329 | ); |
---|
330 | if (sc != RTEMS_SUCCESSFUL) { |
---|
331 | BSP_panic("cannot initialize exceptions"); |
---|
332 | } |
---|
333 | |
---|
334 | /* |
---|
335 | * Init MMU block address translation to enable hardware |
---|
336 | * access |
---|
337 | */ |
---|
338 | setdbat(1, 0xf0000000, 0xf0000000, 0x10000000, IO_PAGE); |
---|
339 | setdbat(3, 0x90000000, 0x90000000, 0x10000000, IO_PAGE); |
---|
340 | |
---|
341 | |
---|
342 | #ifdef SHOW_MORE_INIT_SETTINGS |
---|
343 | printk("Going to start PCI buses scanning and initialization\n"); |
---|
344 | #endif |
---|
345 | pci_initialize(); |
---|
346 | |
---|
347 | #ifdef SHOW_MORE_INIT_SETTINGS |
---|
348 | printk("Number of PCI buses found is : %d\n", pci_bus_count()); |
---|
349 | #endif |
---|
350 | #ifdef TEST_RAW_EXCEPTION_CODE |
---|
351 | printk("Testing exception handling Part 1\n"); |
---|
352 | |
---|
353 | /* |
---|
354 | * Cause a software exception |
---|
355 | */ |
---|
356 | __asm__ __volatile ("sc"); |
---|
357 | |
---|
358 | /* |
---|
359 | * Check we can still catch exceptions and returned coorectly. |
---|
360 | */ |
---|
361 | printk("Testing exception handling Part 2\n"); |
---|
362 | __asm__ __volatile ("sc"); |
---|
363 | #endif |
---|
364 | |
---|
365 | /* |
---|
366 | * Initalize RTEMS IRQ system |
---|
367 | */ |
---|
368 | BSP_rtems_irq_mng_init(0); |
---|
369 | |
---|
370 | /* Activate the page table mappings only after |
---|
371 | * initializing interrupts because the irq_mng_init() |
---|
372 | * routine needs to modify the text |
---|
373 | */ |
---|
374 | if (pt) { |
---|
375 | #ifdef SHOW_MORE_INIT_SETTINGS |
---|
376 | printk("Page table setup finished; will activate it NOW...\n"); |
---|
377 | #endif |
---|
378 | BSP_pgtbl_activate(pt); |
---|
379 | } |
---|
380 | |
---|
381 | /* |
---|
382 | * Initialize VME bridge - needs working PCI |
---|
383 | * and IRQ subsystems... |
---|
384 | */ |
---|
385 | #ifdef SHOW_MORE_INIT_SETTINGS |
---|
386 | printk("Going to initialize VME bridge\n"); |
---|
387 | #endif |
---|
388 | /* VME initialization is in a separate file so apps which don't use |
---|
389 | * VME or want a different configuration may link against a customized |
---|
390 | * routine. |
---|
391 | */ |
---|
392 | BSP_vme_config(); |
---|
393 | |
---|
394 | #ifdef SHOW_MORE_INIT_SETTINGS |
---|
395 | ShowBATS(); |
---|
396 | printk("Exit from bspstart\n"); |
---|
397 | #endif |
---|
398 | } |
---|