source: rtems/c/src/lib/libbsp/powerpc/ep1a/irq/openpic_xxx_irq.c @ e160e41

4.11
Last change on this file since e160e41 was e160e41, checked in by Joel Sherrill <joel.sherrill@…>, on Oct 9, 2014 at 8:15:55 PM

powerpc/ep1a: Remove if 0 sections

There may be useful nuggets for debug and alternate configurations
in this code. There may be methods directly called by the application
which are beyond normal APIs. We have no way of knowing this based
on the comments in these files. There were no public prototypes
so the routines and code in question should have be unused private
methods.

These will always be in the source code control system as a deletion.
If some of the code is needed, justify it and provide a patch to restore
it along with a prototype in a public place if needed and a better name.

  • Property mode set to 100644
File size: 6.6 KB
Line 
1/*
2 *  This file contains the i8259/openpic-specific implementation of
3 *  the function described in irq.h
4 *
5 *  Copyright (C) 1998, 1999 valette@crf.canon.fr
6 *
7 *  The license and distribution terms for this file may be
8 *  found in the file LICENSE in this distribution or at
9 *  http://www.rtems.org/license/LICENSE.
10 */
11
12#include <stdlib.h>
13
14#include <bsp.h>
15#include <bsp/irq.h>
16#include <bsp/irq_supp.h>
17#include <bsp/VMEConfig.h>
18#include <bsp/openpic.h>
19#include <libcpu/io.h>
20#include <bsp/vectors.h>
21#include <stdlib.h>
22
23#include <rtems/bspIo.h> /* for printk */
24#define RAVEN_INTR_ACK_REG 0xfeff0030
25
26#ifdef BSP_PCI_ISA_BRIDGE_IRQ
27/*
28 * pointer to the mask representing the additionnal irq vectors
29 * that must be disabled when a particular entry is activated.
30 * They will be dynamically computed from the priority table given
31 * in BSP_rtems_irq_mngt_set();
32 * CAUTION : this table is accessed directly by interrupt routine
33 *           prologue.
34 */
35rtems_i8259_masks       irq_mask_or_tbl[BSP_IRQ_NUMBER];
36#endif
37
38/*
39 * default handler connected on each irq after bsp initialization
40 */
41static rtems_irq_connect_data   default_rtems_entry;
42
43static rtems_irq_connect_data*          rtems_hdl_tbl;
44
45#ifdef BSP_PCI_ISA_BRIDGE_IRQ
46/*
47 * Check if IRQ is an ISA IRQ
48 */
49static inline int is_isa_irq(const rtems_irq_number irqLine)
50{
51  return (((int) irqLine <= BSP_ISA_IRQ_MAX_OFFSET) &
52          ((int) irqLine >= BSP_ISA_IRQ_LOWEST_OFFSET)
53         );
54}
55#endif
56
57/*
58 * Check if IRQ is an OPENPIC IRQ
59 */
60static inline int is_pci_irq(const rtems_irq_number irqLine)
61{
62  return (((int) irqLine <= BSP_PCI_IRQ_MAX_OFFSET) &
63          ((int) irqLine >= BSP_PCI_IRQ_LOWEST_OFFSET)
64         );
65}
66
67/*
68 * ------------------------ RTEMS Irq helper functions ----------------
69 */
70
71#ifdef BSP_PCI_ISA_BRIDGE_IRQ
72/*
73 * Caution : this function assumes the variable "*config"
74 * is already set and that the tables it contains are still valid
75 * and accessible.
76 */
77static void compute_i8259_masks_from_prio (rtems_irq_global_settings* config)
78{
79  int i;
80  int j;
81  /*
82   * Always mask at least current interrupt to prevent re-entrance
83   */
84  for (i=BSP_ISA_IRQ_LOWEST_OFFSET; i < BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER; i++) {
85    * ((unsigned short*) &irq_mask_or_tbl[i]) = (1 << i);
86    for (j = BSP_ISA_IRQ_LOWEST_OFFSET; j < BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER; j++) {
87      /*
88       * Mask interrupts at i8259 level that have a lower priority
89       */
90      if (config->irqPrioTbl [i] > config->irqPrioTbl [j]) {
91        * ((unsigned short*) &irq_mask_or_tbl[i]) |= (1 << j);
92      }
93    }
94  }
95}
96#endif
97
98void
99BSP_enable_irq_at_pic(const rtems_irq_number name)
100{
101#ifdef BSP_PCI_ISA_BRIDGE_IRQ
102    if (is_isa_irq(name)) {
103      /*
104       * Enable interrupt at PIC level
105       */
106printk("ERROR BSP_irq_enable_at_i8259s Being Called for %d\n", (int)name);
107      BSP_irq_enable_at_i8259s ((int) name);
108    }
109#endif
110
111    if (is_pci_irq(name)) {
112      /*
113       * Enable interrupt at OPENPIC level
114       */
115printk(" openpic_enable_irq %d\n", (int)name );
116       openpic_enable_irq ((int) name);
117    }
118}
119
120int
121BSP_disable_irq_at_pic(const rtems_irq_number name)
122{
123#ifdef BSP_PCI_ISA_BRIDGE_IRQ
124    if (is_isa_irq(name)) {
125      /*
126       * disable interrupt at PIC level
127       */
128      return BSP_irq_disable_at_i8259s ((int) name);
129    }
130#endif
131    if (is_pci_irq(name)) {
132      /*
133       * disable interrupt at OPENPIC level
134       */
135      return openpic_disable_irq ((int) name );
136    }
137        return -1;
138}
139
140/*
141 * RTEMS Global Interrupt Handler Management Routines
142 */
143int BSP_setup_the_pic(rtems_irq_global_settings* config)
144{
145    int i;
146   /*
147    * Store various code accelerators
148    */
149    default_rtems_entry = config->defaultEntry;
150    rtems_hdl_tbl               = config->irqHdlTbl;
151
152    /*
153     * continue with PCI IRQ
154     */
155    for (i=BSP_PCI_IRQ_LOWEST_OFFSET; i < BSP_PCI_IRQ_LOWEST_OFFSET + BSP_PCI_IRQ_NUMBER ; i++) {
156      /*
157       * Note that openpic_set_priority() sets the TASK priority of the PIC
158       */
159      openpic_set_source_priority(i - BSP_PCI_IRQ_LOWEST_OFFSET,
160                                  config->irqPrioTbl[i]);
161      if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) {
162         openpic_enable_irq ((int) i );
163      }
164      else {
165         openpic_disable_irq ((int) i );
166      }
167    }
168
169#ifdef BSP_PCI_ISA_BRIDGE_IRQ
170        if ( BSP_ISA_IRQ_NUMBER > 0 ) {
171        /*
172             * Must enable PCI/ISA bridge IRQ
173             */
174        openpic_enable_irq (0);
175        }
176#endif
177
178    return 1;
179}
180
181int _BSP_vme_bridge_irq = -1;
182
183unsigned BSP_spuriousIntr = 0;
184
185/*
186 * High level IRQ handler called from shared_raw_irq_code_entry
187 */
188int C_dispatch_irq_handler (BSP_Exception_frame *frame, unsigned int excNum)
189{
190  register unsigned int irq;
191#ifdef BSP_PCI_ISA_BRIDGE_IRQ
192  register unsigned isaIntr;                  /* boolean */
193  register unsigned oldMask = 0;              /* old isa pic masks */
194  register unsigned newMask;                  /* new isa pic masks */
195#endif
196
197  if (excNum == ASM_DEC_VECTOR) {
198/* printk("ASM_DEC_VECTOR\n"); */
199        bsp_irq_dispatch_list(rtems_hdl_tbl, BSP_DECREMENTER, default_rtems_entry.hdl);
200
201    return 0;
202
203  }
204  irq = openpic_irq(0);
205  if (irq == OPENPIC_VEC_SPURIOUS) {
206/* printk("OPENPIC_VEC_SPURIOUS interrupt %d\n", OPENPIC_VEC_SPURIOUS ); */
207     ++BSP_spuriousIntr;
208    return 0;
209  }
210
211  /* some BSPs might want to use a different numbering... */
212  irq = irq - OPENPIC_VEC_SOURCE + BSP_PCI_IRQ_LOWEST_OFFSET;
213/* printk("OpenPic Irq: %d\n", irq); */
214
215#ifdef BSP_PCI_ISA_BRIDGE_IRQ
216  isaIntr = (irq == BSP_PCI_ISA_BRIDGE_IRQ);
217  if (isaIntr)  {
218/* printk("BSP_PCI_ISA_BRIDGE_IRQ\n"); */
219    /*
220     * Acknowledge and read 8259 vector
221     */
222    irq = (unsigned int) (*(unsigned char *) RAVEN_INTR_ACK_REG);
223    /*
224     * store current PIC mask
225     */
226    oldMask = i8259s_cache;
227    newMask = oldMask | irq_mask_or_tbl [irq];
228    i8259s_cache = newMask;
229    outport_byte(PIC_MASTER_IMR_IO_PORT, i8259s_cache & 0xff);
230    outport_byte(PIC_SLAVE_IMR_IO_PORT, ((i8259s_cache & 0xff00) >> 8));
231    BSP_irq_ack_at_i8259s (irq);
232    openpic_eoi(0);
233  }
234#endif
235
236
237  /* dispatch handlers */
238/* printk("dispatch\n"); */
239irq -=16;
240  bsp_irq_dispatch_list(rtems_hdl_tbl, irq, default_rtems_entry.hdl);
241/* printk("Back from dispatch\n"); */
242
243#ifdef BSP_PCI_ISA_BRIDGE_IRQ
244  if (isaIntr)  {\
245    i8259s_cache = oldMask;
246    outport_byte(PIC_MASTER_IMR_IO_PORT, i8259s_cache & 0xff);
247    outport_byte(PIC_SLAVE_IMR_IO_PORT, ((i8259s_cache & 0xff00) >> 8));
248  }
249  else
250#endif
251  {
252#ifdef BSP_PCI_VME_DRIVER_DOES_EOI
253        /* leave it to the VME bridge driver to do EOI, so
254     * it can re-enable the openpic while handling
255     * VME interrupts (-> VME priorities in software)
256         */
257        if (_BSP_vme_bridge_irq != irq)
258#endif
259                openpic_eoi(0);
260  }
261  return 0;
262}
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