source: rtems/c/src/lib/libbsp/powerpc/ep1a/irq/irq_init.c @ fb557a9

4.9
Last change on this file since fb557a9 was fb557a9, checked in by Joel Sherrill <joel.sherrill@…>, on 10/16/09 at 16:42:03

2009-10-16 Jennifer Averett <jennifer@…>

  • Makefile.am, configure.ac, preinstall.am, console/alloc360.c, console/config.c, console/console.c, console/m68360.h, console/mc68360_scc.c, console/rsPMCQ1.c, console/rsPMCQ1.h, include/bsp.h, irq/irq_init.c, irq/openpic_xxx_irq.c, start/start.S, startup/bspstart.c, startup/linkcmds, vme/VMEConfig.h: Updated and tested against RTEMS 4.9. Updated README file to latest source status. Modified to use the shared irq source code. Turned off debugging, cleaned up warnings, removed unused code. Tested with two PMCQ1 serial cards. Tested MC68360 serial ports and VME using external tests.
  • README, irq/irq.h, vme/vmeconfig.c: New files.
  • Property mode set to 100644
File size: 8.0 KB
Line 
1/* irq_init.c
2 *
3 *  This file contains the implementation of rtems initialization
4 *  related to interrupt handling.
5 *
6 *  CopyRight (C) 1999 valette@crf.canon.fr
7 *
8 *  Enhanced by Jay Kulpinski <jskulpin@eng01.gdds.com>
9 *  to make it valid for MVME2300 Motorola boards.
10 *
11 *  Till Straumann <strauman@slac.stanford.edu>, 12/20/2001:
12 *  Use the new interface to openpic_init
13 *
14 *  COPYRIGHT (c) 1989-2009.
15 *  On-Line Applications Research Corporation (OAR).
16 *
17 *  The license and distribution terms for this file may be
18 *  found in the file LICENSE in this distribution or at
19 *  http://www.rtems.com/license/LICENSE.
20 *
21 *  $Id$
22 */
23
24#include <libcpu/io.h>
25#include <libcpu/spr.h>
26#include <bsp/pci.h>
27#include <bsp/residual.h>
28#include <bsp/openpic.h>
29#include <bsp/irq.h>
30#include <bsp.h>
31#include <libcpu/raw_exception.h>
32#include <bsp/motorola.h>
33#include <rtems/bspIo.h>
34
35#if 0
36#define TRACE_IRQ_INIT 1   /* XXX */
37#endif
38
39typedef struct {
40  unsigned char bus;    /* few chance the PCI/ISA bridge is not on first bus but ... */
41  unsigned char device;
42  unsigned char function;
43} pci_isa_bridge_device;
44
45pci_isa_bridge_device* via_82c586 = 0;
46#if 0
47static pci_isa_bridge_device bridge;
48#endif
49
50
51
52extern unsigned int external_exception_vector_prolog_code_size[];
53extern void external_exception_vector_prolog_code();
54extern unsigned int decrementer_exception_vector_prolog_code_size[];
55extern void decrementer_exception_vector_prolog_code();
56
57
58static void IRQ_Default_rtems_irq_hdl( rtems_irq_hdl_param ptr ) { printk("IRQ_Default_rtems_irq_hdl\n"); }
59static void IRQ_Default_rtems_irq_enable (const struct __rtems_irq_connect_data__ *ptr)   {}
60static void IRQ_Default_rtems_irq_disable(const struct __rtems_irq_connect_data__ *ptr)   {}
61static int  IRQ_Default_rtems_irq_is_enabled(const struct __rtems_irq_connect_data__ *ptr){ return 1; }
62static rtems_irq_connect_data           rtemsIrq[BSP_IRQ_NUMBER];
63static rtems_irq_global_settings        initial_config;
64static rtems_irq_connect_data           defaultIrq = {
65/*name,  hdl                            handle  on                              off                             isOn */
66  0,     IRQ_Default_rtems_irq_hdl,     NULL,   IRQ_Default_rtems_irq_enable,   IRQ_Default_rtems_irq_disable,  IRQ_Default_rtems_irq_is_enabled
67};
68
69
70/*
71 *  If the BSP_IRQ_NUMBER changes the following if will force the tables to be corrected.
72 */
73#if ( (BSP_ISA_IRQ_NUMBER == 16)      && \
74      (BSP_PCI_IRQ_NUMBER == 26)      && \
75      (BSP_PROCESSOR_IRQ_NUMBER == 1) && \
76      (BSP_MISC_IRQ_NUMBER == 8) )
77
78
79static rtems_irq_prio irqPrioTable[BSP_IRQ_NUMBER]={
80  /*
81   * ISA interrupts.
82   */
83  0, 0,
84  (OPENPIC_NUM_PRI-1),
85  0, 0, 0, 0,  0,  0,  0,  0,  0,  0,  0,  0,  0,
86
87  /*
88   * PCI Interrupts
89   */
90  8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
91  8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
92
93  /*
94   * Processor exceptions handled as interrupts
95   */
96  8,
97 
98  8, 8, 8, 8, 8, 8, 8, 8
99};
100
101static unsigned char mpc8245_openpic_initpolarities[] = {
102    1,  /*  0 8259 cascade */
103    0,  /*  1 */
104    0,  /*  2 */
105    0,  /*  3 */
106    0,  /*  4 */
107    0,  /*  5 */
108    0,  /*  6 */
109    0,  /*  7 */
110    0,  /*  8 */
111    0,  /*  9 */
112    0,  /* 10 */
113    0,  /* 11 */
114    0,  /* 12 */
115    0,  /* 13 */
116    0,  /* 14 */
117    0,  /* 15 */
118    0,  /* 16 */
119    0,  /* 17 */
120    1,  /* 18 all the rest of them */
121    1,  /* 19 all the rest of them */
122    1,  /* 20 all the rest of them */
123    1,  /* 21 all the rest of them */
124    1,  /* 22 all the rest of them */
125    1,  /* 23 all the rest of them */
126    1,  /* 24 all the rest of them */
127    1,  /* 25 all the rest of them */
128    1,  /* 26 all the rest of them */
129    1,  /* 27 all the rest of them */
130    1,  /* 28 all the rest of them */
131    1,  /* 29 all the rest of them */
132    1,  /* 30 all the rest of them */
133    1,  /* 31 all the rest of them */
134    1,  /* 32 all the rest of them */
135    1,  /* 33 all the rest of them */
136    1,  /* 34 all the rest of them */
137    1,  /* 35 all the rest of them */
138    1,  /* 36 all the rest of them */
139    1,  /* 37 all the rest of them */
140    1,  /* 38 all the rest of them */
141    1,  /* 39 all the rest of them */
142    1,  /* 40 all the rest of them */
143    1,  /* 41 all the rest of them */
144    1,  /* 42 all the rest of them */
145    1,  /* 43 all the rest of them */
146    1,  /* 44 all the rest of them */
147    1,  /* 45 all the rest of them */
148    1,  /* 46 all the rest of them */
149    1,  /* 47 all the rest of them */
150    1,  /* 48 all the rest of them */
151    1,  /* 49 all the rest of them */
152    1,  /* 50 all the rest of them */
153    1,  /* 51 all the rest of them */
154
155};
156
157static unsigned char mpc8245_openpic_initsenses[] = {
158    1,  /* 0  */
159    0,  /* 1  */
160    1,  /* 2  */
161    1,  /* 3  */
162    1,  /* 4  */
163    1,  /* 5  */
164    1,  /* 6  */
165    1,  /* 7  */
166    1,  /* 8  */
167    1,  /* 9  */
168    1,  /*10  */
169    1,  /*11  */
170    1,  /*12  */
171    1,  /*13  */
172    1,  /*14  */
173    1,  /*15  */
174    1,
175    1,
176    1,
177    1,
178    1,
179    1,
180    1,
181    1,
182    1,
183    1,
184    1,
185    1,
186    1,
187    1,
188    1,
189    1,
190    1,
191    1,
192    1,
193    1,
194    1,
195    1,
196    1,
197    1,
198    1,
199    1,
200    1,
201    1,
202    1,
203    1,
204    1,
205    1,
206    1,
207    1,
208    1,
209    1
210};
211#endif
212
213  /*
214   * This code assumes the exceptions management setup has already
215   * been done. We just need to replace the exceptions that will
216   * be handled like interrupt. On mcp750/mpc750 and many PPC processors
217   * this means the decrementer exception and the external exception.
218   */
219void BSP_rtems_irq_mng_init(unsigned cpuId)
220{
221  int                           i;
222
223  /*
224   * First initialize the Interrupt management hardware
225   */
226#ifdef TRACE_IRQ_INIT 
227  uint32_t                      msr;
228
229  _CPU_MSR_GET( msr );
230  printk("BSP_rtems_irq_mng_init: Initialize openpic compliant device with MSR %x \n", msr);
231  printk(" BSP_ISA_IRQ_NUMBER %d\n",BSP_ISA_IRQ_NUMBER );
232  printk(" BSP_ISA_IRQ_LOWEST_OFFSET %d\n",BSP_ISA_IRQ_LOWEST_OFFSET );
233  printk(" BSP_ISA_IRQ_MAX_OFFSET %d\n", BSP_ISA_IRQ_MAX_OFFSET);
234  printk(" BSP_PCI_IRQ_NUMBER %d\n",BSP_PCI_IRQ_NUMBER );
235  printk(" BSP_PCI_IRQ_LOWEST_OFFSET %d\n",BSP_PCI_IRQ_LOWEST_OFFSET );
236  printk(" BSP_PCI_IRQ_MAX_OFFSET %d\n",BSP_PCI_IRQ_MAX_OFFSET );
237  printk(" BSP_PROCESSOR_IRQ_NUMBER %d\n",BSP_PROCESSOR_IRQ_NUMBER );
238  printk(" BSP_PROCESSOR_IRQ_LOWEST_OFFSET %d\n",BSP_PROCESSOR_IRQ_LOWEST_OFFSET );
239  printk(" BSP_PROCESSOR_IRQ_MAX_OFFSET %d\n", BSP_PROCESSOR_IRQ_MAX_OFFSET);
240  printk(" BSP_MISC_IRQ_NUMBER %d\n", BSP_MISC_IRQ_NUMBER);
241  printk(" BSP_MISC_IRQ_LOWEST_OFFSET %d\n", BSP_MISC_IRQ_LOWEST_OFFSET);
242  printk(" BSP_MISC_IRQ_MAX_OFFSET %d\n",BSP_MISC_IRQ_MAX_OFFSET );
243  printk(" BSP_IRQ_NUMBER %d\n",BSP_IRQ_NUMBER );
244  printk(" BSP_LOWEST_OFFSET %d\n",BSP_LOWEST_OFFSET );
245  printk(" BSP_MAX_OFFSET %d\n",BSP_MAX_OFFSET );
246#endif
247       
248  /* FIXME (t.s.): we should probably setup the EOI delay by
249   * passing a non-zero 'epic_freq' argument (frequency of the
250   * EPIC serial interface) but I don't know the value on this
251   * board (8245 SDRAM freq, IIRC)...
252   *
253   * When tested this appears to work correctly.
254   */
255  openpic_init(1, mpc8245_openpic_initpolarities, mpc8245_openpic_initsenses, 0, 0, 0);
256
257  /*
258   * Initialize Rtems management interrupt table
259   */
260    /*
261     * re-init the rtemsIrq table
262     */
263    for (i = 0; i < BSP_IRQ_NUMBER; i++) {
264      rtemsIrq[i]      = defaultIrq;
265      rtemsIrq[i].name = i;
266#ifdef BSP_SHARED_HANDLER_SUPPORT
267      rtemsIrq[i].next_handler = NULL;
268#endif
269    }
270
271    /*
272     * Init initial Interrupt management config
273     */
274    initial_config.irqNb        = BSP_IRQ_NUMBER;
275    initial_config.defaultEntry = defaultIrq;
276    initial_config.irqHdlTbl    = rtemsIrq;
277    initial_config.irqBase      = BSP_LOWEST_OFFSET;
278    initial_config.irqPrioTbl   = irqPrioTable;
279
280
281#ifdef TRACE_IRQ_INIT 
282    _CPU_MSR_GET( msr );
283    printk("BSP_rtems_irq_mng_init: Set initial configuration with MSR %x\n", msr);
284#endif
285    if (!BSP_rtems_irq_mngt_set(&initial_config)) {
286      /*
287       * put something here that will show the failure...
288       */
289      BSP_panic("Unable to initialize RTEMS interrupt Management!!! System locked\n");
290    }  else {
291      printk(" Initialized RTEMS Interrupt Manager\n");
292    }
293
294#ifdef TRACE_IRQ_INIT 
295    printk("RTEMS IRQ management is now operationnal\n");
296#endif
297}
298
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