1 | /* irq_init.c |
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2 | * |
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3 | * This file contains the implementation of rtems initialization |
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4 | * related to interrupt handling. |
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5 | * |
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6 | * CopyRight (C) 1999 valette@crf.canon.fr |
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7 | * |
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8 | * Enhanced by Jay Kulpinski <jskulpin@eng01.gdds.com> |
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9 | * to make it valid for MVME2300 Motorola boards. |
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10 | * |
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11 | * Till Straumann <strauman@slac.stanford.edu>, 12/20/2001: |
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12 | * Use the new interface to openpic_init |
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13 | * |
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14 | * COPYRIGHT (c) 1989-2009. |
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15 | * On-Line Applications Research Corporation (OAR). |
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16 | * |
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17 | * The license and distribution terms for this file may be |
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18 | * found in the file LICENSE in this distribution or at |
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19 | * http://www.rtems.com/license/LICENSE. |
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20 | * |
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21 | * $Id$ |
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22 | */ |
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23 | |
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24 | #include <libcpu/io.h> |
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25 | #include <libcpu/spr.h> |
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26 | #include <bsp/pci.h> |
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27 | #include <bsp/residual.h> |
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28 | #include <bsp/openpic.h> |
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29 | #include <bsp/irq.h> |
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30 | #include <bsp.h> |
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31 | #include <libcpu/raw_exception.h> |
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32 | #include <bsp/motorola.h> |
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33 | #include <rtems/bspIo.h> |
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34 | |
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35 | #if 0 |
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36 | #define TRACE_IRQ_INIT 1 /* XXX */ |
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37 | #endif |
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38 | |
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39 | typedef struct { |
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40 | unsigned char bus; /* few chance the PCI/ISA bridge is not on first bus but ... */ |
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41 | unsigned char device; |
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42 | unsigned char function; |
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43 | } pci_isa_bridge_device; |
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44 | |
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45 | pci_isa_bridge_device* via_82c586 = 0; |
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46 | #if 0 |
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47 | static pci_isa_bridge_device bridge; |
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48 | #endif |
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49 | |
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50 | |
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51 | |
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52 | extern unsigned int external_exception_vector_prolog_code_size[]; |
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53 | extern void external_exception_vector_prolog_code(); |
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54 | extern unsigned int decrementer_exception_vector_prolog_code_size[]; |
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55 | extern void decrementer_exception_vector_prolog_code(); |
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56 | |
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57 | |
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58 | static void IRQ_Default_rtems_irq_hdl( rtems_irq_hdl_param ptr ) { printk("IRQ_Default_rtems_irq_hdl\n"); } |
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59 | static void IRQ_Default_rtems_irq_enable (const struct __rtems_irq_connect_data__ *ptr) {} |
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60 | static void IRQ_Default_rtems_irq_disable(const struct __rtems_irq_connect_data__ *ptr) {} |
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61 | static int IRQ_Default_rtems_irq_is_enabled(const struct __rtems_irq_connect_data__ *ptr){ return 1; } |
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62 | static rtems_irq_connect_data rtemsIrq[BSP_IRQ_NUMBER]; |
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63 | static rtems_irq_global_settings initial_config; |
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64 | static rtems_irq_connect_data defaultIrq = { |
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65 | /*name, hdl handle on off isOn */ |
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66 | 0, IRQ_Default_rtems_irq_hdl, NULL, IRQ_Default_rtems_irq_enable, IRQ_Default_rtems_irq_disable, IRQ_Default_rtems_irq_is_enabled |
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67 | }; |
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68 | |
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69 | |
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70 | /* |
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71 | * If the BSP_IRQ_NUMBER changes the following if will force the tables to be corrected. |
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72 | */ |
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73 | #if ( (BSP_ISA_IRQ_NUMBER == 16) && \ |
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74 | (BSP_PCI_IRQ_NUMBER == 26) && \ |
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75 | (BSP_PROCESSOR_IRQ_NUMBER == 1) && \ |
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76 | (BSP_MISC_IRQ_NUMBER == 8) ) |
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77 | |
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78 | |
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79 | static rtems_irq_prio irqPrioTable[BSP_IRQ_NUMBER]={ |
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80 | /* |
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81 | * ISA interrupts. |
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82 | */ |
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83 | 0, 0, |
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84 | (OPENPIC_NUM_PRI-1), |
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85 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
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86 | |
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87 | /* |
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88 | * PCI Interrupts |
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89 | */ |
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90 | 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, |
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91 | 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, |
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92 | |
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93 | /* |
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94 | * Processor exceptions handled as interrupts |
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95 | */ |
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96 | 8, |
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97 | |
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98 | 8, 8, 8, 8, 8, 8, 8, 8 |
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99 | }; |
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100 | |
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101 | static unsigned char mpc8245_openpic_initpolarities[] = { |
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102 | 1, /* 0 8259 cascade */ |
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103 | 0, /* 1 */ |
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104 | 0, /* 2 */ |
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105 | 0, /* 3 */ |
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106 | 0, /* 4 */ |
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107 | 0, /* 5 */ |
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108 | 0, /* 6 */ |
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109 | 0, /* 7 */ |
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110 | 0, /* 8 */ |
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111 | 0, /* 9 */ |
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112 | 0, /* 10 */ |
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113 | 0, /* 11 */ |
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114 | 0, /* 12 */ |
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115 | 0, /* 13 */ |
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116 | 0, /* 14 */ |
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117 | 0, /* 15 */ |
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118 | 0, /* 16 */ |
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119 | 0, /* 17 */ |
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120 | 1, /* 18 all the rest of them */ |
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121 | 1, /* 19 all the rest of them */ |
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122 | 1, /* 20 all the rest of them */ |
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123 | 1, /* 21 all the rest of them */ |
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124 | 1, /* 22 all the rest of them */ |
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125 | 1, /* 23 all the rest of them */ |
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126 | 1, /* 24 all the rest of them */ |
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127 | 1, /* 25 all the rest of them */ |
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128 | 1, /* 26 all the rest of them */ |
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129 | 1, /* 27 all the rest of them */ |
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130 | 1, /* 28 all the rest of them */ |
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131 | 1, /* 29 all the rest of them */ |
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132 | 1, /* 30 all the rest of them */ |
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133 | 1, /* 31 all the rest of them */ |
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134 | 1, /* 32 all the rest of them */ |
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135 | 1, /* 33 all the rest of them */ |
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136 | 1, /* 34 all the rest of them */ |
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137 | 1, /* 35 all the rest of them */ |
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138 | 1, /* 36 all the rest of them */ |
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139 | 1, /* 37 all the rest of them */ |
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140 | 1, /* 38 all the rest of them */ |
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141 | 1, /* 39 all the rest of them */ |
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142 | 1, /* 40 all the rest of them */ |
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143 | 1, /* 41 all the rest of them */ |
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144 | 1, /* 42 all the rest of them */ |
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145 | 1, /* 43 all the rest of them */ |
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146 | 1, /* 44 all the rest of them */ |
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147 | 1, /* 45 all the rest of them */ |
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148 | 1, /* 46 all the rest of them */ |
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149 | 1, /* 47 all the rest of them */ |
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150 | 1, /* 48 all the rest of them */ |
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151 | 1, /* 49 all the rest of them */ |
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152 | 1, /* 50 all the rest of them */ |
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153 | 1, /* 51 all the rest of them */ |
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154 | |
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155 | }; |
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156 | |
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157 | static unsigned char mpc8245_openpic_initsenses[] = { |
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158 | 1, /* 0 */ |
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159 | 0, /* 1 */ |
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160 | 1, /* 2 */ |
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161 | 1, /* 3 */ |
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162 | 1, /* 4 */ |
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163 | 1, /* 5 */ |
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164 | 1, /* 6 */ |
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165 | 1, /* 7 */ |
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166 | 1, /* 8 */ |
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167 | 1, /* 9 */ |
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168 | 1, /*10 */ |
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169 | 1, /*11 */ |
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170 | 1, /*12 */ |
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171 | 1, /*13 */ |
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172 | 1, /*14 */ |
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173 | 1, /*15 */ |
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174 | 1, |
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175 | 1, |
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176 | 1, |
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177 | 1, |
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178 | 1, |
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179 | 1, |
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180 | 1, |
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181 | 1, |
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182 | 1, |
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183 | 1, |
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184 | 1, |
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185 | 1, |
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186 | 1, |
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187 | 1, |
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188 | 1, |
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189 | 1, |
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190 | 1, |
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191 | 1, |
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192 | 1, |
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193 | 1, |
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194 | 1, |
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195 | 1, |
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196 | 1, |
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197 | 1, |
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198 | 1, |
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199 | 1, |
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200 | 1, |
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201 | 1, |
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202 | 1, |
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203 | 1, |
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204 | 1, |
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205 | 1, |
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206 | 1, |
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207 | 1, |
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208 | 1, |
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209 | 1 |
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210 | }; |
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211 | #endif |
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212 | |
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213 | /* |
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214 | * This code assumes the exceptions management setup has already |
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215 | * been done. We just need to replace the exceptions that will |
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216 | * be handled like interrupt. On mcp750/mpc750 and many PPC processors |
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217 | * this means the decrementer exception and the external exception. |
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218 | */ |
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219 | void BSP_rtems_irq_mng_init(unsigned cpuId) |
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220 | { |
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221 | int i; |
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222 | |
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223 | /* |
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224 | * First initialize the Interrupt management hardware |
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225 | */ |
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226 | #ifdef TRACE_IRQ_INIT |
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227 | uint32_t msr; |
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228 | |
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229 | _CPU_MSR_GET( msr ); |
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230 | printk("BSP_rtems_irq_mng_init: Initialize openpic compliant device with MSR %x \n", msr); |
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231 | printk(" BSP_ISA_IRQ_NUMBER %d\n",BSP_ISA_IRQ_NUMBER ); |
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232 | printk(" BSP_ISA_IRQ_LOWEST_OFFSET %d\n",BSP_ISA_IRQ_LOWEST_OFFSET ); |
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233 | printk(" BSP_ISA_IRQ_MAX_OFFSET %d\n", BSP_ISA_IRQ_MAX_OFFSET); |
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234 | printk(" BSP_PCI_IRQ_NUMBER %d\n",BSP_PCI_IRQ_NUMBER ); |
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235 | printk(" BSP_PCI_IRQ_LOWEST_OFFSET %d\n",BSP_PCI_IRQ_LOWEST_OFFSET ); |
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236 | printk(" BSP_PCI_IRQ_MAX_OFFSET %d\n",BSP_PCI_IRQ_MAX_OFFSET ); |
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237 | printk(" BSP_PROCESSOR_IRQ_NUMBER %d\n",BSP_PROCESSOR_IRQ_NUMBER ); |
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238 | printk(" BSP_PROCESSOR_IRQ_LOWEST_OFFSET %d\n",BSP_PROCESSOR_IRQ_LOWEST_OFFSET ); |
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239 | printk(" BSP_PROCESSOR_IRQ_MAX_OFFSET %d\n", BSP_PROCESSOR_IRQ_MAX_OFFSET); |
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240 | printk(" BSP_MISC_IRQ_NUMBER %d\n", BSP_MISC_IRQ_NUMBER); |
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241 | printk(" BSP_MISC_IRQ_LOWEST_OFFSET %d\n", BSP_MISC_IRQ_LOWEST_OFFSET); |
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242 | printk(" BSP_MISC_IRQ_MAX_OFFSET %d\n",BSP_MISC_IRQ_MAX_OFFSET ); |
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243 | printk(" BSP_IRQ_NUMBER %d\n",BSP_IRQ_NUMBER ); |
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244 | printk(" BSP_LOWEST_OFFSET %d\n",BSP_LOWEST_OFFSET ); |
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245 | printk(" BSP_MAX_OFFSET %d\n",BSP_MAX_OFFSET ); |
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246 | #endif |
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247 | |
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248 | /* FIXME (t.s.): we should probably setup the EOI delay by |
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249 | * passing a non-zero 'epic_freq' argument (frequency of the |
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250 | * EPIC serial interface) but I don't know the value on this |
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251 | * board (8245 SDRAM freq, IIRC)... |
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252 | * |
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253 | * When tested this appears to work correctly. |
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254 | */ |
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255 | openpic_init(1, mpc8245_openpic_initpolarities, mpc8245_openpic_initsenses, 0, 0, 0); |
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256 | |
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257 | /* |
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258 | * Initialize Rtems management interrupt table |
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259 | */ |
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260 | /* |
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261 | * re-init the rtemsIrq table |
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262 | */ |
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263 | for (i = 0; i < BSP_IRQ_NUMBER; i++) { |
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264 | rtemsIrq[i] = defaultIrq; |
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265 | rtemsIrq[i].name = i; |
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266 | #ifdef BSP_SHARED_HANDLER_SUPPORT |
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267 | rtemsIrq[i].next_handler = NULL; |
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268 | #endif |
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269 | } |
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270 | |
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271 | /* |
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272 | * Init initial Interrupt management config |
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273 | */ |
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274 | initial_config.irqNb = BSP_IRQ_NUMBER; |
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275 | initial_config.defaultEntry = defaultIrq; |
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276 | initial_config.irqHdlTbl = rtemsIrq; |
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277 | initial_config.irqBase = BSP_LOWEST_OFFSET; |
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278 | initial_config.irqPrioTbl = irqPrioTable; |
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279 | |
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280 | |
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281 | #ifdef TRACE_IRQ_INIT |
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282 | _CPU_MSR_GET( msr ); |
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283 | printk("BSP_rtems_irq_mng_init: Set initial configuration with MSR %x\n", msr); |
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284 | #endif |
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285 | if (!BSP_rtems_irq_mngt_set(&initial_config)) { |
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286 | /* |
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287 | * put something here that will show the failure... |
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288 | */ |
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289 | BSP_panic("Unable to initialize RTEMS interrupt Management!!! System locked\n"); |
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290 | } else { |
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291 | printk(" Initialized RTEMS Interrupt Manager\n"); |
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292 | } |
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293 | |
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294 | #ifdef TRACE_IRQ_INIT |
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295 | printk("RTEMS IRQ management is now operationnal\n"); |
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296 | #endif |
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297 | } |
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298 | |
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