source: rtems/c/src/lib/libbsp/powerpc/ep1a/irq/irq.c @ 41a4657

4.104.114.84.9
Last change on this file since 41a4657 was 41a4657, checked in by Jennifer Averett <Jennifer.Averett@…>, on May 17, 2005 at 2:58:28 PM

2005-05-17 Jennifer Averett <jennifer.averett@…>

  • console/rsPMCQ1.c, irq/irq.c: Modified to use rtems/irq.h.
  • Property mode set to 100644
File size: 13.8 KB
Line 
1/*
2 *
3 *  This file contains the implementation of the function described in irq.h
4 *
5 *  COPYRIGHT (c) 1989-1999.
6 *  On-Line Applications Research Corporation (OAR).
7 *
8 *  The license and distribution terms for this file may be
9 *  found in the file LICENSE in this distribution or at
10 *  http://www.rtems.com/license/LICENSE.
11 *
12 *  $Id$
13 */
14 
15#include <rtems/system.h>
16#include <bsp.h>
17#include <bsp/irq.h>
18#include <bsp/VME.h>
19#include <bsp/openpic.h>
20#include <rtems/score/thread.h>
21#include <rtems/score/apiext.h>
22#include <libcpu/raw_exception.h>
23#include <libcpu/io.h>
24#include <bsp/vectors.h>
25#include <stdlib.h>
26#include <rtems/bspIo.h> /* for printk */
27#define RAVEN_INTR_ACK_REG 0xfeff0030
28
29/*
30 * pointer to the mask representing the additionnal irq vectors
31 * that must be disabled when a particular entry is activated.
32 * They will be dynamically computed from teh prioruty table given
33 * in BSP_rtems_irq_mngt_set();
34 * CAUTION : this table is accessed directly by interrupt routine
35 *           prologue.
36 */
37rtems_i8259_masks       irq_mask_or_tbl[BSP_IRQ_NUMBER];
38/*
39 * default handler connected on each irq after bsp initialization
40 */
41static rtems_irq_connect_data   default_rtems_entry;
42
43/*
44 * location used to store initial tables used for interrupt
45 * management.
46 */
47static rtems_irq_global_settings*       internal_config;
48static rtems_irq_connect_data*          rtems_hdl_tbl;
49
50/*
51 * Check if IRQ is an ISA IRQ
52 */
53static inline int is_isa_irq(const rtems_irq_number irqLine)
54{
55  return (((int) irqLine <= BSP_ISA_IRQ_MAX_OFFSET) &
56          ((int) irqLine >= BSP_ISA_IRQ_LOWEST_OFFSET)
57         );
58}
59
60/*
61 * Check if IRQ is an OPENPIC IRQ
62 */
63static inline int is_pci_irq(const rtems_irq_number irqLine)
64{
65  return (((int) irqLine <= BSP_PCI_IRQ_MAX_OFFSET) &
66          ((int) irqLine >= BSP_PCI_IRQ_LOWEST_OFFSET)
67         );
68}
69
70/*
71 * Check if IRQ is a Porcessor IRQ
72 */
73static inline int is_processor_irq(const rtems_irq_number irqLine)
74{
75  return (((int) irqLine <= BSP_PROCESSOR_IRQ_MAX_OFFSET) &
76          ((int) irqLine >= BSP_PROCESSOR_IRQ_LOWEST_OFFSET)
77         );
78}
79
80
81/*
82 * ------------------------ RTEMS Irq helper functions ----------------
83 */
84 
85/*
86 * This function check that the value given for the irq line
87 * is valid.
88 */
89
90static int isValidInterrupt(int irq)
91{
92  if ( (irq < BSP_LOWEST_OFFSET) || (irq > BSP_MAX_OFFSET))
93    return 0;
94  return 1;
95}
96
97
98/*
99 * ------------------------ RTEMS Shared Irq Handler Mngt Routines ----------------
100 */
101int BSP_install_rtems_shared_irq_handler  (const rtems_irq_connect_data* irq)
102{
103    unsigned int level;
104    rtems_irq_connect_data* vchain;
105
106    if (!isValidInterrupt(irq->name)) {
107      printk("Invalid interrupt vector %d\n",irq->name);
108      return 0;
109    }
110    printk("Install Shared interrupt %d\n", irq->name);
111
112    _CPU_ISR_Disable(level);
113
114    if ( (int)rtems_hdl_tbl[irq->name].next_handler  == -1 ) {
115      _CPU_ISR_Enable(level);
116      printk("IRQ vector %d already connected to an unshared handler\n",irq->name);
117      return 0;
118    }
119
120     vchain = (rtems_irq_connect_data*)malloc(sizeof(rtems_irq_connect_data));
121
122    /* save off topmost handler */
123    vchain[0]= rtems_hdl_tbl[irq->name];
124   
125    /*
126     * store the data provided by user
127     */
128    rtems_hdl_tbl[irq->name] = *irq;
129
130    /* link chain to new topmost handler */
131    rtems_hdl_tbl[irq->name].next_handler = (void *)vchain;
132
133   
134    if (is_isa_irq(irq->name)) {
135      /*
136       * Enable interrupt at PIC level
137       */
138      BSP_irq_enable_at_i8259s (irq->name);
139    }
140   
141    if (is_pci_irq(irq->name)) {
142      /*
143       * Enable interrupt at OPENPIC level
144       */
145      printk(" openpic_enable_irq %d\n", (int)irq->name );
146      openpic_enable_irq ((int) irq->name );  /* - BSP_PCI_IRQ_LOWEST_OFFSET); */
147    }
148
149    if (is_processor_irq(irq->name)) {
150      /*
151       * Enable exception at processor level
152       */
153    }
154    /*
155     * Enable interrupt on device
156     */
157    irq->on(irq);
158   
159    _CPU_ISR_Enable(level);
160
161    return 1;
162}
163
164
165/*
166 * ------------------------ RTEMS Single Irq Handler Mngt Routines ----------------
167 */
168
169int BSP_install_rtems_irq_handler  (const rtems_irq_connect_data* irq)
170{
171    unsigned int level;
172
173    if (!isValidInterrupt(irq->name)) {
174      printk("Invalid interrupt vector %d\n",irq->name);
175      return 0;
176    }
177    /*
178     * Check if default handler is actually connected. If not issue an error.
179     * You must first get the current handler via i386_get_current_idt_entry
180     * and then disconnect it using i386_delete_idt_entry.
181     * RATIONALE : to always have the same transition by forcing the user
182     * to get the previous handler before accepting to disconnect.
183     */
184    _CPU_ISR_Disable(level);
185    if (rtems_hdl_tbl[irq->name].hdl != default_rtems_entry.hdl) {
186      _CPU_ISR_Enable(level);
187      printk("IRQ vector %d already connected\n",irq->name);
188      return 0;
189    }
190
191    /*
192     * store the data provided by user
193     */
194    rtems_hdl_tbl[irq->name] = *irq;
195    rtems_hdl_tbl[irq->name].next_handler = (void *)-1;
196   
197    if (is_isa_irq(irq->name)) {
198      /*
199       * Enable interrupt at PIC level
200       */
201      BSP_irq_enable_at_i8259s (irq->name);
202    }
203   
204    if (is_pci_irq(irq->name)) {
205      /*
206       * Enable interrupt at OPENPIC level
207       */
208      openpic_enable_irq ((int) irq->name ); /* - BSP_PCI_IRQ_LOWEST_OFFSET); */
209    }
210
211    if (is_processor_irq(irq->name)) {
212      /*
213       * Enable exception at processor level
214       */
215    }
216    /*
217     * Enable interrupt on device
218     */
219    irq->on(irq);
220   
221    _CPU_ISR_Enable(level);
222
223    return 1;
224}
225
226
227int BSP_get_current_rtems_irq_handler   (rtems_irq_connect_data* irq)
228{
229     unsigned int level;
230
231     if (!isValidInterrupt(irq->name)) {
232      return 0;
233     }
234     _CPU_ISR_Disable(level);
235     *irq = rtems_hdl_tbl[irq->name];
236     _CPU_ISR_Enable(level);
237     return 1;
238}
239
240int BSP_remove_rtems_irq_handler  (const rtems_irq_connect_data* irq)
241{
242   rtems_irq_connect_data *pchain= NULL, *vchain = NULL;
243    unsigned int level;
244 
245    if (!isValidInterrupt(irq->name)) {
246      return 0;
247    }
248    /*
249     * Check if default handler is actually connected. If not issue an error.
250     * You must first get the current handler via i386_get_current_idt_entry
251     * and then disconnect it using i386_delete_idt_entry.
252     * RATIONALE : to always have the same transition by forcing the user
253     * to get the previous handler before accepting to disconnect.
254     */
255    _CPU_ISR_Disable(level);
256    if (rtems_hdl_tbl[irq->name].hdl != irq->hdl) {
257      _CPU_ISR_Enable(level);
258      return 0;
259    }
260
261    if( (int)rtems_hdl_tbl[irq->name].next_handler != -1 )
262    {
263       int found = 0;
264
265       for( (pchain= NULL, vchain = &rtems_hdl_tbl[irq->name]);
266            (vchain->hdl != default_rtems_entry.hdl);
267            (pchain= vchain, vchain = (rtems_irq_connect_data*)vchain->next_handler) )
268       {
269          if( vchain->hdl == irq->hdl )
270          {
271             found= -1; break;
272          }
273       }
274
275       if( !found )
276       {
277          _CPU_ISR_Enable(level);
278          return 0;
279       }
280    }
281    else
282    {
283       if (rtems_hdl_tbl[irq->name].hdl != irq->hdl) 
284       {
285          _CPU_ISR_Enable(level);
286         return 0;
287       }
288    }
289
290    if (is_isa_irq(irq->name)) {
291      /*
292       * disable interrupt at PIC level
293       */
294      BSP_irq_disable_at_i8259s (irq->name);
295    }
296    if (is_pci_irq(irq->name)) {
297      /*
298       * disable interrupt at OPENPIC level
299       */
300      openpic_disable_irq ((int) irq->name ); 
301    }
302    if (is_processor_irq(irq->name)) {
303      /*
304       * disable exception at processor level
305       */
306    }   
307
308    /*
309     * Disable interrupt on device
310     */
311    irq->off(irq);
312
313    /*
314     * restore the default irq value
315     */
316    if( !vchain )
317    {
318       /* single handler vector... */
319       rtems_hdl_tbl[irq->name] = default_rtems_entry;
320    }
321    else
322    {
323       if( pchain )
324       {
325          /* non-first handler being removed */
326          pchain->next_handler = vchain->next_handler;
327       }
328       else
329       {
330          /* first handler isn't malloc'ed, so just overwrite it.  Since
331          the contents of vchain are being struct copied, vchain itself
332          goes away */
333          rtems_hdl_tbl[irq->name]= *vchain;
334       }
335       free(vchain);
336    }
337
338    _CPU_ISR_Enable(level);
339
340    return 1;
341}
342
343/*
344 * ------------------------ RTEMS Global Irq Handler Mngt Routines ----------------
345 */
346
347int BSP_rtems_irq_mngt_set(rtems_irq_global_settings* config)
348{
349    int i;
350    unsigned int level;
351   /*
352    * Store various code accelerators
353    */
354    internal_config             = config;
355    default_rtems_entry         = config->defaultEntry;
356    rtems_hdl_tbl               = config->irqHdlTbl;
357    return 1; 
358
359    _CPU_ISR_Disable(level);
360    /*
361     * set up internal tables used by rtems interrupt prologue
362     */
363    for (i=BSP_PCI_IRQ_LOWEST_OFFSET; i < BSP_PCI_IRQ_LOWEST_OFFSET + BSP_PCI_IRQ_NUMBER ; i++) {
364      /*
365       * Note that openpic_set_priority() sets the TASK priority of the PIC
366       */
367      openpic_set_source_priority(i, internal_config->irqPrioTbl[i]);
368      if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) {
369         openpic_enable_irq ((int) i); 
370         {
371            rtems_irq_connect_data* vchain;
372            for( vchain = &rtems_hdl_tbl[i];
373                 ((int)vchain != -1 && vchain->hdl != default_rtems_entry.hdl); 
374                 vchain = (rtems_irq_connect_data*)vchain->next_handler )
375            {
376               vchain->on(vchain);
377            }
378         }
379
380      }
381      else {
382         /* rtems_hdl_tbl[i].off(&rtems_hdl_tbl[i]); */
383         {
384            rtems_irq_connect_data* vchain;
385            for( vchain = &rtems_hdl_tbl[i];
386                 ((int)vchain != -1 && vchain->hdl != default_rtems_entry.hdl); 
387                 vchain = (rtems_irq_connect_data*)vchain->next_handler )
388            {
389               vchain->off(vchain);
390            }
391         }
392         
393         openpic_disable_irq ((int) i ); 
394      }
395    }
396    /*
397     * Must enable PCI/ISA bridge IRQ
398     */
399    openpic_enable_irq (0);
400    /*
401     * finish with Processor exceptions handled like IRQ
402     */
403    for (i=BSP_PROCESSOR_IRQ_LOWEST_OFFSET; i < BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER; i++) {
404      if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) {
405         /* rtems_hdl_tbl[i].on(&rtems_hdl_tbl[i]); */
406         {
407            rtems_irq_connect_data* vchain;
408            for( vchain = &rtems_hdl_tbl[i];
409                 ((int)vchain != -1 && vchain->hdl != default_rtems_entry.hdl); 
410                 vchain = (rtems_irq_connect_data*)vchain->next_handler )
411            {
412               vchain->on(vchain);
413            }
414         }
415
416      }
417      else {
418         /* rtems_hdl_tbl[i].off(&rtems_hdl_tbl[i]); */
419         {
420            rtems_irq_connect_data* vchain;
421            for( vchain = &rtems_hdl_tbl[i];
422                 ((int)vchain != -1 && vchain->hdl != default_rtems_entry.hdl); 
423                 vchain = (rtems_irq_connect_data*)vchain->next_handler )
424            {
425               vchain->off(vchain);
426            }
427         }
428
429      }
430    }
431    _CPU_ISR_Enable(level);
432    return 1;
433}
434
435int BSP_rtems_irq_mngt_get(rtems_irq_global_settings** config)
436{
437    *config = internal_config;
438    return 0;
439}   
440
441int _BSP_vme_bridge_irq = -1;
442 
443unsigned BSP_spuriousIntr = 0;
444/*
445 * High level IRQ handler called from shared_raw_irq_code_entry
446 */
447void C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum)
448{
449  register unsigned int irq;
450  register unsigned isaIntr;                  /* boolean */
451  register unsigned oldMask = 0;              /* old isa pic masks */
452  register unsigned newMask;                  /* new isa pic masks */
453  register unsigned msr;
454  register unsigned new_msr;
455
456  if (excNum == ASM_DEC_VECTOR) {
457    _CPU_MSR_GET(msr);
458    new_msr = msr | MSR_EE;
459    _CPU_MSR_SET(new_msr);
460   
461    rtems_hdl_tbl[BSP_DECREMENTER].hdl( rtems_hdl_tbl[BSP_DECREMENTER].handle );
462
463    _CPU_MSR_SET(msr);
464    return;
465   
466  }
467
468  irq = openpic_irq(0);
469
470  if (irq == OPENPIC_VEC_SPURIOUS) {
471    ++BSP_spuriousIntr;
472   return;
473  }
474
475  isaIntr = (irq == BSP_PCI_ISA_BRIDGE_IRQ);
476  if (isaIntr)  {
477    /*
478     * Acknowledge and read 8259 vector
479     */
480    irq = (unsigned int) (*(unsigned char *) RAVEN_INTR_ACK_REG);
481    /*
482     * store current PIC mask
483     */
484    oldMask = i8259s_cache;
485    newMask = oldMask | irq_mask_or_tbl [irq];
486    i8259s_cache = newMask;
487    outport_byte(PIC_MASTER_IMR_IO_PORT, i8259s_cache & 0xff);
488    outport_byte(PIC_SLAVE_IMR_IO_PORT, ((i8259s_cache & 0xff00) >> 8));
489    BSP_irq_ack_at_i8259s (irq);
490    openpic_eoi(0);
491  }
492
493  _CPU_MSR_GET(msr);
494  new_msr = msr | MSR_EE;
495  _CPU_MSR_SET(new_msr);
496
497  {
498     rtems_irq_connect_data* vchain;
499     irq -= 16;    /* Correct the vector for the 8240 */ 
500     for( vchain = &rtems_hdl_tbl[irq];
501          ((int)vchain != -1 && vchain->hdl != default_rtems_entry.hdl);
502          vchain = (rtems_irq_connect_data*)vchain->next_handler )
503     {
504        vchain->hdl( vchain->handle );
505     }
506  }
507  _CPU_MSR_SET(msr);
508
509  if (isaIntr)  {
510    i8259s_cache = oldMask;
511    outport_byte(PIC_MASTER_IMR_IO_PORT, i8259s_cache & 0xff);
512    outport_byte(PIC_SLAVE_IMR_IO_PORT, ((i8259s_cache & 0xff00) >> 8));
513  }
514  else {
515#ifdef BSP_PCI_VME_DRIVER_DOES_EOI
516        /* leave it to the VME bridge driver to do EOI, so
517     * it can re-enable the openpic while handling
518     * VME interrupts (-> VME priorities in software)
519         */
520        if (_BSP_vme_bridge_irq != irq)
521#endif
522                openpic_eoi(0);
523  }
524}
525   
526   
527 
528void _ThreadProcessSignalsFromIrq (BSP_Exception_frame* ctx)
529{
530  /*
531   * Process pending signals that have not already been
532   * processed by _Thread_Displatch. This happens quite
533   * unfrequently : the ISR must have posted an action
534   * to the current running thread.
535   */
536  if ( _Thread_Do_post_task_switch_extension ||
537       _Thread_Executing->do_post_task_switch_extension ) {
538    _Thread_Executing->do_post_task_switch_extension = FALSE;
539    _API_extensions_Run_postswitch();
540  }
541  /*
542   * I plan to process other thread related events here.
543   * This will include DEBUG session requested from keyboard...
544   */
545}
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