[0329aae] | 1 | /* |
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| 2 | * |
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| 3 | * This file contains the implementation of the function described in irq.h |
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| 4 | * |
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| 5 | * COPYRIGHT (c) 1989-1999. |
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| 6 | * On-Line Applications Research Corporation (OAR). |
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| 7 | * |
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| 8 | * The license and distribution terms for this file may be |
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| 9 | * found in the file LICENSE in this distribution or at |
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| 10 | * http://www.rtems.com/license/LICENSE. |
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| 11 | * |
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| 12 | * $Id$ |
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| 13 | */ |
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| 14 | |
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| 15 | #include <rtems/system.h> |
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| 16 | #include <bsp.h> |
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| 17 | #include <bsp/irq.h> |
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| 18 | #include <bsp/VME.h> |
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| 19 | #include <bsp/openpic.h> |
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| 20 | #include <rtems/score/thread.h> |
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| 21 | #include <rtems/score/apiext.h> |
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| 22 | #include <libcpu/raw_exception.h> |
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| 23 | #include <libcpu/io.h> |
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| 24 | #include <bsp/vectors.h> |
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| 25 | #include <stdlib.h> |
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| 26 | #include <rtems/bspIo.h> /* for printk */ |
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| 27 | #define RAVEN_INTR_ACK_REG 0xfeff0030 |
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| 28 | |
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| 29 | /* |
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| 30 | * pointer to the mask representing the additionnal irq vectors |
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| 31 | * that must be disabled when a particular entry is activated. |
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| 32 | * They will be dynamically computed from teh prioruty table given |
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| 33 | * in BSP_rtems_irq_mngt_set(); |
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| 34 | * CAUTION : this table is accessed directly by interrupt routine |
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| 35 | * prologue. |
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| 36 | */ |
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| 37 | rtems_i8259_masks irq_mask_or_tbl[BSP_IRQ_NUMBER]; |
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| 38 | /* |
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| 39 | * default handler connected on each irq after bsp initialization |
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| 40 | */ |
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| 41 | static rtems_irq_connect_data default_rtems_entry; |
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| 42 | |
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| 43 | /* |
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| 44 | * location used to store initial tables used for interrupt |
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| 45 | * management. |
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| 46 | */ |
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| 47 | static rtems_irq_global_settings* internal_config; |
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| 48 | static rtems_irq_connect_data* rtems_hdl_tbl; |
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| 49 | |
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| 50 | /* |
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| 51 | * Check if IRQ is an ISA IRQ |
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| 52 | */ |
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[41a4657] | 53 | static inline int is_isa_irq(const rtems_irq_number irqLine) |
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[0329aae] | 54 | { |
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| 55 | return (((int) irqLine <= BSP_ISA_IRQ_MAX_OFFSET) & |
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| 56 | ((int) irqLine >= BSP_ISA_IRQ_LOWEST_OFFSET) |
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| 57 | ); |
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| 58 | } |
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| 59 | |
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| 60 | /* |
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| 61 | * Check if IRQ is an OPENPIC IRQ |
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| 62 | */ |
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[41a4657] | 63 | static inline int is_pci_irq(const rtems_irq_number irqLine) |
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[0329aae] | 64 | { |
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| 65 | return (((int) irqLine <= BSP_PCI_IRQ_MAX_OFFSET) & |
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| 66 | ((int) irqLine >= BSP_PCI_IRQ_LOWEST_OFFSET) |
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| 67 | ); |
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| 68 | } |
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| 69 | |
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| 70 | /* |
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| 71 | * Check if IRQ is a Porcessor IRQ |
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| 72 | */ |
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[41a4657] | 73 | static inline int is_processor_irq(const rtems_irq_number irqLine) |
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[0329aae] | 74 | { |
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| 75 | return (((int) irqLine <= BSP_PROCESSOR_IRQ_MAX_OFFSET) & |
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| 76 | ((int) irqLine >= BSP_PROCESSOR_IRQ_LOWEST_OFFSET) |
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| 77 | ); |
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| 78 | } |
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| 79 | |
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| 80 | |
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| 81 | /* |
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| 82 | * ------------------------ RTEMS Irq helper functions ---------------- |
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| 83 | */ |
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| 84 | |
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| 85 | /* |
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| 86 | * This function check that the value given for the irq line |
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| 87 | * is valid. |
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| 88 | */ |
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| 89 | |
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| 90 | static int isValidInterrupt(int irq) |
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| 91 | { |
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| 92 | if ( (irq < BSP_LOWEST_OFFSET) || (irq > BSP_MAX_OFFSET)) |
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| 93 | return 0; |
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| 94 | return 1; |
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| 95 | } |
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| 96 | |
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| 97 | |
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| 98 | /* |
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| 99 | * ------------------------ RTEMS Shared Irq Handler Mngt Routines ---------------- |
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| 100 | */ |
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| 101 | int BSP_install_rtems_shared_irq_handler (const rtems_irq_connect_data* irq) |
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| 102 | { |
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[ec1d0b9d] | 103 | rtems_interrupt_level level; |
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[0329aae] | 104 | rtems_irq_connect_data* vchain; |
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| 105 | |
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| 106 | if (!isValidInterrupt(irq->name)) { |
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| 107 | printk("Invalid interrupt vector %d\n",irq->name); |
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| 108 | return 0; |
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| 109 | } |
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| 110 | printk("Install Shared interrupt %d\n", irq->name); |
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| 111 | |
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[ec1d0b9d] | 112 | rtems_interrupt_disable(level); |
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[0329aae] | 113 | |
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| 114 | if ( (int)rtems_hdl_tbl[irq->name].next_handler == -1 ) { |
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[ec1d0b9d] | 115 | rtems_interrupt_enable(level); |
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[0329aae] | 116 | printk("IRQ vector %d already connected to an unshared handler\n",irq->name); |
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| 117 | return 0; |
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| 118 | } |
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| 119 | |
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| 120 | vchain = (rtems_irq_connect_data*)malloc(sizeof(rtems_irq_connect_data)); |
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| 121 | |
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| 122 | /* save off topmost handler */ |
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| 123 | vchain[0]= rtems_hdl_tbl[irq->name]; |
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| 124 | |
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| 125 | /* |
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| 126 | * store the data provided by user |
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| 127 | */ |
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| 128 | rtems_hdl_tbl[irq->name] = *irq; |
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| 129 | |
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| 130 | /* link chain to new topmost handler */ |
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| 131 | rtems_hdl_tbl[irq->name].next_handler = (void *)vchain; |
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| 132 | |
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| 133 | |
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| 134 | if (is_isa_irq(irq->name)) { |
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| 135 | /* |
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| 136 | * Enable interrupt at PIC level |
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| 137 | */ |
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| 138 | BSP_irq_enable_at_i8259s (irq->name); |
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| 139 | } |
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| 140 | |
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| 141 | if (is_pci_irq(irq->name)) { |
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| 142 | /* |
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| 143 | * Enable interrupt at OPENPIC level |
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| 144 | */ |
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| 145 | printk(" openpic_enable_irq %d\n", (int)irq->name ); |
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| 146 | openpic_enable_irq ((int) irq->name ); /* - BSP_PCI_IRQ_LOWEST_OFFSET); */ |
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| 147 | } |
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| 148 | |
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| 149 | if (is_processor_irq(irq->name)) { |
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| 150 | /* |
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| 151 | * Enable exception at processor level |
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| 152 | */ |
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| 153 | } |
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| 154 | /* |
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| 155 | * Enable interrupt on device |
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| 156 | */ |
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| 157 | irq->on(irq); |
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| 158 | |
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[ec1d0b9d] | 159 | rtems_interrupt_enable(level); |
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[0329aae] | 160 | |
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| 161 | return 1; |
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| 162 | } |
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| 163 | |
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| 164 | |
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| 165 | /* |
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| 166 | * ------------------------ RTEMS Single Irq Handler Mngt Routines ---------------- |
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| 167 | */ |
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| 168 | |
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| 169 | int BSP_install_rtems_irq_handler (const rtems_irq_connect_data* irq) |
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| 170 | { |
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[ec1d0b9d] | 171 | rtems_interrupt_level level; |
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[0329aae] | 172 | |
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| 173 | if (!isValidInterrupt(irq->name)) { |
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| 174 | printk("Invalid interrupt vector %d\n",irq->name); |
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| 175 | return 0; |
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| 176 | } |
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| 177 | /* |
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| 178 | * Check if default handler is actually connected. If not issue an error. |
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| 179 | * You must first get the current handler via i386_get_current_idt_entry |
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| 180 | * and then disconnect it using i386_delete_idt_entry. |
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| 181 | * RATIONALE : to always have the same transition by forcing the user |
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| 182 | * to get the previous handler before accepting to disconnect. |
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| 183 | */ |
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[ec1d0b9d] | 184 | rtems_interrupt_disable(level); |
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[0329aae] | 185 | if (rtems_hdl_tbl[irq->name].hdl != default_rtems_entry.hdl) { |
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[ec1d0b9d] | 186 | rtems_interrupt_enable(level); |
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[0329aae] | 187 | printk("IRQ vector %d already connected\n",irq->name); |
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| 188 | return 0; |
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| 189 | } |
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| 190 | |
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| 191 | /* |
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| 192 | * store the data provided by user |
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| 193 | */ |
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| 194 | rtems_hdl_tbl[irq->name] = *irq; |
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| 195 | rtems_hdl_tbl[irq->name].next_handler = (void *)-1; |
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| 196 | |
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| 197 | if (is_isa_irq(irq->name)) { |
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| 198 | /* |
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| 199 | * Enable interrupt at PIC level |
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| 200 | */ |
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| 201 | BSP_irq_enable_at_i8259s (irq->name); |
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| 202 | } |
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| 203 | |
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| 204 | if (is_pci_irq(irq->name)) { |
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| 205 | /* |
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| 206 | * Enable interrupt at OPENPIC level |
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| 207 | */ |
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| 208 | openpic_enable_irq ((int) irq->name ); /* - BSP_PCI_IRQ_LOWEST_OFFSET); */ |
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| 209 | } |
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| 210 | |
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| 211 | if (is_processor_irq(irq->name)) { |
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| 212 | /* |
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| 213 | * Enable exception at processor level |
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| 214 | */ |
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| 215 | } |
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| 216 | /* |
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| 217 | * Enable interrupt on device |
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| 218 | */ |
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| 219 | irq->on(irq); |
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| 220 | |
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[ec1d0b9d] | 221 | rtems_interrupt_enable(level); |
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[0329aae] | 222 | |
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| 223 | return 1; |
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| 224 | } |
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| 225 | |
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| 226 | |
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| 227 | int BSP_get_current_rtems_irq_handler (rtems_irq_connect_data* irq) |
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| 228 | { |
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[ec1d0b9d] | 229 | rtems_interrupt_level level; |
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[0329aae] | 230 | |
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[ec1d0b9d] | 231 | if (!isValidInterrupt(irq->name)) { |
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[0329aae] | 232 | return 0; |
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[ec1d0b9d] | 233 | } |
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| 234 | rtems_interrupt_disable(level); |
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| 235 | *irq = rtems_hdl_tbl[irq->name]; |
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| 236 | rtems_interrupt_enable(level); |
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| 237 | return 1; |
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[0329aae] | 238 | } |
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| 239 | |
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| 240 | int BSP_remove_rtems_irq_handler (const rtems_irq_connect_data* irq) |
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| 241 | { |
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[ec1d0b9d] | 242 | rtems_irq_connect_data *pchain= NULL, *vchain = NULL; |
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| 243 | rtems_interrupt_level level; |
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[0329aae] | 244 | |
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| 245 | if (!isValidInterrupt(irq->name)) { |
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| 246 | return 0; |
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| 247 | } |
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| 248 | /* |
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| 249 | * Check if default handler is actually connected. If not issue an error. |
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| 250 | * You must first get the current handler via i386_get_current_idt_entry |
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| 251 | * and then disconnect it using i386_delete_idt_entry. |
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| 252 | * RATIONALE : to always have the same transition by forcing the user |
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| 253 | * to get the previous handler before accepting to disconnect. |
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| 254 | */ |
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[ec1d0b9d] | 255 | rtems_interrupt_disable(level); |
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[0329aae] | 256 | if (rtems_hdl_tbl[irq->name].hdl != irq->hdl) { |
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[ec1d0b9d] | 257 | rtems_interrupt_enable(level); |
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[0329aae] | 258 | return 0; |
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| 259 | } |
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| 260 | |
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| 261 | if( (int)rtems_hdl_tbl[irq->name].next_handler != -1 ) |
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| 262 | { |
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| 263 | int found = 0; |
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| 264 | |
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| 265 | for( (pchain= NULL, vchain = &rtems_hdl_tbl[irq->name]); |
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| 266 | (vchain->hdl != default_rtems_entry.hdl); |
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| 267 | (pchain= vchain, vchain = (rtems_irq_connect_data*)vchain->next_handler) ) |
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| 268 | { |
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| 269 | if( vchain->hdl == irq->hdl ) |
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| 270 | { |
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| 271 | found= -1; break; |
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| 272 | } |
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| 273 | } |
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| 274 | |
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| 275 | if( !found ) |
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| 276 | { |
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[ec1d0b9d] | 277 | rtems_interrupt_enable(level); |
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[0329aae] | 278 | return 0; |
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| 279 | } |
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| 280 | } |
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| 281 | else |
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| 282 | { |
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| 283 | if (rtems_hdl_tbl[irq->name].hdl != irq->hdl) |
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| 284 | { |
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[ec1d0b9d] | 285 | rtems_interrupt_enable(level); |
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[0329aae] | 286 | return 0; |
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| 287 | } |
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| 288 | } |
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| 289 | |
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| 290 | if (is_isa_irq(irq->name)) { |
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| 291 | /* |
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| 292 | * disable interrupt at PIC level |
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| 293 | */ |
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| 294 | BSP_irq_disable_at_i8259s (irq->name); |
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| 295 | } |
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| 296 | if (is_pci_irq(irq->name)) { |
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| 297 | /* |
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| 298 | * disable interrupt at OPENPIC level |
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| 299 | */ |
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| 300 | openpic_disable_irq ((int) irq->name ); |
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| 301 | } |
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| 302 | if (is_processor_irq(irq->name)) { |
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| 303 | /* |
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| 304 | * disable exception at processor level |
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| 305 | */ |
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| 306 | } |
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| 307 | |
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| 308 | /* |
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| 309 | * Disable interrupt on device |
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| 310 | */ |
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| 311 | irq->off(irq); |
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| 312 | |
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| 313 | /* |
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| 314 | * restore the default irq value |
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| 315 | */ |
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| 316 | if( !vchain ) |
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| 317 | { |
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| 318 | /* single handler vector... */ |
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| 319 | rtems_hdl_tbl[irq->name] = default_rtems_entry; |
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| 320 | } |
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| 321 | else |
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| 322 | { |
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| 323 | if( pchain ) |
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| 324 | { |
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| 325 | /* non-first handler being removed */ |
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| 326 | pchain->next_handler = vchain->next_handler; |
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| 327 | } |
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| 328 | else |
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| 329 | { |
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| 330 | /* first handler isn't malloc'ed, so just overwrite it. Since |
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| 331 | the contents of vchain are being struct copied, vchain itself |
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| 332 | goes away */ |
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| 333 | rtems_hdl_tbl[irq->name]= *vchain; |
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| 334 | } |
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| 335 | free(vchain); |
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| 336 | } |
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| 337 | |
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[ec1d0b9d] | 338 | rtems_interrupt_enable(level); |
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[0329aae] | 339 | |
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| 340 | return 1; |
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| 341 | } |
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| 342 | |
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| 343 | /* |
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| 344 | * ------------------------ RTEMS Global Irq Handler Mngt Routines ---------------- |
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| 345 | */ |
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| 346 | |
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| 347 | int BSP_rtems_irq_mngt_set(rtems_irq_global_settings* config) |
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| 348 | { |
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[ec1d0b9d] | 349 | int i; |
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| 350 | rtems_interrupt_level level; |
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| 351 | |
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| 352 | /* |
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| 353 | * Store various code accelerators |
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| 354 | */ |
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[0329aae] | 355 | internal_config = config; |
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| 356 | default_rtems_entry = config->defaultEntry; |
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| 357 | rtems_hdl_tbl = config->irqHdlTbl; |
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| 358 | return 1; |
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| 359 | |
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[ec1d0b9d] | 360 | rtems_interrupt_disable(level); |
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[0329aae] | 361 | /* |
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| 362 | * set up internal tables used by rtems interrupt prologue |
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| 363 | */ |
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| 364 | for (i=BSP_PCI_IRQ_LOWEST_OFFSET; i < BSP_PCI_IRQ_LOWEST_OFFSET + BSP_PCI_IRQ_NUMBER ; i++) { |
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| 365 | /* |
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| 366 | * Note that openpic_set_priority() sets the TASK priority of the PIC |
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| 367 | */ |
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| 368 | openpic_set_source_priority(i, internal_config->irqPrioTbl[i]); |
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| 369 | if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) { |
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| 370 | openpic_enable_irq ((int) i); |
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| 371 | { |
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| 372 | rtems_irq_connect_data* vchain; |
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| 373 | for( vchain = &rtems_hdl_tbl[i]; |
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| 374 | ((int)vchain != -1 && vchain->hdl != default_rtems_entry.hdl); |
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| 375 | vchain = (rtems_irq_connect_data*)vchain->next_handler ) |
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| 376 | { |
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| 377 | vchain->on(vchain); |
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| 378 | } |
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| 379 | } |
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| 380 | |
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| 381 | } |
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| 382 | else { |
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| 383 | /* rtems_hdl_tbl[i].off(&rtems_hdl_tbl[i]); */ |
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| 384 | { |
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| 385 | rtems_irq_connect_data* vchain; |
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| 386 | for( vchain = &rtems_hdl_tbl[i]; |
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| 387 | ((int)vchain != -1 && vchain->hdl != default_rtems_entry.hdl); |
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| 388 | vchain = (rtems_irq_connect_data*)vchain->next_handler ) |
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| 389 | { |
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| 390 | vchain->off(vchain); |
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| 391 | } |
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| 392 | } |
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| 393 | |
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| 394 | openpic_disable_irq ((int) i ); |
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| 395 | } |
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| 396 | } |
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| 397 | /* |
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| 398 | * Must enable PCI/ISA bridge IRQ |
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| 399 | */ |
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| 400 | openpic_enable_irq (0); |
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| 401 | /* |
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| 402 | * finish with Processor exceptions handled like IRQ |
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| 403 | */ |
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| 404 | for (i=BSP_PROCESSOR_IRQ_LOWEST_OFFSET; i < BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER; i++) { |
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| 405 | if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) { |
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| 406 | /* rtems_hdl_tbl[i].on(&rtems_hdl_tbl[i]); */ |
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| 407 | { |
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| 408 | rtems_irq_connect_data* vchain; |
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| 409 | for( vchain = &rtems_hdl_tbl[i]; |
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| 410 | ((int)vchain != -1 && vchain->hdl != default_rtems_entry.hdl); |
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| 411 | vchain = (rtems_irq_connect_data*)vchain->next_handler ) |
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| 412 | { |
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| 413 | vchain->on(vchain); |
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| 414 | } |
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| 415 | } |
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| 416 | |
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| 417 | } |
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| 418 | else { |
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| 419 | /* rtems_hdl_tbl[i].off(&rtems_hdl_tbl[i]); */ |
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| 420 | { |
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| 421 | rtems_irq_connect_data* vchain; |
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| 422 | for( vchain = &rtems_hdl_tbl[i]; |
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| 423 | ((int)vchain != -1 && vchain->hdl != default_rtems_entry.hdl); |
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| 424 | vchain = (rtems_irq_connect_data*)vchain->next_handler ) |
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| 425 | { |
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| 426 | vchain->off(vchain); |
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| 427 | } |
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| 428 | } |
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| 429 | |
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| 430 | } |
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| 431 | } |
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[ec1d0b9d] | 432 | rtems_interrupt_enable(level); |
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[0329aae] | 433 | return 1; |
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| 434 | } |
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| 435 | |
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| 436 | int BSP_rtems_irq_mngt_get(rtems_irq_global_settings** config) |
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| 437 | { |
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| 438 | *config = internal_config; |
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| 439 | return 0; |
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| 440 | } |
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| 441 | |
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| 442 | int _BSP_vme_bridge_irq = -1; |
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| 443 | |
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| 444 | unsigned BSP_spuriousIntr = 0; |
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| 445 | /* |
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| 446 | * High level IRQ handler called from shared_raw_irq_code_entry |
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| 447 | */ |
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| 448 | void C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum) |
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| 449 | { |
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| 450 | register unsigned int irq; |
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| 451 | register unsigned isaIntr; /* boolean */ |
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| 452 | register unsigned oldMask = 0; /* old isa pic masks */ |
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| 453 | register unsigned newMask; /* new isa pic masks */ |
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| 454 | register unsigned msr; |
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| 455 | register unsigned new_msr; |
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| 456 | |
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| 457 | if (excNum == ASM_DEC_VECTOR) { |
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| 458 | _CPU_MSR_GET(msr); |
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| 459 | new_msr = msr | MSR_EE; |
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| 460 | _CPU_MSR_SET(new_msr); |
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| 461 | |
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| 462 | rtems_hdl_tbl[BSP_DECREMENTER].hdl( rtems_hdl_tbl[BSP_DECREMENTER].handle ); |
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| 463 | |
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| 464 | _CPU_MSR_SET(msr); |
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| 465 | return; |
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| 466 | |
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| 467 | } |
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| 468 | |
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| 469 | irq = openpic_irq(0); |
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| 470 | |
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| 471 | if (irq == OPENPIC_VEC_SPURIOUS) { |
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| 472 | ++BSP_spuriousIntr; |
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| 473 | return; |
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| 474 | } |
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| 475 | |
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| 476 | isaIntr = (irq == BSP_PCI_ISA_BRIDGE_IRQ); |
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| 477 | if (isaIntr) { |
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| 478 | /* |
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| 479 | * Acknowledge and read 8259 vector |
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| 480 | */ |
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| 481 | irq = (unsigned int) (*(unsigned char *) RAVEN_INTR_ACK_REG); |
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| 482 | /* |
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| 483 | * store current PIC mask |
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| 484 | */ |
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| 485 | oldMask = i8259s_cache; |
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| 486 | newMask = oldMask | irq_mask_or_tbl [irq]; |
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| 487 | i8259s_cache = newMask; |
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| 488 | outport_byte(PIC_MASTER_IMR_IO_PORT, i8259s_cache & 0xff); |
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| 489 | outport_byte(PIC_SLAVE_IMR_IO_PORT, ((i8259s_cache & 0xff00) >> 8)); |
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| 490 | BSP_irq_ack_at_i8259s (irq); |
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| 491 | openpic_eoi(0); |
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| 492 | } |
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| 493 | |
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| 494 | _CPU_MSR_GET(msr); |
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| 495 | new_msr = msr | MSR_EE; |
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| 496 | _CPU_MSR_SET(new_msr); |
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| 497 | |
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| 498 | { |
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| 499 | rtems_irq_connect_data* vchain; |
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| 500 | irq -= 16; /* Correct the vector for the 8240 */ |
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| 501 | for( vchain = &rtems_hdl_tbl[irq]; |
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| 502 | ((int)vchain != -1 && vchain->hdl != default_rtems_entry.hdl); |
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| 503 | vchain = (rtems_irq_connect_data*)vchain->next_handler ) |
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| 504 | { |
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| 505 | vchain->hdl( vchain->handle ); |
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| 506 | } |
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| 507 | } |
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| 508 | _CPU_MSR_SET(msr); |
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| 509 | |
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| 510 | if (isaIntr) { |
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| 511 | i8259s_cache = oldMask; |
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| 512 | outport_byte(PIC_MASTER_IMR_IO_PORT, i8259s_cache & 0xff); |
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| 513 | outport_byte(PIC_SLAVE_IMR_IO_PORT, ((i8259s_cache & 0xff00) >> 8)); |
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| 514 | } |
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| 515 | else { |
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| 516 | #ifdef BSP_PCI_VME_DRIVER_DOES_EOI |
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| 517 | /* leave it to the VME bridge driver to do EOI, so |
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| 518 | * it can re-enable the openpic while handling |
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| 519 | * VME interrupts (-> VME priorities in software) |
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| 520 | */ |
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| 521 | if (_BSP_vme_bridge_irq != irq) |
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| 522 | #endif |
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| 523 | openpic_eoi(0); |
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| 524 | } |
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| 525 | } |
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| 526 | |
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| 527 | |
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| 528 | |
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| 529 | void _ThreadProcessSignalsFromIrq (BSP_Exception_frame* ctx) |
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| 530 | { |
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| 531 | /* |
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| 532 | * Process pending signals that have not already been |
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| 533 | * processed by _Thread_Displatch. This happens quite |
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| 534 | * unfrequently : the ISR must have posted an action |
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| 535 | * to the current running thread. |
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| 536 | */ |
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| 537 | if ( _Thread_Do_post_task_switch_extension || |
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| 538 | _Thread_Executing->do_post_task_switch_extension ) { |
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| 539 | _Thread_Executing->do_post_task_switch_extension = FALSE; |
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| 540 | _API_extensions_Run_postswitch(); |
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| 541 | } |
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| 542 | /* |
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| 543 | * I plan to process other thread related events here. |
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| 544 | * This will include DEBUG session requested from keyboard... |
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| 545 | */ |
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| 546 | } |
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