source: rtems/c/src/lib/libbsp/powerpc/ep1a/include/bsp.h @ afce764d

4.104.114.9
Last change on this file since afce764d was afce764d, checked in by Joel Sherrill <joel.sherrill@…>, on Dec 4, 2007 at 10:21:41 PM

2007-12-04 Joel Sherrill <joel.sherrill@…>

  • Makefile.am, include/bsp.h, startup/bspstart.c: Move interrupt_stack_size field from CPU Table to Configuration Table. Eliminate CPU Table from all ports. Delete references to CPU Table in all forms.
  • Property mode set to 100644
File size: 6.9 KB
Line 
1/*
2 *
3 *  COPYRIGHT (c) 1989-1999.
4 *  On-Line Applications Research Corporation (OAR).
5 *
6 *  The license and distribution terms for this file may be
7 *  found in the file LICENSE in this distribution or at
8 *  http://www.rtems.com/license/LICENSE.
9 *
10 *  $Id$
11 */
12
13#ifndef _BSP_H
14#define _BSP_H
15
16#include <bspopts.h>
17
18#include <rtems.h>
19#include <rtems/console.h>
20#include <libcpu/io.h>
21#include <rtems/clockdrv.h>
22#include <bsp/vectors.h>
23
24
25/*
26 *  confdefs.h overrides for this BSP:
27 *   - termios serial ports (defaults to 1)
28 *   - Interrupt stack space is not minimum if defined.
29 */
30
31#define CONFIGURE_NUMBER_OF_TERMIOS_PORTS 2
32
33/* fundamental addresses for BSP (CHRPxxx and PREPxxx are from libcpu/io.h) */
34#define _IO_BASE                CHRP_ISA_IO_BASE
35#define _ISA_MEM_BASE           CHRP_ISA_MEM_BASE
36/* address of our ram on the PCI bus   */
37#define PCI_DRAM_OFFSET         CHRP_PCI_DRAM_OFFSET
38#define PCI_MEM_BASE            0x80000000
39#define PCI_MEM_BASE_ADJUSTMENT 0
40
41/* address of our ram on the PCI bus   */
42#define PCI_DRAM_OFFSET         CHRP_PCI_DRAM_OFFSET
43
44/* offset of pci memory as seen from the CPU */
45#define PCI_MEM_BASE            0x00000000 
46
47/* Override the default values for the following     DEFAULT */
48#define PCI_CONFIG_ADDR                 0xfec00000  /* 0xcf8 */
49#define PCI_CONFIG_DATA                 0xfee00000  /* 0xcfc */
50
51/*
52 * EP1A configuration Registers.
53 * Note:  All addresses assume flash boot.
54 */
55
56#define EQUIPMENT_PRESENT_REGISTER1     ((volatile unsigned char *)0xffa00000)
57#define EQUIPMENT_PRESENT_REGISTER2     ((volatile unsigned char *)0xffa00008)
58#define BOARD_REVISION_REGISTER1        ((volatile unsigned char *)0xffa00010)
59#define BOARD_REVISION_REGISTER2        ((volatile unsigned char *)0xffa00018)
60#define GENERAL_REGISTER1               ((volatile unsigned char *)0xffa00020)
61#define GENERAL_REGISTER2               ((volatile unsigned char *)0xffa00028)
62#define WATCHDOG_TRIGGER                ((volatile unsigned char *)0xffa00030)
63
64/* EQUIPMENT_PRESENT_REGISTER1 */
65#define BANK_MEMORY_SIZE_128MB          0x20
66#define BANK_MEMORY_SIZE_64MB           0x10
67#define ECC_ENABLED                     0x04
68
69/* EQUIPMENT-PRESENT_REGISTER2 */
70#define PLL_CFG_MASK                     0xf8
71#define MHZ_33_66_200                    0x70   /* PCI MEM CPU Frequency */
72#define MHZ_33_100_200                   0x80   /* PCI MEM CPU Frequency */
73#define MHZ_33_66_266                    0xb0   /* PCI MEM CPU Frequency */
74#define MHZ_33_66_333                    0x50   /* PCI MEM CPU Frequency */
75#define MHZ_33_100_333                   0x08   /* PCI MEM CPU Frequency */
76#define MHZ_33_100_350                   0x78   /* PCI MEM CPU Frequency */
77
78#define PMC_SLOT1_PRESENT                0x02
79#define PMC_SLOT2_PRESENT                0x01
80 
81/* BOARD_REVISION_REGISTER1 */
82#define ARTWORK_REVISION_MASK            0xf0
83#define BUILD_REVISION_MASK              0x0f
84
85/* BOARD_REVISION_REGISTER2 */
86#define HARDWARE_ID_MASK                 0xe0
87#define HARDWARE_ID_PPC5_EP1A            0xe0
88#define HARDWARE_ID_EP1B                 0xc0
89
90/* GENERAL_REGISTER1 */
91#define DISABLE_WATCHDOG                  0x80
92#define DISABLE_RESET_SWITCH              0x40
93#define DISABLE_USER_FLASH                0x20
94#define DISABLE_BOOT_FLASH                0x10
95#define LED4_OFF                          0x08
96#define LED3_OFF                          0x04
97#define LED2_OFF                          0x02
98#define LED1_OFF                          0x01
99
100
101/* GENERAL_REGISTER2 */
102#define BSP_FLASH_VPP_ENABLE              0x01
103#define BSP_FLASH_PAGE_MASK               0x38
104#define BSP_FLASH_PAGE_SHIFT              0x03
105#define BSP_BIT_SLOWSTART                 0x04
106#define BSP_OFFLINE                       0x02
107#define BSP_SYSFAIL                       0x01
108
109/* WATCHDOG_TRIGGER */
110#define BSP_FLASH_BASE                   0xff000000
111#define BSP_VME_A16_BASE                 0x9fff0000
112#define BSP_VME_A24_BASE                 0x9f000000
113
114/*
115 *  address definitions for several devices
116 *
117 */
118#define UART_OFFSET_1_8245 (0x04500)   
119#define UART_OFFSET_2_8245 (0x04600)
120#define UART_BASE_COM1     0xff800000
121#define UART_BASE_COM2     0xff800040
122
123#include <bsp/openpic.h>
124
125/* Note docs list 0x41000 but OpenPIC has a 0x1000 pad at the start
126 * assume that open pic specifies this pad but not mentioned in
127 * 8245 docs.
128 * This is an offset from EUMBBAR
129 */
130#define BSP_OPEN_PIC_BASE_OFFSET     0x40000 
131
132/* BSP_PIC_DO_EOI is optionally used by the 'vmeUniverse' driver
133 * to implement VME IRQ priorities in software.
134 * Note that this requires support by the interrupt controller
135 * driver (cf. libbsp/shared/powerpc/irq/openpic_i8259_irq.c)
136 * and the BSP-specific universe initialization/configuration
137 * (cf. libbsp/shared/powerpc/vme/VMEConfig.h vme_universe.c)
138 *
139 * ********* IMPORTANT NOTE ********
140 * When deriving from this file (new BSPs)
141 * DO NOT define "BSP_PIC_DO_EOI" if you don't know what
142 * you are doing i.e., w/o implementing the required pieces
143 * mentioned above.
144 * ********* IMPORTANT NOTE ********
145 */
146#define BSP_PIC_DO_EOI openpic_eoi(0)
147
148
149#ifndef ASM
150#define outport_byte(port,value) outb(value,port)
151#define outport_word(port,value) outw(value,port)
152#define outport_long(port,value) outl(value,port)
153
154#define inport_byte(port,value) (value = inb(port))
155#define inport_word(port,value) (value = inw(port))
156#define inport_long(port,value) (value = inl(port))
157
158/*
159 * EUMMBAR
160 */
161extern unsigned int EUMBBAR;
162
163/*
164 * Total memory
165 */
166extern unsigned int BSP_mem_size;
167
168/*
169 * PCI Bus Frequency
170 */
171extern unsigned int BSP_bus_frequency;
172
173/*
174 * processor clock frequency
175 */
176extern unsigned int BSP_processor_frequency;
177
178/*
179 * Time base divisior (how many tick for 1 second).
180 */
181extern unsigned int BSP_time_base_divisor;
182
183#define BSP_Convert_decrementer( _value ) \
184  ((unsigned long long) ((((unsigned long long)BSP_time_base_divisor) * 1000000ULL) /((unsigned long long) BSP_bus_frequency)) * ((unsigned long long) (_value)))
185
186#define Processor_Synchronize() \
187  asm(" eieio ")
188
189extern rtems_configuration_table  BSP_Configuration;
190extern void BSP_panic(char *s);
191extern void rtemsReboot(void);
192extern int BSP_disconnect_clock_handler (void);
193extern int BSP_connect_clock_handler (void);
194
195/*
196 * FLASH
197 */
198int BSP_FLASH_Enable_writes( uint32_t area );
199int BSP_FLASH_Disable_writes(  uint32_t area );
200void BSP_FLASH_set_page( uint8_t  page );
201
202#define BSP_FLASH_ENABLE_WRITES( _area) BSP_FLASH_Enable_writes( _area )
203#define BSP_FLASH_DISABLE_WRITES(_area) BSP_FLASH_Disable_writes( _area )
204#define BSP_FLASH_SET_PAGE(_page)       BSP_FLASH_set_page( _page )
205
206
207/* clear hostbridge errors
208 *
209 * enableMCP: whether to enable MCP checkstop / machine check interrupts
210 *            on the hostbridge and in HID0.
211 *
212 *            NOTE: HID0 and MEREN are left alone if this flag is 0
213 *
214 * quiet    : be silent
215 *
216 * RETURNS  : raven MERST register contents (lowermost 16 bits), 0 if
217 *            there were no errors
218 */
219extern unsigned long _BSP_clear_hostbridge_errors(int enableMCP, int quiet);
220
221#endif
222
223#endif
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