source: rtems/c/src/lib/libbsp/powerpc/ep1a/include/bsp.h @ a771462e

4.104.114.84.9
Last change on this file since a771462e was a771462e, checked in by Till Straumann <strauman@…>, on Jan 31, 2007 at 3:40:58 AM

2007-01-30 Till Straumann <strauman@…>

  • Makefile.am, preinstall.am, include/bsp.h,
  • vme/vmeconfig.c (removed), vme/VMEConfig.h (added): cleaned up vme support - use files from libbsp/powerpc/shared/vme and define BSP specifica in VMEConfig.h. Use VME DMA support implemented by vmeUniverse and libbsp/powerpc/shared/vme/vme_universe_dma.c
  • Property mode set to 100644
File size: 7.0 KB
Line 
1/*
2 *
3 *  COPYRIGHT (c) 1989-1999.
4 *  On-Line Applications Research Corporation (OAR).
5 *
6 *  The license and distribution terms for this file may be
7 *  found in the file LICENSE in this distribution or at
8 *  http://www.rtems.com/license/LICENSE.
9 *
10 *  $Id$
11 */
12
13#ifndef _BSP_H
14#define _BSP_H
15
16#include <bspopts.h>
17
18#include <rtems.h>
19#include <rtems/console.h>
20#include <libcpu/io.h>
21#include <rtems/clockdrv.h>
22#include <bsp/vectors.h>
23
24
25/*
26 *  confdefs.h overrides for this BSP:
27 *   - termios serial ports (defaults to 1)
28 *   - Interrupt stack space is not minimum if defined.
29 */
30
31#define CONFIGURE_NUMBER_OF_TERMIOS_PORTS 2
32#define CONFIGURE_INTERRUPT_STACK_MEMORY  (16 * 1024)
33
34/* fundamental addresses for BSP (CHRPxxx and PREPxxx are from libcpu/io.h) */
35#define _IO_BASE                CHRP_ISA_IO_BASE
36#define _ISA_MEM_BASE           CHRP_ISA_MEM_BASE
37/* address of our ram on the PCI bus   */
38#define PCI_DRAM_OFFSET         CHRP_PCI_DRAM_OFFSET
39#define PCI_MEM_BASE            0x80000000
40#define PCI_MEM_BASE_ADJUSTMENT 0
41
42/* address of our ram on the PCI bus   */
43#define PCI_DRAM_OFFSET         CHRP_PCI_DRAM_OFFSET
44
45/* offset of pci memory as seen from the CPU */
46#define PCI_MEM_BASE            0x00000000 
47
48/* Override the default values for the following     DEFAULT */
49#define PCI_CONFIG_ADDR                 0xfec00000  /* 0xcf8 */
50#define PCI_CONFIG_DATA                 0xfee00000  /* 0xcfc */
51
52/*
53 * EP1A configuration Registers.
54 * Note:  All addresses assume flash boot.
55 */
56
57#define EQUIPMENT_PRESENT_REGISTER1     ((volatile unsigned char *)0xffa00000)
58#define EQUIPMENT_PRESENT_REGISTER2     ((volatile unsigned char *)0xffa00008)
59#define BOARD_REVISION_REGISTER1        ((volatile unsigned char *)0xffa00010)
60#define BOARD_REVISION_REGISTER2        ((volatile unsigned char *)0xffa00018)
61#define GENERAL_REGISTER1               ((volatile unsigned char *)0xffa00020)
62#define GENERAL_REGISTER2               ((volatile unsigned char *)0xffa00028)
63#define WATCHDOG_TRIGGER                ((volatile unsigned char *)0xffa00030)
64
65/* EQUIPMENT_PRESENT_REGISTER1 */
66#define BANK_MEMORY_SIZE_128MB          0x20
67#define BANK_MEMORY_SIZE_64MB           0x10
68#define ECC_ENABLED                     0x04
69
70/* EQUIPMENT-PRESENT_REGISTER2 */
71#define PLL_CFG_MASK                     0xf8
72#define MHZ_33_66_200                    0x70   /* PCI MEM CPU Frequency */
73#define MHZ_33_100_200                   0x80   /* PCI MEM CPU Frequency */
74#define MHZ_33_66_266                    0xb0   /* PCI MEM CPU Frequency */
75#define MHZ_33_66_333                    0x50   /* PCI MEM CPU Frequency */
76#define MHZ_33_100_333                   0x08   /* PCI MEM CPU Frequency */
77#define MHZ_33_100_350                   0x78   /* PCI MEM CPU Frequency */
78
79#define PMC_SLOT1_PRESENT                0x02
80#define PMC_SLOT2_PRESENT                0x01
81 
82/* BOARD_REVISION_REGISTER1 */
83#define ARTWORK_REVISION_MASK            0xf0
84#define BUILD_REVISION_MASK              0x0f
85
86/* BOARD_REVISION_REGISTER2 */
87#define HARDWARE_ID_MASK                 0xe0
88#define HARDWARE_ID_PPC5_EP1A            0xe0
89#define HARDWARE_ID_EP1B                 0xc0
90
91/* GENERAL_REGISTER1 */
92#define DISABLE_WATCHDOG                  0x80
93#define DISABLE_RESET_SWITCH              0x40
94#define DISABLE_USER_FLASH                0x20
95#define DISABLE_BOOT_FLASH                0x10
96#define LED4_OFF                          0x08
97#define LED3_OFF                          0x04
98#define LED2_OFF                          0x02
99#define LED1_OFF                          0x01
100
101
102/* GENERAL_REGISTER2 */
103#define BSP_FLASH_VPP_ENABLE              0x01
104#define BSP_FLASH_PAGE_MASK               0x38
105#define BSP_FLASH_PAGE_SHIFT              0x03
106#define BSP_BIT_SLOWSTART                 0x04
107#define BSP_OFFLINE                       0x02
108#define BSP_SYSFAIL                       0x01
109
110/* WATCHDOG_TRIGGER */
111#define BSP_FLASH_BASE                   0xff000000
112#define BSP_VME_A16_BASE                 0x9fff0000
113#define BSP_VME_A24_BASE                 0x9f000000
114
115/*
116 *  address definitions for several devices
117 *
118 */
119#define UART_OFFSET_1_8245 (0x04500)   
120#define UART_OFFSET_2_8245 (0x04600)
121#define UART_BASE_COM1     0xff800000
122#define UART_BASE_COM2     0xff800040
123
124#include <bsp/openpic.h>
125
126/* Note docs list 0x41000 but OpenPIC has a 0x1000 pad at the start
127 * assume that open pic specifies this pad but not mentioned in
128 * 8245 docs.
129 * This is an offset from EUMBBAR
130 */
131#define BSP_OPEN_PIC_BASE_OFFSET     0x40000 
132
133/* BSP_PIC_DO_EOI is optionally used by the 'vmeUniverse' driver
134 * to implement VME IRQ priorities in software.
135 * Note that this requires support by the interrupt controller
136 * driver (cf. libbsp/shared/powerpc/irq/openpic_i8259_irq.c)
137 * and the BSP-specific universe initialization/configuration
138 * (cf. libbsp/shared/powerpc/vme/VMEConfig.h vme_universe.c)
139 *
140 * ********* IMPORTANT NOTE ********
141 * When deriving from this file (new BSPs)
142 * DO NOT define "BSP_PIC_DO_EOI" if you don't know what
143 * you are doing i.e., w/o implementing the required pieces
144 * mentioned above.
145 * ********* IMPORTANT NOTE ********
146 */
147#define BSP_PIC_DO_EOI openpic_eoi(0)
148
149
150#ifndef ASM
151#define outport_byte(port,value) outb(value,port)
152#define outport_word(port,value) outw(value,port)
153#define outport_long(port,value) outl(value,port)
154
155#define inport_byte(port,value) (value = inb(port))
156#define inport_word(port,value) (value = inw(port))
157#define inport_long(port,value) (value = inl(port))
158
159/*
160 * EUMMBAR
161 */
162extern unsigned int EUMBBAR;
163
164/*
165 * Total memory
166 */
167extern unsigned int BSP_mem_size;
168
169/*
170 * PCI Bus Frequency
171 */
172extern unsigned int BSP_bus_frequency;
173
174/*
175 * processor clock frequency
176 */
177extern unsigned int BSP_processor_frequency;
178
179/*
180 * Time base divisior (how many tick for 1 second).
181 */
182extern unsigned int BSP_time_base_divisor;
183
184#define BSP_Convert_decrementer( _value ) \
185  ((unsigned long long) ((((unsigned long long)BSP_time_base_divisor) * 1000000ULL) /((unsigned long long) BSP_bus_frequency)) * ((unsigned long long) (_value)))
186
187#define Processor_Synchronize() \
188  asm(" eieio ")
189
190extern rtems_configuration_table  BSP_Configuration;
191extern void BSP_panic(char *s);
192extern void rtemsReboot(void);
193extern int BSP_disconnect_clock_handler (void);
194extern int BSP_connect_clock_handler (void);
195
196/*
197 * FLASH
198 */
199int BSP_FLASH_Enable_writes( uint32_t area );
200int BSP_FLASH_Disable_writes(  uint32_t area );
201void BSP_FLASH_set_page( uint8_t  page );
202
203#define BSP_FLASH_ENABLE_WRITES( _area) BSP_FLASH_Enable_writes( _area )
204#define BSP_FLASH_DISABLE_WRITES(_area) BSP_FLASH_Disable_writes( _area )
205#define BSP_FLASH_SET_PAGE(_page)       BSP_FLASH_set_page( _page )
206
207
208/* clear hostbridge errors
209 *
210 * enableMCP: whether to enable MCP checkstop / machine check interrupts
211 *            on the hostbridge and in HID0.
212 *
213 *            NOTE: HID0 and MEREN are left alone if this flag is 0
214 *
215 * quiet    : be silent
216 *
217 * RETURNS  : raven MERST register contents (lowermost 16 bits), 0 if
218 *            there were no errors
219 */
220extern unsigned long _BSP_clear_hostbridge_errors(int enableMCP, int quiet);
221
222#endif
223
224#endif
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