source: rtems/c/src/lib/libbsp/powerpc/ep1a/include/bsp.h @ a052181

4.115
Last change on this file since a052181 was a052181, checked in by Sebastian Huber <sebastian.huber@…>, on 11/14/12 at 08:59:10

score: Add RTEMS_FATAL_SOURCE_EXIT

Include <bsp/default-initial-extension.h> in all BSPs. Call
rtems_fatal() with RTEMS_FATAL_SOURCE_EXIT as source and the exit()
status code as fatal code in every bsp_cleanup(). Move previous
bsp_cleanup() code into bsp_fatal_extension().
  • Property mode set to 100644
File size: 6.7 KB
Line 
1/*
2 *  COPYRIGHT (c) 1989-2008.
3 *  On-Line Applications Research Corporation (OAR).
4 *
5 *  The license and distribution terms for this file may be
6 *  found in the file LICENSE in this distribution or at
7 *  http://www.rtems.com/license/LICENSE.
8 */
9
10#ifndef _BSP_H
11#define _BSP_H
12
13#include <bspopts.h>
14#include <bsp/default-initial-extension.h>
15
16#include <rtems.h>
17#include <rtems/console.h>
18#include <libcpu/io.h>
19#include <rtems/clockdrv.h>
20#include <bsp/vectors.h>
21
22/* fundamental addresses for BSP (CHRPxxx and PREPxxx are from libcpu/io.h) */
23#define _IO_BASE                CHRP_ISA_IO_BASE
24#define _ISA_MEM_BASE           CHRP_ISA_MEM_BASE
25/* address of our ram on the PCI bus   */
26#define PCI_DRAM_OFFSET         CHRP_PCI_DRAM_OFFSET
27#define PCI_MEM_BASE            0x80000000
28#define PCI_MEM_BASE_ADJUSTMENT 0
29/* address of our ram on the PCI bus   */
30#define PCI_DRAM_OFFSET         CHRP_PCI_DRAM_OFFSET
31
32/* offset of pci memory as seen from the CPU */
33#undef  PCI_MEM_BASE
34#define PCI_MEM_BASE            0x00000000
35
36/* Override the default values for the following     DEFAULT */
37#define PCI_CONFIG_ADDR                 0xfec00000  /* 0xcf8 */
38#define PCI_CONFIG_DATA                 0xfee00000  /* 0xcfc */
39
40/*
41 * EP1A configuration Registers.
42 * Note:  All addresses assume flash boot.
43 */
44
45#define EQUIPMENT_PRESENT_REGISTER1     ((volatile unsigned char *)0xffa00000)
46#define EQUIPMENT_PRESENT_REGISTER2     ((volatile unsigned char *)0xffa00008)
47#define BOARD_REVISION_REGISTER1        ((volatile unsigned char *)0xffa00010)
48#define BOARD_REVISION_REGISTER2        ((volatile unsigned char *)0xffa00018)
49#define GENERAL_REGISTER1               ((volatile unsigned char *)0xffa00020)
50#define GENERAL_REGISTER2               ((volatile unsigned char *)0xffa00028)
51#define WATCHDOG_TRIGGER                ((volatile unsigned char *)0xffa00030)
52
53/* EQUIPMENT_PRESENT_REGISTER1 */
54#define BANK_MEMORY_SIZE_128MB          0x20
55#define BANK_MEMORY_SIZE_64MB           0x10
56#define ECC_ENABLED                     0x04
57
58/* EQUIPMENT-PRESENT_REGISTER2 */
59#define PLL_CFG_MASK                     0xf8
60#define MHZ_33_66_200                    0x70   /* PCI MEM CPU Frequency */
61#define MHZ_33_100_200                   0x80   /* PCI MEM CPU Frequency */
62#define MHZ_33_66_266                    0xb0   /* PCI MEM CPU Frequency */
63#define MHZ_33_66_333                    0x50   /* PCI MEM CPU Frequency */
64#define MHZ_33_100_333                   0x08   /* PCI MEM CPU Frequency */
65#define MHZ_33_100_350                   0x78   /* PCI MEM CPU Frequency */
66
67#define PMC_SLOT1_PRESENT                0x02
68#define PMC_SLOT2_PRESENT                0x01
69
70/* BOARD_REVISION_REGISTER1 */
71#define ARTWORK_REVISION_MASK            0xf0
72#define BUILD_REVISION_MASK              0x0f
73
74/* BOARD_REVISION_REGISTER2 */
75#define HARDWARE_ID_MASK                 0xe0
76#define HARDWARE_ID_PPC5_EP1A            0xe0
77#define HARDWARE_ID_EP1B                 0xc0
78
79/* GENERAL_REGISTER1 */
80#define DISABLE_WATCHDOG                  0x80
81#define DISABLE_RESET_SWITCH              0x40
82#define DISABLE_USER_FLASH                0x20
83#define DISABLE_BOOT_FLASH                0x10
84#define LED4_OFF                          0x08
85#define LED3_OFF                          0x04
86#define LED2_OFF                          0x02
87#define LED1_OFF                          0x01
88
89
90/* GENERAL_REGISTER2 */
91#define BSP_FLASH_VPP_ENABLE              0x01
92#define BSP_FLASH_PAGE_MASK               0x38
93#define BSP_FLASH_PAGE_SHIFT              0x03
94#define BSP_BIT_SLOWSTART                 0x04
95#define BSP_OFFLINE                       0x02
96#define BSP_SYSFAIL                       0x01
97
98/* WATCHDOG_TRIGGER */
99#define BSP_FLASH_BASE                   0xff000000
100#define BSP_VME_A16_BASE                 0x9fff0000
101#define BSP_VME_A24_BASE                 0x9f000000
102
103/*
104 *  address definitions for several devices
105 *
106 */
107#define UART_OFFSET_1_8245 (0x04500)
108#define UART_OFFSET_2_8245 (0x04600)
109#define UART_BASE_COM1     0xff800000
110#define UART_BASE_COM2     0xff800040
111
112#include <bsp/openpic.h>
113
114/* Note docs list 0x41000 but OpenPIC has a 0x1000 pad at the start
115 * assume that open pic specifies this pad but not mentioned in
116 * 8245 docs.
117 * This is an offset from EUMBBAR
118 */
119#define BSP_OPEN_PIC_BASE_OFFSET     0x40000
120
121/* BSP_PIC_DO_EOI is optionally used by the 'vmeUniverse' driver
122 * to implement VME IRQ priorities in software.
123 * Note that this requires support by the interrupt controller
124 * driver (cf. libbsp/shared/powerpc/irq/openpic_i8259_irq.c)
125 * and the BSP-specific universe initialization/configuration
126 * (cf. libbsp/shared/powerpc/vme/VMEConfig.h vme_universe.c)
127 *
128 * ********* IMPORTANT NOTE ********
129 * When deriving from this file (new BSPs)
130 * DO NOT define "BSP_PIC_DO_EOI" if you don't know what
131 * you are doing i.e., w/o implementing the required pieces
132 * mentioned above.
133 * ********* IMPORTANT NOTE ********
134 */
135#define BSP_PIC_DO_EOI openpic_eoi(0)
136
137
138#ifndef ASM
139#define outport_byte(port,value) outb(value,port)
140#define outport_word(port,value) outw(value,port)
141#define outport_long(port,value) outl(value,port)
142
143#define inport_byte(port,value) (value = inb(port))
144#define inport_word(port,value) (value = inw(port))
145#define inport_long(port,value) (value = inl(port))
146
147/*
148 * EUMMBAR
149 */
150extern unsigned int EUMBBAR;
151
152/*
153 * Total memory
154 */
155extern unsigned int BSP_mem_size;
156
157/*
158 * PCI Bus Frequency
159 */
160extern unsigned int BSP_bus_frequency;
161
162/*
163 * processor clock frequency
164 */
165extern unsigned int BSP_processor_frequency;
166
167/*
168 * Time base divisior (how many tick for 1 second).
169 */
170extern unsigned int BSP_time_base_divisor;
171
172#define BSP_Convert_decrementer( _value ) \
173  ((unsigned long long) ((((unsigned long long)BSP_time_base_divisor) * 1000000ULL) /((unsigned long long) BSP_bus_frequency)) * ((unsigned long long) (_value)))
174
175#define Processor_Synchronize() \
176  __asm__ (" eieio ")
177
178extern void BSP_panic(char *s);
179extern int BSP_disconnect_clock_handler (void);
180extern int BSP_connect_clock_handler (void);
181
182/*
183 * FLASH
184 */
185int BSP_FLASH_Enable_writes( uint32_t area );
186int BSP_FLASH_Disable_writes(  uint32_t area );
187void BSP_FLASH_set_page( uint8_t  page );
188
189#define BSP_FLASH_ENABLE_WRITES( _area) BSP_FLASH_Enable_writes( _area )
190#define BSP_FLASH_DISABLE_WRITES(_area) BSP_FLASH_Disable_writes( _area )
191#define BSP_FLASH_SET_PAGE(_page)       BSP_FLASH_set_page( _page )
192
193/* clear hostbridge errors
194 *
195 * enableMCP: whether to enable MCP checkstop / machine check interrupts
196 *            on the hostbridge and in HID0.
197 *
198 *            NOTE: HID0 and MEREN are left alone if this flag is 0
199 *
200 * quiet    : be silent
201 *
202 * RETURNS  : raven MERST register contents (lowermost 16 bits), 0 if
203 *            there were no errors
204 */
205extern unsigned long _BSP_clear_hostbridge_errors(int enableMCP, int quiet);
206
207#endif
208
209#endif
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