1 | /* |
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2 | * COPYRIGHT (c) 1989-2008. |
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3 | * On-Line Applications Research Corporation (OAR). |
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4 | * |
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5 | * The license and distribution terms for this file may be |
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6 | * found in the file LICENSE in this distribution or at |
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7 | * http://www.rtems.com/license/LICENSE. |
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8 | * |
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9 | * $Id$ |
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10 | */ |
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11 | |
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12 | #ifndef _BSP_H |
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13 | #define _BSP_H |
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14 | |
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15 | #include <bspopts.h> |
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16 | |
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17 | #include <rtems.h> |
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18 | #include <rtems/console.h> |
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19 | #include <libcpu/io.h> |
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20 | #include <rtems/clockdrv.h> |
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21 | #include <bsp/vectors.h> |
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22 | |
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23 | /* fundamental addresses for BSP (CHRPxxx and PREPxxx are from libcpu/io.h) */ |
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24 | #define _IO_BASE CHRP_ISA_IO_BASE |
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25 | #define _ISA_MEM_BASE CHRP_ISA_MEM_BASE |
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26 | /* address of our ram on the PCI bus */ |
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27 | #define PCI_DRAM_OFFSET CHRP_PCI_DRAM_OFFSET |
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28 | #define PCI_MEM_BASE 0x80000000 |
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29 | #define PCI_MEM_BASE_ADJUSTMENT 0 |
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30 | /* address of our ram on the PCI bus */ |
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31 | #define PCI_DRAM_OFFSET CHRP_PCI_DRAM_OFFSET |
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32 | |
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33 | /* offset of pci memory as seen from the CPU */ |
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34 | #undef PCI_MEM_BASE |
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35 | #define PCI_MEM_BASE 0x00000000 |
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36 | |
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37 | /* Override the default values for the following DEFAULT */ |
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38 | #define PCI_CONFIG_ADDR 0xfec00000 /* 0xcf8 */ |
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39 | #define PCI_CONFIG_DATA 0xfee00000 /* 0xcfc */ |
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40 | |
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41 | /* |
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42 | * EP1A configuration Registers. |
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43 | * Note: All addresses assume flash boot. |
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44 | */ |
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45 | |
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46 | #define EQUIPMENT_PRESENT_REGISTER1 ((volatile unsigned char *)0xffa00000) |
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47 | #define EQUIPMENT_PRESENT_REGISTER2 ((volatile unsigned char *)0xffa00008) |
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48 | #define BOARD_REVISION_REGISTER1 ((volatile unsigned char *)0xffa00010) |
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49 | #define BOARD_REVISION_REGISTER2 ((volatile unsigned char *)0xffa00018) |
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50 | #define GENERAL_REGISTER1 ((volatile unsigned char *)0xffa00020) |
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51 | #define GENERAL_REGISTER2 ((volatile unsigned char *)0xffa00028) |
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52 | #define WATCHDOG_TRIGGER ((volatile unsigned char *)0xffa00030) |
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53 | |
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54 | /* EQUIPMENT_PRESENT_REGISTER1 */ |
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55 | #define BANK_MEMORY_SIZE_128MB 0x20 |
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56 | #define BANK_MEMORY_SIZE_64MB 0x10 |
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57 | #define ECC_ENABLED 0x04 |
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58 | |
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59 | /* EQUIPMENT-PRESENT_REGISTER2 */ |
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60 | #define PLL_CFG_MASK 0xf8 |
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61 | #define MHZ_33_66_200 0x70 /* PCI MEM CPU Frequency */ |
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62 | #define MHZ_33_100_200 0x80 /* PCI MEM CPU Frequency */ |
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63 | #define MHZ_33_66_266 0xb0 /* PCI MEM CPU Frequency */ |
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64 | #define MHZ_33_66_333 0x50 /* PCI MEM CPU Frequency */ |
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65 | #define MHZ_33_100_333 0x08 /* PCI MEM CPU Frequency */ |
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66 | #define MHZ_33_100_350 0x78 /* PCI MEM CPU Frequency */ |
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67 | |
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68 | #define PMC_SLOT1_PRESENT 0x02 |
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69 | #define PMC_SLOT2_PRESENT 0x01 |
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70 | |
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71 | /* BOARD_REVISION_REGISTER1 */ |
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72 | #define ARTWORK_REVISION_MASK 0xf0 |
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73 | #define BUILD_REVISION_MASK 0x0f |
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74 | |
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75 | /* BOARD_REVISION_REGISTER2 */ |
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76 | #define HARDWARE_ID_MASK 0xe0 |
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77 | #define HARDWARE_ID_PPC5_EP1A 0xe0 |
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78 | #define HARDWARE_ID_EP1B 0xc0 |
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79 | |
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80 | /* GENERAL_REGISTER1 */ |
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81 | #define DISABLE_WATCHDOG 0x80 |
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82 | #define DISABLE_RESET_SWITCH 0x40 |
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83 | #define DISABLE_USER_FLASH 0x20 |
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84 | #define DISABLE_BOOT_FLASH 0x10 |
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85 | #define LED4_OFF 0x08 |
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86 | #define LED3_OFF 0x04 |
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87 | #define LED2_OFF 0x02 |
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88 | #define LED1_OFF 0x01 |
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89 | |
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90 | |
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91 | /* GENERAL_REGISTER2 */ |
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92 | #define BSP_FLASH_VPP_ENABLE 0x01 |
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93 | #define BSP_FLASH_PAGE_MASK 0x38 |
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94 | #define BSP_FLASH_PAGE_SHIFT 0x03 |
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95 | #define BSP_BIT_SLOWSTART 0x04 |
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96 | #define BSP_OFFLINE 0x02 |
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97 | #define BSP_SYSFAIL 0x01 |
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98 | |
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99 | /* WATCHDOG_TRIGGER */ |
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100 | #define BSP_FLASH_BASE 0xff000000 |
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101 | #define BSP_VME_A16_BASE 0x9fff0000 |
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102 | #define BSP_VME_A24_BASE 0x9f000000 |
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103 | |
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104 | /* |
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105 | * address definitions for several devices |
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106 | * |
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107 | */ |
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108 | #define UART_OFFSET_1_8245 (0x04500) |
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109 | #define UART_OFFSET_2_8245 (0x04600) |
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110 | #define UART_BASE_COM1 0xff800000 |
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111 | #define UART_BASE_COM2 0xff800040 |
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112 | |
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113 | #include <bsp/openpic.h> |
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114 | |
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115 | /* Note docs list 0x41000 but OpenPIC has a 0x1000 pad at the start |
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116 | * assume that open pic specifies this pad but not mentioned in |
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117 | * 8245 docs. |
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118 | * This is an offset from EUMBBAR |
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119 | */ |
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120 | #define BSP_OPEN_PIC_BASE_OFFSET 0x40000 |
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121 | |
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122 | /* BSP_PIC_DO_EOI is optionally used by the 'vmeUniverse' driver |
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123 | * to implement VME IRQ priorities in software. |
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124 | * Note that this requires support by the interrupt controller |
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125 | * driver (cf. libbsp/shared/powerpc/irq/openpic_i8259_irq.c) |
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126 | * and the BSP-specific universe initialization/configuration |
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127 | * (cf. libbsp/shared/powerpc/vme/VMEConfig.h vme_universe.c) |
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128 | * |
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129 | * ********* IMPORTANT NOTE ******** |
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130 | * When deriving from this file (new BSPs) |
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131 | * DO NOT define "BSP_PIC_DO_EOI" if you don't know what |
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132 | * you are doing i.e., w/o implementing the required pieces |
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133 | * mentioned above. |
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134 | * ********* IMPORTANT NOTE ******** |
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135 | */ |
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136 | #define BSP_PIC_DO_EOI openpic_eoi(0) |
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137 | |
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138 | |
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139 | #ifndef ASM |
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140 | #define outport_byte(port,value) outb(value,port) |
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141 | #define outport_word(port,value) outw(value,port) |
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142 | #define outport_long(port,value) outl(value,port) |
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143 | |
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144 | #define inport_byte(port,value) (value = inb(port)) |
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145 | #define inport_word(port,value) (value = inw(port)) |
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146 | #define inport_long(port,value) (value = inl(port)) |
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147 | |
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148 | /* |
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149 | * EUMMBAR |
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150 | */ |
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151 | extern unsigned int EUMBBAR; |
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152 | |
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153 | /* |
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154 | * Total memory |
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155 | */ |
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156 | extern unsigned int BSP_mem_size; |
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157 | |
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158 | /* |
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159 | * PCI Bus Frequency |
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160 | */ |
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161 | extern unsigned int BSP_bus_frequency; |
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162 | |
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163 | /* |
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164 | * processor clock frequency |
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165 | */ |
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166 | extern unsigned int BSP_processor_frequency; |
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167 | |
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168 | /* |
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169 | * Time base divisior (how many tick for 1 second). |
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170 | */ |
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171 | extern unsigned int BSP_time_base_divisor; |
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172 | |
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173 | #define BSP_Convert_decrementer( _value ) \ |
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174 | ((unsigned long long) ((((unsigned long long)BSP_time_base_divisor) * 1000000ULL) /((unsigned long long) BSP_bus_frequency)) * ((unsigned long long) (_value))) |
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175 | |
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176 | #define Processor_Synchronize() \ |
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177 | __asm__ (" eieio ") |
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178 | |
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179 | extern void BSP_panic(char *s); |
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180 | extern int BSP_disconnect_clock_handler (void); |
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181 | extern int BSP_connect_clock_handler (void); |
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182 | |
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183 | /* |
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184 | * FLASH |
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185 | */ |
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186 | int BSP_FLASH_Enable_writes( uint32_t area ); |
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187 | int BSP_FLASH_Disable_writes( uint32_t area ); |
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188 | void BSP_FLASH_set_page( uint8_t page ); |
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189 | |
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190 | #define BSP_FLASH_ENABLE_WRITES( _area) BSP_FLASH_Enable_writes( _area ) |
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191 | #define BSP_FLASH_DISABLE_WRITES(_area) BSP_FLASH_Disable_writes( _area ) |
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192 | #define BSP_FLASH_SET_PAGE(_page) BSP_FLASH_set_page( _page ) |
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193 | |
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194 | /* clear hostbridge errors |
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195 | * |
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196 | * enableMCP: whether to enable MCP checkstop / machine check interrupts |
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197 | * on the hostbridge and in HID0. |
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198 | * |
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199 | * NOTE: HID0 and MEREN are left alone if this flag is 0 |
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200 | * |
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201 | * quiet : be silent |
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202 | * |
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203 | * RETURNS : raven MERST register contents (lowermost 16 bits), 0 if |
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204 | * there were no errors |
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205 | */ |
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206 | extern unsigned long _BSP_clear_hostbridge_errors(int enableMCP, int quiet); |
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207 | |
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208 | #endif |
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209 | |
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210 | #endif |
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