source: rtems/c/src/lib/libbsp/powerpc/ep1a/include/bsp.h @ 5134f172

4.115
Last change on this file since 5134f172 was 5134f172, checked in by Ralf Corsepius <ralf.corsepius@…>, on 02/11/11 at 12:44:30

2011-02-11 Ralf Corsépius <ralf.corsepius@…>

  • console/console.c, console/ns16550cfg.c, console/polled_io.c, include/bsp.h, include/tm27.h, startup/bspstart.c: Use "asm" instead of "asm" for improved c99-compliance.
  • Property mode set to 100644
File size: 6.6 KB
Line 
1/*
2 *  COPYRIGHT (c) 1989-2008.
3 *  On-Line Applications Research Corporation (OAR).
4 *
5 *  The license and distribution terms for this file may be
6 *  found in the file LICENSE in this distribution or at
7 *  http://www.rtems.com/license/LICENSE.
8 *
9 *  $Id$
10 */
11
12#ifndef _BSP_H
13#define _BSP_H
14
15#include <bspopts.h>
16
17#include <rtems.h>
18#include <rtems/console.h>
19#include <libcpu/io.h>
20#include <rtems/clockdrv.h>
21#include <bsp/vectors.h>
22
23/* fundamental addresses for BSP (CHRPxxx and PREPxxx are from libcpu/io.h) */
24#define _IO_BASE                CHRP_ISA_IO_BASE
25#define _ISA_MEM_BASE           CHRP_ISA_MEM_BASE
26/* address of our ram on the PCI bus   */
27#define PCI_DRAM_OFFSET         CHRP_PCI_DRAM_OFFSET
28#define PCI_MEM_BASE            0x80000000
29#define PCI_MEM_BASE_ADJUSTMENT 0
30/* address of our ram on the PCI bus   */
31#define PCI_DRAM_OFFSET         CHRP_PCI_DRAM_OFFSET
32
33/* offset of pci memory as seen from the CPU */
34#undef  PCI_MEM_BASE
35#define PCI_MEM_BASE            0x00000000
36
37/* Override the default values for the following     DEFAULT */
38#define PCI_CONFIG_ADDR                 0xfec00000  /* 0xcf8 */
39#define PCI_CONFIG_DATA                 0xfee00000  /* 0xcfc */
40
41/*
42 * EP1A configuration Registers.
43 * Note:  All addresses assume flash boot.
44 */
45
46#define EQUIPMENT_PRESENT_REGISTER1     ((volatile unsigned char *)0xffa00000)
47#define EQUIPMENT_PRESENT_REGISTER2     ((volatile unsigned char *)0xffa00008)
48#define BOARD_REVISION_REGISTER1        ((volatile unsigned char *)0xffa00010)
49#define BOARD_REVISION_REGISTER2        ((volatile unsigned char *)0xffa00018)
50#define GENERAL_REGISTER1               ((volatile unsigned char *)0xffa00020)
51#define GENERAL_REGISTER2               ((volatile unsigned char *)0xffa00028)
52#define WATCHDOG_TRIGGER                ((volatile unsigned char *)0xffa00030)
53
54/* EQUIPMENT_PRESENT_REGISTER1 */
55#define BANK_MEMORY_SIZE_128MB          0x20
56#define BANK_MEMORY_SIZE_64MB           0x10
57#define ECC_ENABLED                     0x04
58
59/* EQUIPMENT-PRESENT_REGISTER2 */
60#define PLL_CFG_MASK                     0xf8
61#define MHZ_33_66_200                    0x70   /* PCI MEM CPU Frequency */
62#define MHZ_33_100_200                   0x80   /* PCI MEM CPU Frequency */
63#define MHZ_33_66_266                    0xb0   /* PCI MEM CPU Frequency */
64#define MHZ_33_66_333                    0x50   /* PCI MEM CPU Frequency */
65#define MHZ_33_100_333                   0x08   /* PCI MEM CPU Frequency */
66#define MHZ_33_100_350                   0x78   /* PCI MEM CPU Frequency */
67
68#define PMC_SLOT1_PRESENT                0x02
69#define PMC_SLOT2_PRESENT                0x01
70
71/* BOARD_REVISION_REGISTER1 */
72#define ARTWORK_REVISION_MASK            0xf0
73#define BUILD_REVISION_MASK              0x0f
74
75/* BOARD_REVISION_REGISTER2 */
76#define HARDWARE_ID_MASK                 0xe0
77#define HARDWARE_ID_PPC5_EP1A            0xe0
78#define HARDWARE_ID_EP1B                 0xc0
79
80/* GENERAL_REGISTER1 */
81#define DISABLE_WATCHDOG                  0x80
82#define DISABLE_RESET_SWITCH              0x40
83#define DISABLE_USER_FLASH                0x20
84#define DISABLE_BOOT_FLASH                0x10
85#define LED4_OFF                          0x08
86#define LED3_OFF                          0x04
87#define LED2_OFF                          0x02
88#define LED1_OFF                          0x01
89
90
91/* GENERAL_REGISTER2 */
92#define BSP_FLASH_VPP_ENABLE              0x01
93#define BSP_FLASH_PAGE_MASK               0x38
94#define BSP_FLASH_PAGE_SHIFT              0x03
95#define BSP_BIT_SLOWSTART                 0x04
96#define BSP_OFFLINE                       0x02
97#define BSP_SYSFAIL                       0x01
98
99/* WATCHDOG_TRIGGER */
100#define BSP_FLASH_BASE                   0xff000000
101#define BSP_VME_A16_BASE                 0x9fff0000
102#define BSP_VME_A24_BASE                 0x9f000000
103
104/*
105 *  address definitions for several devices
106 *
107 */
108#define UART_OFFSET_1_8245 (0x04500)
109#define UART_OFFSET_2_8245 (0x04600)
110#define UART_BASE_COM1     0xff800000
111#define UART_BASE_COM2     0xff800040
112
113#include <bsp/openpic.h>
114
115/* Note docs list 0x41000 but OpenPIC has a 0x1000 pad at the start
116 * assume that open pic specifies this pad but not mentioned in
117 * 8245 docs.
118 * This is an offset from EUMBBAR
119 */
120#define BSP_OPEN_PIC_BASE_OFFSET     0x40000
121
122/* BSP_PIC_DO_EOI is optionally used by the 'vmeUniverse' driver
123 * to implement VME IRQ priorities in software.
124 * Note that this requires support by the interrupt controller
125 * driver (cf. libbsp/shared/powerpc/irq/openpic_i8259_irq.c)
126 * and the BSP-specific universe initialization/configuration
127 * (cf. libbsp/shared/powerpc/vme/VMEConfig.h vme_universe.c)
128 *
129 * ********* IMPORTANT NOTE ********
130 * When deriving from this file (new BSPs)
131 * DO NOT define "BSP_PIC_DO_EOI" if you don't know what
132 * you are doing i.e., w/o implementing the required pieces
133 * mentioned above.
134 * ********* IMPORTANT NOTE ********
135 */
136#define BSP_PIC_DO_EOI openpic_eoi(0)
137
138
139#ifndef ASM
140#define outport_byte(port,value) outb(value,port)
141#define outport_word(port,value) outw(value,port)
142#define outport_long(port,value) outl(value,port)
143
144#define inport_byte(port,value) (value = inb(port))
145#define inport_word(port,value) (value = inw(port))
146#define inport_long(port,value) (value = inl(port))
147
148/*
149 * EUMMBAR
150 */
151extern unsigned int EUMBBAR;
152
153/*
154 * Total memory
155 */
156extern unsigned int BSP_mem_size;
157
158/*
159 * PCI Bus Frequency
160 */
161extern unsigned int BSP_bus_frequency;
162
163/*
164 * processor clock frequency
165 */
166extern unsigned int BSP_processor_frequency;
167
168/*
169 * Time base divisior (how many tick for 1 second).
170 */
171extern unsigned int BSP_time_base_divisor;
172
173#define BSP_Convert_decrementer( _value ) \
174  ((unsigned long long) ((((unsigned long long)BSP_time_base_divisor) * 1000000ULL) /((unsigned long long) BSP_bus_frequency)) * ((unsigned long long) (_value)))
175
176#define Processor_Synchronize() \
177  __asm__ (" eieio ")
178
179extern void BSP_panic(char *s);
180extern int BSP_disconnect_clock_handler (void);
181extern int BSP_connect_clock_handler (void);
182
183/*
184 * FLASH
185 */
186int BSP_FLASH_Enable_writes( uint32_t area );
187int BSP_FLASH_Disable_writes(  uint32_t area );
188void BSP_FLASH_set_page( uint8_t  page );
189
190#define BSP_FLASH_ENABLE_WRITES( _area) BSP_FLASH_Enable_writes( _area )
191#define BSP_FLASH_DISABLE_WRITES(_area) BSP_FLASH_Disable_writes( _area )
192#define BSP_FLASH_SET_PAGE(_page)       BSP_FLASH_set_page( _page )
193
194/* clear hostbridge errors
195 *
196 * enableMCP: whether to enable MCP checkstop / machine check interrupts
197 *            on the hostbridge and in HID0.
198 *
199 *            NOTE: HID0 and MEREN are left alone if this flag is 0
200 *
201 * quiet    : be silent
202 *
203 * RETURNS  : raven MERST register contents (lowermost 16 bits), 0 if
204 *            there were no errors
205 */
206extern unsigned long _BSP_clear_hostbridge_errors(int enableMCP, int quiet);
207
208#endif
209
210#endif
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