1 | /* rsPMCQ1.c - Radstone PMCQ1 Common Initialisation Code |
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2 | * |
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3 | * Copyright 2000 Radstone Technology |
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4 | * |
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5 | * THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY |
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6 | * KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE |
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7 | * IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK |
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8 | * AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU. |
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9 | * |
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10 | * You are hereby granted permission to use, copy, modify, and distribute |
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11 | * this file, provided that this notice, plus the above copyright notice |
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12 | * and disclaimer, appears in all copies. Radstone Technology will provide |
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13 | * no support for this code. |
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14 | * |
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15 | * COPYRIGHT (c) 2005. |
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16 | * On-Line Applications Research Corporation (OAR). |
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17 | * |
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18 | * The license and distribution terms for this file may be |
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19 | * found in the file LICENSE in this distribution or at |
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20 | * http://www.rtems.org/license/LICENSE. |
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21 | * |
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22 | */ |
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23 | |
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24 | /* |
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25 | DESCRIPTION |
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26 | These functions are responsible for scanning for PMCQ1's and setting up |
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27 | the Motorola MC68360's if present. |
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28 | |
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29 | USAGE |
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30 | call rsPMCQ1Init() to perform ba sic initialisation of the PMCQ1's. |
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31 | */ |
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32 | |
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33 | /* includes */ |
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34 | #include <libcpu/io.h> |
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35 | #include <bsp/irq.h> |
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36 | #include <stdlib.h> |
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37 | #include <rtems/bspIo.h> |
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38 | #include <bsp/pci.h> |
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39 | #include <bsp.h> |
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40 | #include "rsPMCQ1.h" |
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41 | #include "m68360.h" |
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42 | |
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43 | /* defines */ |
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44 | #if 1 |
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45 | #define DEBUG_360 |
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46 | #endif |
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47 | |
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48 | /* Local data */ |
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49 | PPMCQ1BoardData pmcq1BoardData = NULL; |
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50 | |
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51 | static unsigned char rsPMCQ1Initialized = FALSE; |
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52 | |
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53 | /* forward declarations */ |
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54 | |
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55 | static void MsDelay(void) |
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56 | { |
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57 | printk("."); |
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58 | } |
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59 | |
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60 | static void write8( int addr, int data ){ |
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61 | out_8((void *)addr, (unsigned char)data); |
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62 | } |
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63 | |
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64 | static void write16( int addr, int data ) { |
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65 | out_be16((void *)addr, (short)data ); |
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66 | } |
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67 | |
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68 | static void write32( int addr, int data ) { |
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69 | out_be32((unsigned int *)addr, data ); |
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70 | } |
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71 | |
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72 | static void rsPMCQ1_scc_nullFunc(void) {} |
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73 | |
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74 | /******************************************************************************* |
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75 | * rsPMCQ1Int - handle a PMCQ1 interrupt |
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76 | * |
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77 | * This routine gets called when the QUICC or MA causes |
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78 | * an interrupt. |
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79 | * |
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80 | * RETURNS: NONE. |
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81 | */ |
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82 | |
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83 | static void rsPMCQ1Int( void *ptr ) |
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84 | { |
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85 | unsigned long status; |
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86 | unsigned long status1; |
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87 | unsigned long mask; |
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88 | uint32_t data; |
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89 | PPMCQ1BoardData boardData = ptr; |
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90 | |
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91 | status = PMCQ1_Read_EPLD(boardData->baseaddr, PMCQ1_INT_STATUS ); |
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92 | mask = PMCQ1_Read_EPLD(boardData->baseaddr, PMCQ1_INT_MASK ); |
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93 | |
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94 | if (((mask & PMCQ1_INT_MASK_QUICC) == 0) && (status & PMCQ1_INT_STATUS_QUICC)) |
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95 | { |
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96 | /* If there is a handler call it otherwise mask the interrupt */ |
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97 | if (boardData->quiccInt) { |
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98 | boardData->quiccInt(boardData->quiccArg); |
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99 | } else { |
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100 | *(volatile unsigned long *)(boardData->baseaddr + PMCQ1_INT_MASK) |= PMCQ1_INT_MASK_QUICC; |
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101 | } |
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102 | } |
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103 | |
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104 | if (((mask & PMCQ1_INT_MASK_MA) == 0) && (status & PMCQ1_INT_STATUS_MA)) |
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105 | { |
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106 | /* If there is a handler call it otherwise mask the interrupt */ |
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107 | if (boardData->maInt) { |
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108 | boardData->maInt(boardData->maArg); |
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109 | |
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110 | data = PMCQ1_Read_EPLD(boardData->baseaddr, PMCQ1_INT_STATUS ); |
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111 | data &= (~PMCQ1_INT_STATUS_MA); |
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112 | PMCQ1_Write_EPLD(boardData->baseaddr, PMCQ1_INT_STATUS, data ); |
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113 | |
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114 | } else { |
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115 | *(volatile unsigned long *)(boardData->baseaddr + PMCQ1_INT_MASK) |= PMCQ1_INT_MASK_MA; |
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116 | } |
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117 | } |
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118 | |
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119 | RTEMS_COMPILER_MEMORY_BARRIER(); |
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120 | |
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121 | /* Clear Interrupt on QSPAN */ |
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122 | *(volatile unsigned long *)(boardData->bridgeaddr + 0x600) = 0x00001000; |
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123 | |
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124 | /* read back the status register to ensure that the pci write has completed */ |
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125 | status1 = *(volatile unsigned long *)(boardData->bridgeaddr + 0x600); |
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126 | (void) status1; /* avoid set but not used warning */ |
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127 | RTEMS_COMPILER_MEMORY_BARRIER(); |
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128 | |
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129 | } |
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130 | |
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131 | |
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132 | /******************************************************************************* |
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133 | * |
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134 | * rsPMCQ1MaIntConnect - connect a MiniAce interrupt routine |
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135 | * |
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136 | * This routine is called to connect a MiniAce interrupt handler |
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137 | * upto a PMCQ1. |
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138 | * |
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139 | * RETURNS: OK if PMCQ1 found, ERROR if not. |
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140 | */ |
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141 | |
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142 | unsigned int rsPMCQ1MaIntConnect ( |
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143 | unsigned long busNo, /* Pci Bus number of PMCQ1 */ |
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144 | unsigned long slotNo, /* Pci Slot number of PMCQ1 */ |
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145 | unsigned long funcNo, /* Pci Function number of PMCQ1 */ |
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146 | FUNCTION_PTR routine,/* interrupt routine */ |
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147 | uintptr_t arg /* argument to pass to interrupt routine */ |
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148 | ) |
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149 | { |
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150 | PPMCQ1BoardData boardData; |
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151 | uint32_t data; |
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152 | unsigned int status = RTEMS_IO_ERROR; |
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153 | |
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154 | for (boardData = pmcq1BoardData; boardData; boardData = boardData->pNext) |
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155 | { |
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156 | if ((boardData->busNo == busNo) && (boardData->slotNo == slotNo) && |
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157 | (boardData->funcNo == funcNo)) |
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158 | { |
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159 | boardData->maInt = routine; |
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160 | boardData->maArg = arg; |
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161 | |
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162 | data = PMCQ1_Read_EPLD(boardData->baseaddr, PMCQ1_INT_MASK ); |
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163 | data &= (~PMCQ1_INT_MASK_MA); |
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164 | PMCQ1_Write_EPLD(boardData->baseaddr, PMCQ1_INT_MASK, data ); |
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165 | |
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166 | data = PMCQ1_Read_EPLD(boardData->baseaddr, PMCQ1_INT_STATUS ); |
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167 | data &= (~PMCQ1_INT_STATUS_MA); |
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168 | PMCQ1_Write_EPLD(boardData->baseaddr, PMCQ1_INT_STATUS, data ); |
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169 | |
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170 | status = RTEMS_SUCCESSFUL; |
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171 | break; |
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172 | } |
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173 | } |
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174 | |
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175 | return (status); |
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176 | } |
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177 | |
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178 | /******************************************************************************* |
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179 | * |
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180 | * rsPMCQ1QuiccIntConnect - connect a Quicc interrupt routine |
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181 | * |
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182 | * This routine is called to connect a Quicc interrupt handler |
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183 | * upto a PMCQ1. |
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184 | * |
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185 | * RETURNS: OK if PMCQ1 found, ERROR if not. |
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186 | */ |
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187 | unsigned int rsPMCQ1QuiccIntConnect( |
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188 | unsigned long busNo, /* Pci Bus number of PMCQ1 */ |
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189 | unsigned long slotNo, /* Pci Slot number of PMCQ1 */ |
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190 | unsigned long funcNo, /* Pci Function number of PMCQ1 */ |
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191 | FUNCTION_PTR routine,/* interrupt routine */ |
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192 | uintptr_t arg /* argument to pass to interrupt routine */ |
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193 | ) |
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194 | { |
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195 | PPMCQ1BoardData boardData; |
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196 | unsigned int status = RTEMS_IO_ERROR; |
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197 | |
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198 | for (boardData = pmcq1BoardData; boardData; boardData = boardData->pNext) |
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199 | { |
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200 | if ((boardData->busNo == busNo) && (boardData->slotNo == slotNo) && |
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201 | (boardData->funcNo == funcNo)) |
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202 | { |
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203 | boardData->quiccInt = routine; |
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204 | boardData->quiccArg = arg; |
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205 | status = RTEMS_SUCCESSFUL; |
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206 | break; |
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207 | } |
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208 | } |
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209 | return (status); |
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210 | } |
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211 | |
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212 | /******************************************************************************* |
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213 | * |
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214 | * rsPMCQ1Init - initialize the PMCQ1's |
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215 | * |
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216 | * This routine is called to initialize the PCI card to a quiescent state. |
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217 | * |
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218 | * RETURNS: OK if PMCQ1 found, ERROR if not. |
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219 | */ |
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220 | |
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221 | unsigned int rsPMCQ1Init(void) |
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222 | { |
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223 | int busNo; |
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224 | int slotNo; |
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225 | uint32_t baseaddr = 0; |
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226 | uint32_t bridgeaddr = 0; |
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227 | unsigned long pbti0_ctl; |
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228 | int i; |
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229 | unsigned char int_vector; |
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230 | int fun; |
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231 | uint32_t temp; |
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232 | PPMCQ1BoardData boardData; |
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233 | rtems_irq_connect_data IrqData = { |
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234 | .name = 0, |
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235 | .hdl = rsPMCQ1Int, |
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236 | .handle = NULL, |
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237 | .on = (rtems_irq_enable) rsPMCQ1_scc_nullFunc, |
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238 | .off = (rtems_irq_disable) rsPMCQ1_scc_nullFunc, |
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239 | .isOn = (rtems_irq_is_enabled) rsPMCQ1_scc_nullFunc, |
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240 | }; |
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241 | |
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242 | if (rsPMCQ1Initialized) |
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243 | { |
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244 | return RTEMS_SUCCESSFUL; |
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245 | } |
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246 | for (i=0;;i++){ |
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247 | if ( pci_find_device(PCI_VEN_ID_RADSTONE, PCI_DEV_ID_PMCQ1, i, &busNo, &slotNo, &fun) != 0 ) |
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248 | break; |
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249 | |
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250 | pci_read_config_dword(busNo, slotNo, 0, PCI_BASE_ADDRESS_2, &baseaddr); |
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251 | pci_read_config_dword(busNo, slotNo, 0, PCI_BASE_ADDRESS_0, &bridgeaddr); |
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252 | #ifdef DEBUG_360 |
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253 | printk("PMCQ1 baseaddr 0x%08x bridgeaddr 0x%08x\n", baseaddr, bridgeaddr ); |
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254 | #endif |
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255 | |
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256 | /* Set function code to normal mode and enable window */ |
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257 | pbti0_ctl = *(unsigned long *)(bridgeaddr + 0x100) & 0xff0fffff; |
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258 | eieio(); |
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259 | *(unsigned long *)(bridgeaddr + 0x100) = pbti0_ctl | 0x00500080; |
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260 | eieio(); |
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261 | |
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262 | /* Assert QBUS reset */ |
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263 | *(unsigned long *)(bridgeaddr + 0x800) |= 0x00000080; |
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264 | eieio(); |
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265 | |
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266 | /* |
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267 | * Hold QBus in reset for 1ms |
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268 | */ |
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269 | MsDelay(); |
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270 | |
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271 | /* Take QBUS out of reset */ |
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272 | *(unsigned long *)(bridgeaddr + 0x800) &= ~0x00000080; |
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273 | eieio(); |
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274 | |
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275 | MsDelay(); |
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276 | |
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277 | /* If a QUICC is fitted initialise it */ |
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278 | if (PMCQ1_Read_EPLD(baseaddr, PMCQ1_BUILD_OPTION) & PMCQ1_QUICC_FITTED) |
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279 | { |
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280 | #ifdef DEBUG_360 |
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281 | printk(" Found QUICC busNo %d slotNo %d\n", busNo, slotNo); |
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282 | #endif |
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283 | |
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284 | /* Initialise MBAR (must use function code of 7) */ |
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285 | *(unsigned long *)(bridgeaddr + 0x100) = pbti0_ctl | 0x00700080; |
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286 | eieio(); |
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287 | |
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288 | /* place internal 8K SRAM and registers at address 0x0 */ |
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289 | *(unsigned long *)(baseaddr + Q1_360_MBAR) = 0x1; |
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290 | eieio(); |
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291 | |
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292 | /* Set function code to normal mode */ |
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293 | *(unsigned long *)(bridgeaddr + 0x100) = pbti0_ctl | 0x00500080; |
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294 | eieio(); |
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295 | |
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296 | /* Disable the SWT and perform basic initialisation */ |
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297 | write8(baseaddr+Q1_360_SIM_SYPCR,0); |
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298 | eieio(); |
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299 | |
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300 | write32(baseaddr+Q1_360_SIM_MCR,0xa0001029); |
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301 | write16(baseaddr+Q1_360_SIM_PICR,0); |
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302 | write16(baseaddr+Q1_360_SIM_PITR,0); |
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303 | |
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304 | write16(baseaddr+Q1_360_CPM_ICCR,0x770); |
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305 | write16(baseaddr+Q1_360_CPM_SDCR,0x770); |
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306 | write32(baseaddr+Q1_360_CPM_CICR,0x00e49f00); |
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307 | write16(baseaddr+Q1_360_SIM_PEPAR,0x2080); |
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308 | eieio(); |
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309 | |
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310 | /* Enable SRAM */ |
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311 | write32(baseaddr+Q1_360_SIM_GMR,0x00001000); /* external master wait state */ |
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312 | eieio(); |
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313 | write32(baseaddr+Q1_360_SIM_OR0,0x1ff00000); /*| MEMC_OR_FC*/ |
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314 | eieio(); |
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315 | write32(baseaddr+Q1_360_SIM_BR0,0); |
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316 | eieio(); |
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317 | write32(baseaddr+Q1_360_SIM_OR1,(0x5ff00000 | 0x00000780)); /*| MEMC_OR_FC*/ |
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318 | eieio(); |
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319 | write32(baseaddr+Q1_360_SIM_BR1,(0x00000040 | 0x00000001 | 0x00200280) ); |
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320 | eieio(); |
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321 | } |
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322 | |
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323 | /* |
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324 | * If a second PCI window is present then make it opposite |
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325 | * endian to simplify 1553 integration. |
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326 | */ |
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327 | pci_read_config_dword(busNo, slotNo, 0, PCI_BASE_ADDRESS_3, &temp); |
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328 | if (temp) { |
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329 | *(unsigned long *)(bridgeaddr + 0x110) |= 0x00500880; |
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330 | } |
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331 | |
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332 | /* |
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333 | * Create descriptor structure for this card |
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334 | */ |
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335 | if ((boardData = malloc(sizeof(struct _PMCQ1BoardData))) == NULL) |
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336 | { |
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337 | printk("Error Unable to allocate memory for _PMCQ1BoardData\n"); |
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338 | return(RTEMS_IO_ERROR); |
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339 | } |
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340 | |
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341 | boardData->pNext = pmcq1BoardData; |
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342 | boardData->busNo = busNo; |
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343 | boardData->slotNo = slotNo; |
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344 | boardData->funcNo = 0; |
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345 | boardData->baseaddr = baseaddr; |
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346 | boardData->bridgeaddr = bridgeaddr; |
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347 | boardData->quiccInt = NULL; |
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348 | boardData->maInt = NULL; |
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349 | pmcq1BoardData = boardData; |
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350 | mc68360_scc_create_chip( boardData, int_vector ); |
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351 | |
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352 | /* |
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353 | * Connect PMCQ1 interrupt handler. |
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354 | */ |
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355 | pci_read_config_byte(busNo, slotNo, 0, 0x3c, &int_vector); |
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356 | #ifdef DEBUG_360 |
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357 | printk("PMCQ1 int_vector %d\n", int_vector); |
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358 | #endif |
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359 | IrqData.name = ((unsigned int)BSP_PCI_IRQ0 + int_vector); |
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360 | IrqData.handle = boardData; |
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361 | if (!BSP_install_rtems_shared_irq_handler (&IrqData)) { |
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362 | printk("Error installing interrupt handler!\n"); |
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363 | rtems_fatal_error_occurred(1); |
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364 | } |
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365 | |
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366 | /* |
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367 | * Enable PMCQ1 Interrupts from QSPAN-II |
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368 | */ |
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369 | |
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370 | *(unsigned long *)(bridgeaddr + 0x600) = 0x00001000; |
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371 | eieio(); |
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372 | *(unsigned long *)(bridgeaddr + 0x604) |= 0x00001000; |
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373 | |
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374 | eieio(); |
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375 | } |
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376 | |
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377 | if (i > 0) |
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378 | { |
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379 | rsPMCQ1Initialized = TRUE; |
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380 | } |
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381 | return((i > 0) ? RTEMS_SUCCESSFUL : RTEMS_IO_ERROR); |
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382 | } |
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383 | |
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384 | uint32_t PMCQ1_Read_EPLD( uint32_t base, uint32_t reg ) |
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385 | { |
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386 | uint32_t data; |
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387 | |
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388 | data = ( *((unsigned long *) (base + reg)) ); |
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389 | #ifdef DEBUG_360 |
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390 | printk("EPLD Read 0x%x: 0x%08x\n", reg + base, data ); |
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391 | #endif |
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392 | return data; |
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393 | } |
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394 | |
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395 | void PMCQ1_Write_EPLD( uint32_t base, uint32_t reg, uint32_t data ) |
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396 | { |
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397 | *((unsigned long *) (base + reg)) = data; |
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398 | #ifdef DEBUG_360 |
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399 | printk("EPLD Write 0x%x: 0x%08x\n", reg+base, data ); |
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400 | #endif |
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401 | } |
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402 | |
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