1 | /* rsPMCQ1.c - Radstone PMCQ1 Common Initialisation Code |
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2 | * |
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3 | * Copyright 2000 Radstone Technology |
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4 | * |
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5 | * THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY |
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6 | * KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE |
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7 | * IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK |
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8 | * AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU. |
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9 | * |
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10 | * You are hereby granted permission to use, copy, modify, and distribute |
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11 | * this file, provided that this notice, plus the above copyright notice |
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12 | * and disclaimer, appears in all copies. Radstone Technology will provide |
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13 | * no support for this code. |
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14 | * |
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15 | * COPYRIGHT (c) 2005. |
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16 | * On-Line Applications Research Corporation (OAR). |
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17 | * |
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18 | * The license and distribution terms for this file may be |
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19 | * found in the file LICENSE in this distribution or at |
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20 | * http://www.rtems.com/license/LICENSE. |
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21 | * |
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22 | */ |
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23 | |
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24 | /* |
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25 | DESCRIPTION |
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26 | These functions are responsible for scanning for PMCQ1's and setting up |
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27 | the Motorola MC68360's if present. |
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28 | |
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29 | USAGE |
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30 | call rsPMCQ1Init() to perform ba sic initialisation of the PMCQ1's. |
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31 | */ |
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32 | |
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33 | /* includes */ |
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34 | #include <libcpu/io.h> |
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35 | #include <bsp/irq.h> |
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36 | #include <stdlib.h> |
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37 | #include <rtems/bspIo.h> |
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38 | #include <bsp/pci.h> |
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39 | #include <bsp.h> |
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40 | #include "rsPMCQ1.h" |
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41 | #include "m68360.h" |
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42 | |
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43 | /* defines */ |
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44 | #if 0 |
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45 | #define DEBUG_360 |
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46 | #endif |
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47 | |
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48 | /* Local data */ |
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49 | PPMCQ1BoardData pmcq1BoardData = NULL; |
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50 | |
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51 | static unsigned char rsPMCQ1Initialized = FALSE; |
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52 | |
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53 | /* forward declarations */ |
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54 | |
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55 | /* local Qspan II serial eeprom table */ |
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56 | static unsigned char rsPMCQ1eeprom[] = |
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57 | { |
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58 | 0x00, /* Byte 0 - PCI_SID */ |
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59 | 0x00, /* Byte 1 - PCI_SID */ |
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60 | 0x00, /* Byte 2 - PCI_SID */ |
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61 | 0x00, /* Byte 3 - PCI_SID */ |
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62 | 0x00, /* Byte 4 - PBROM_CTL */ |
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63 | 0x00, /* Byte 5 - PBROM_CTL */ |
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64 | 0x00, /* Byte 6 - PBROM_CTL */ |
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65 | 0x2C, /* Byte 7 - PBTI0_CTL */ |
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66 | 0xB0, /* Byte 8 - PBTI1_CTL */ |
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67 | 0x00, /* Byte 9 - QBSI0_AT */ |
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68 | 0x00, /* Byte 10 - QBSI0_AT */ |
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69 | 0x02, /* Byte 11 - QBSI0_AT */ |
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70 | 0x00, /* Byte 12 - PCI_ID */ |
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71 | 0x07, /* Byte 13 - PCI_ID */ |
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72 | 0x11, /* Byte 14 - PCI_ID */ |
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73 | 0xB5, /* Byte 15 - PCI_ID */ |
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74 | 0x06, /* Byte 16 - PCI_CLASS */ |
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75 | 0x80, /* Byte 17 - PCI_CLASS */ |
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76 | 0x00, /* Byte 18 - PCI_CLASS */ |
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77 | 0x00, /* Byte 19 - PCI_MISC1 */ |
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78 | 0x00, /* Byte 20 - PCI_MISC1 */ |
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79 | 0xC0, /* Byte 21 - PCI_PMC */ |
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80 | 0x00 /* Byte 22 - PCI_BST */ |
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81 | }; |
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82 | |
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83 | void MsDelay() |
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84 | { |
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85 | printk("."); |
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86 | } |
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87 | |
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88 | void write8( int addr, int data ){ |
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89 | out_8((void *)addr, (unsigned char)data); |
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90 | } |
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91 | |
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92 | void write16( int addr, int data ) { |
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93 | out_be16((void *)addr, (short)data ); |
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94 | } |
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95 | |
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96 | void write32( int addr, int data ) { |
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97 | out_be32((unsigned int *)addr, data ); |
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98 | } |
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99 | |
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100 | int read32( int addr){ |
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101 | return in_be32((unsigned int *)addr); |
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102 | } |
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103 | |
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104 | |
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105 | void rsPMCQ1_scc_nullFunc() {} |
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106 | |
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107 | /******************************************************************************* |
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108 | * rsPMCQ1Int - handle a PMCQ1 interrupt |
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109 | * |
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110 | * This routine gets called when the QUICC or MA causes |
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111 | * an interrupt. |
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112 | * |
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113 | * RETURNS: NONE. |
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114 | */ |
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115 | |
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116 | void rsPMCQ1Int( void *ptr ) |
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117 | { |
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118 | unsigned long status; |
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119 | unsigned long status1; |
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120 | unsigned long mask; |
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121 | PPMCQ1BoardData boardData = ptr; |
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122 | |
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123 | status = PMCQ1_Read_EPLD(boardData->baseaddr, PMCQ1_INT_STATUS ); |
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124 | mask = PMCQ1_Read_EPLD(boardData->baseaddr, PMCQ1_INT_MASK ); |
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125 | |
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126 | if (((mask & PMCQ1_INT_MASK_QUICC) == 0) && (status & PMCQ1_INT_STATUS_QUICC)) |
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127 | { |
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128 | /* If there is a handler call it otherwise mask the interrupt */ |
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129 | if (boardData->quiccInt) { |
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130 | boardData->quiccInt(boardData->quiccArg); |
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131 | } else { |
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132 | *(unsigned long *)(boardData->baseaddr + PMCQ1_INT_MASK) |= PMCQ1_INT_MASK_QUICC; |
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133 | } |
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134 | } |
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135 | |
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136 | if (((mask & PMCQ1_INT_MASK_MA) == 0) && (status & PMCQ1_INT_STATUS_MA)) |
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137 | { |
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138 | /* If there is a handler call it otherwise mask the interrupt */ |
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139 | if (boardData->maInt) { |
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140 | boardData->maInt(boardData->maArg); |
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141 | } else { |
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142 | *(unsigned long *)(boardData->baseaddr + PMCQ1_INT_MASK) |= PMCQ1_INT_MASK_MA; |
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143 | } |
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144 | } |
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145 | |
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146 | /* Clear Interrupt on QSPAN */ |
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147 | *(unsigned long *)(boardData->bridgeaddr + 0x600) = 0x00001000; |
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148 | |
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149 | /* read back the status register to ensure that the pci write has completed */ |
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150 | status1 = *(volatile unsigned long *)(boardData->bridgeaddr + 0x600); |
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151 | } |
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152 | |
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153 | |
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154 | /******************************************************************************* |
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155 | * |
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156 | * rsPMCQ1MaIntConnect - connect a MiniAce interrupt routine |
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157 | * |
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158 | * This routine is called to connect a MiniAce interrupt handler |
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159 | * upto a PMCQ1. |
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160 | * |
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161 | * RETURNS: OK if PMCQ1 found, ERROR if not. |
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162 | */ |
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163 | |
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164 | unsigned int rsPMCQ1MaIntConnect ( |
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165 | unsigned long busNo, /* Pci Bus number of PMCQ1 */ |
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166 | unsigned long slotNo, /* Pci Slot number of PMCQ1 */ |
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167 | unsigned long funcNo, /* Pci Function number of PMCQ1 */ |
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168 | rtems_irq_hdl routine,/* interrupt routine */ |
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169 | rtems_irq_hdl_param arg /* argument to pass to interrupt routine */ |
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170 | ) |
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171 | { |
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172 | PPMCQ1BoardData boardData; |
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173 | unsigned int status = RTEMS_IO_ERROR; |
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174 | |
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175 | for (boardData = pmcq1BoardData; boardData; boardData = boardData->pNext) |
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176 | { |
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177 | if ((boardData->busNo == busNo) && (boardData->slotNo == slotNo) && |
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178 | (boardData->funcNo == funcNo)) |
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179 | { |
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180 | boardData->maInt = routine; |
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181 | boardData->maArg = arg; |
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182 | status = RTEMS_SUCCESSFUL; |
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183 | break; |
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184 | } |
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185 | } |
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186 | |
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187 | return (status); |
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188 | } |
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189 | |
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190 | /******************************************************************************* |
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191 | * |
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192 | * rsPMCQ1MaIntDisconnect - disconnect a MiniAce interrupt routine |
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193 | * |
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194 | * This routine is called to disconnect a MiniAce interrupt handler |
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195 | * from a PMCQ1. It also masks the interrupt source on the PMCQ1. |
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196 | * |
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197 | * RETURNS: OK if PMCQ1 found, ERROR if not. |
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198 | */ |
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199 | |
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200 | unsigned int rsPMCQ1MaIntDisconnect( |
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201 | unsigned long busNo, /* Pci Bus number of PMCQ1 */ |
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202 | unsigned long slotNo, /* Pci Slot number of PMCQ1 */ |
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203 | unsigned long funcNo /* Pci Function number of PMCQ1 */ |
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204 | ) |
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205 | { |
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206 | PPMCQ1BoardData boardData; |
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207 | unsigned int status = RTEMS_IO_ERROR; |
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208 | |
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209 | for (boardData = pmcq1BoardData; boardData; boardData = boardData->pNext) { |
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210 | if ((boardData->busNo == busNo) && (boardData->slotNo == slotNo) && |
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211 | (boardData->funcNo == funcNo)) |
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212 | { |
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213 | boardData->maInt = NULL; |
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214 | *(unsigned long *)(boardData->baseaddr + PMCQ1_INT_MASK) |= PMCQ1_INT_MASK_MA; |
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215 | status = RTEMS_SUCCESSFUL; |
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216 | break; |
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217 | } |
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218 | } |
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219 | |
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220 | return (status); |
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221 | } |
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222 | |
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223 | /******************************************************************************* |
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224 | * |
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225 | * rsPMCQ1QuiccIntConnect - connect a Quicc interrupt routine |
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226 | * |
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227 | * This routine is called to connect a Quicc interrupt handler |
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228 | * upto a PMCQ1. |
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229 | * |
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230 | * RETURNS: OK if PMCQ1 found, ERROR if not. |
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231 | */ |
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232 | |
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233 | unsigned int rsPMCQ1QuiccIntConnect( |
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234 | unsigned long busNo, /* Pci Bus number of PMCQ1 */ |
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235 | unsigned long slotNo, /* Pci Slot number of PMCQ1 */ |
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236 | unsigned long funcNo, /* Pci Function number of PMCQ1 */ |
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237 | rtems_irq_hdl routine,/* interrupt routine */ |
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238 | rtems_irq_hdl_param arg /* argument to pass to interrupt routine */ |
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239 | ) |
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240 | { |
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241 | PPMCQ1BoardData boardData; |
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242 | unsigned int status = RTEMS_IO_ERROR; |
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243 | |
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244 | for (boardData = pmcq1BoardData; boardData; boardData = boardData->pNext) |
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245 | { |
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246 | if ((boardData->busNo == busNo) && (boardData->slotNo == slotNo) && |
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247 | (boardData->funcNo == funcNo)) |
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248 | { |
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249 | boardData->quiccInt = routine; |
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250 | boardData->quiccArg = arg; |
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251 | status = RTEMS_SUCCESSFUL; |
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252 | break; |
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253 | } |
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254 | } |
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255 | return (status); |
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256 | } |
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257 | |
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258 | /******************************************************************************* |
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259 | * |
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260 | * rsPMCQ1QuiccIntDisconnect - disconnect a Quicc interrupt routine |
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261 | * |
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262 | * This routine is called to disconnect a Quicc interrupt handler |
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263 | * from a PMCQ1. It also masks the interrupt source on the PMCQ1. |
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264 | * |
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265 | * RETURNS: OK if PMCQ1 found, ERROR if not. |
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266 | */ |
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267 | |
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268 | unsigned int rsPMCQ1QuiccIntDisconnect( |
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269 | unsigned long busNo, /* Pci Bus number of PMCQ1 */ |
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270 | unsigned long slotNo, /* Pci Slot number of PMCQ1 */ |
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271 | unsigned long funcNo /* Pci Function number of PMCQ1 */ |
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272 | ) |
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273 | { |
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274 | PPMCQ1BoardData boardData; |
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275 | unsigned int status = RTEMS_IO_ERROR; |
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276 | |
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277 | for (boardData = pmcq1BoardData; boardData; boardData = boardData->pNext) |
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278 | { |
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279 | if ((boardData->busNo == busNo) && (boardData->slotNo == slotNo) && |
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280 | (boardData->funcNo == funcNo)) |
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281 | { |
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282 | boardData->quiccInt = NULL; |
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283 | *(unsigned long *)(boardData->baseaddr + PMCQ1_INT_MASK) |= PMCQ1_INT_MASK_QUICC; |
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284 | status = RTEMS_SUCCESSFUL; |
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285 | break; |
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286 | } |
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287 | } |
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288 | |
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289 | return (status); |
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290 | } |
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291 | |
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292 | |
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293 | /******************************************************************************* |
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294 | * |
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295 | * rsPMCQ1Init - initialize the PMCQ1's |
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296 | * |
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297 | * This routine is called to initialize the PCI card to a quiescent state. |
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298 | * |
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299 | * RETURNS: OK if PMCQ1 found, ERROR if not. |
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300 | */ |
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301 | |
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302 | unsigned int rsPMCQ1Init() |
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303 | { |
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304 | int busNo; |
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305 | int slotNo; |
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306 | unsigned int baseaddr = 0; |
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307 | unsigned int bridgeaddr = 0; |
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308 | unsigned long pbti0_ctl; |
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309 | int i; |
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310 | unsigned char int_vector; |
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311 | int fun; |
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312 | unsigned int temp; |
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313 | PPMCQ1BoardData boardData; |
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314 | rtems_irq_connect_data IrqData = {0, |
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315 | rsPMCQ1Int, |
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316 | NULL, |
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317 | (rtems_irq_enable)rsPMCQ1_scc_nullFunc, |
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318 | (rtems_irq_disable)rsPMCQ1_scc_nullFunc, |
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319 | (rtems_irq_is_enabled)rsPMCQ1_scc_nullFunc, |
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320 | NULL}; |
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321 | |
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322 | if (rsPMCQ1Initialized) |
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323 | { |
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324 | return RTEMS_SUCCESSFUL; |
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325 | } |
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326 | for (i=0;;i++){ |
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327 | if ( pci_find_device(PCI_VEN_ID_RADSTONE, PCI_DEV_ID_PMCQ1, i, &busNo, &slotNo, &fun) != 0 ) |
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328 | break; |
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329 | |
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330 | pci_read_config_dword(busNo, slotNo, 0, PCI_BASE_ADDRESS_2, &baseaddr); |
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331 | pci_read_config_dword(busNo, slotNo, 0, PCI_BASE_ADDRESS_0, &bridgeaddr); |
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332 | #ifdef DEBUG_360 |
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333 | printk("PMCQ1 baseaddr 0x%08x bridgeaddr 0x%08x\n", baseaddr, bridgeaddr ); |
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334 | #endif |
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335 | |
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336 | /* Set function code to normal mode and enable window */ |
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337 | pbti0_ctl = *(unsigned long *)(bridgeaddr + 0x100) & 0xff0fffff; |
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338 | eieio(); |
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339 | *(unsigned long *)(bridgeaddr + 0x100) = pbti0_ctl | 0x00500080; |
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340 | eieio(); |
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341 | |
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342 | /* Assert QBUS reset */ |
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343 | *(unsigned long *)(bridgeaddr + 0x800) |= 0x00000080; |
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344 | eieio(); |
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345 | |
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346 | /* |
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347 | * Hold QBus in reset for 1ms |
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348 | */ |
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349 | MsDelay(); |
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350 | |
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351 | /* Take QBUS out of reset */ |
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352 | *(unsigned long *)(bridgeaddr + 0x800) &= ~0x00000080; |
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353 | eieio(); |
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354 | |
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355 | MsDelay(); |
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356 | |
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357 | /* If a QUICC is fitted initialise it */ |
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358 | if (PMCQ1_Read_EPLD(baseaddr, PMCQ1_BUILD_OPTION) & PMCQ1_QUICC_FITTED) |
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359 | { |
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360 | #ifdef DEBUG_360 |
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361 | printk(" Found QUICC busNo %d slotNo %d\n", busNo, slotNo); |
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362 | #endif |
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363 | |
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364 | /* Initialise MBAR (must use function code of 7) */ |
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365 | *(unsigned long *)(bridgeaddr + 0x100) = pbti0_ctl | 0x00700080; |
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366 | eieio(); |
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367 | |
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368 | /* place internal 8K SRAM and registers at address 0x0 */ |
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369 | *(unsigned long *)(baseaddr + Q1_360_MBAR) = 0x1; |
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370 | eieio(); |
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371 | |
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372 | /* Set function code to normal mode */ |
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373 | *(unsigned long *)(bridgeaddr + 0x100) = pbti0_ctl | 0x00500080; |
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374 | eieio(); |
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375 | |
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376 | /* Disable the SWT and perform basic initialisation */ |
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377 | write8(baseaddr+Q1_360_SIM_SYPCR,0); |
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378 | eieio(); |
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379 | |
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380 | write32(baseaddr+Q1_360_SIM_MCR,0xa0001029); |
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381 | write16(baseaddr+Q1_360_SIM_PICR,0); |
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382 | write16(baseaddr+Q1_360_SIM_PITR,0); |
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383 | |
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384 | write16(baseaddr+Q1_360_CPM_ICCR,0x770); |
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385 | write16(baseaddr+Q1_360_CPM_SDCR,0x770); |
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386 | write32(baseaddr+Q1_360_CPM_CICR,0x00e49f00); |
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387 | write16(baseaddr+Q1_360_SIM_PEPAR,0x2080); |
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388 | eieio(); |
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389 | |
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390 | /* Enable SRAM */ |
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391 | write32(baseaddr+Q1_360_SIM_GMR,0x00001000); /* external master wait state */ |
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392 | eieio(); |
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393 | write32(baseaddr+Q1_360_SIM_OR0,0x1ff00000); /*| MEMC_OR_FC*/ |
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394 | eieio(); |
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395 | write32(baseaddr+Q1_360_SIM_BR0,0); |
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396 | eieio(); |
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397 | write32(baseaddr+Q1_360_SIM_OR1,(0x5ff00000 | 0x00000780)); /*| MEMC_OR_FC*/ |
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398 | eieio(); |
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399 | write32(baseaddr+Q1_360_SIM_BR1,(0x00000040 | 0x00000001 | 0x00200280) ); |
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400 | eieio(); |
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401 | } |
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402 | |
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403 | /* |
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404 | * If a second PCI window is present then make it opposite |
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405 | * endian to simplify 1553 integration. |
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406 | */ |
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407 | pci_read_config_dword(busNo, slotNo, 0, PCI_BASE_ADDRESS_3, &temp); |
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408 | if (temp) { |
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409 | *(unsigned long *)(bridgeaddr + 0x110) |= 0x00500880; |
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410 | } |
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411 | |
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412 | /* |
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413 | * Create descriptor structure for this card |
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414 | */ |
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415 | if ((boardData = malloc(sizeof(struct _PMCQ1BoardData))) == NULL) |
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416 | { |
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417 | printk("Error Unable to allocate memory for _PMCQ1BoardData\n"); |
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418 | return(RTEMS_IO_ERROR); |
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419 | } |
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420 | |
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421 | boardData->pNext = pmcq1BoardData; |
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422 | boardData->busNo = busNo; |
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423 | boardData->slotNo = slotNo; |
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424 | boardData->funcNo = 0; |
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425 | boardData->baseaddr = baseaddr; |
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426 | boardData->bridgeaddr = bridgeaddr; |
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427 | boardData->quiccInt = NULL; |
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428 | boardData->maInt = NULL; |
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429 | pmcq1BoardData = boardData; |
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430 | mc68360_scc_create_chip( boardData, int_vector ); |
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431 | |
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432 | /* |
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433 | * Connect PMCQ1 interrupt handler. |
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434 | */ |
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435 | pci_read_config_byte(busNo, slotNo, 0, 0x3c, &int_vector); |
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436 | #ifdef DEBUG_360 |
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437 | printk("PMCQ1 int_vector %d\n", int_vector); |
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438 | #endif |
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439 | IrqData.name = (rtems_irq_number)((unsigned int)BSP_PCI_IRQ0 + int_vector); |
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440 | IrqData.handle = boardData; |
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441 | if (!BSP_install_rtems_shared_irq_handler (&IrqData)) { |
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442 | printk("Error installing interrupt handler!\n"); |
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443 | rtems_fatal_error_occurred(1); |
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444 | } |
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445 | |
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446 | /* |
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447 | * Enable PMCQ1 Interrupts from QSPAN-II |
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448 | */ |
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449 | |
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450 | *(unsigned long *)(bridgeaddr + 0x600) = 0x00001000; |
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451 | eieio(); |
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452 | *(unsigned long *)(bridgeaddr + 0x604) |= 0x00001000; |
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453 | |
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454 | eieio(); |
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455 | } |
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456 | |
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457 | if (i > 0) |
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458 | { |
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459 | rsPMCQ1Initialized = TRUE; |
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460 | } |
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461 | return((i > 0) ? RTEMS_SUCCESSFUL : RTEMS_IO_ERROR); |
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462 | } |
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463 | |
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464 | /******************************************************************************* |
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465 | * |
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466 | * rsPMCQ1Commission - initialize the serial EEPROM on the QSPAN |
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467 | * |
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468 | * This routine is called to initialize the EEPROM attached to the QSPAN |
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469 | * on the PMCQ1 module. It will load standard settings into any QSPAN's |
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470 | * found with apparently uninitialised EEPROM's or PMCQ1's (to allow |
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471 | * EEPROM modifications to be performed). |
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472 | */ |
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473 | |
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474 | unsigned int rsPMCQ1Commission( unsigned long busNo, unsigned long slotNo ) |
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475 | { |
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476 | unsigned int status = RTEMS_IO_ERROR; |
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477 | unsigned int bridgeaddr = 0; |
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478 | unsigned long val; |
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479 | int i; |
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480 | unsigned int venId1; |
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481 | unsigned int venId2; |
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482 | |
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483 | pci_read_config_dword(busNo, slotNo, 0, PCI_VENDOR_ID, &venId1); |
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484 | pci_read_config_dword(busNo, slotNo, 0, PCI_VENDOR_ID, &venId2); |
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485 | if ((venId1 == 0x086210e3) || |
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486 | (venId2 == PCI_ID(PCI_VEN_ID_RADSTONE, PCI_DEV_ID_PMCQ1))) |
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487 | { |
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488 | pci_read_config_dword(busNo, slotNo, 0, PCI_BASE_ADDRESS_0, &bridgeaddr); |
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489 | status = RTEMS_SUCCESSFUL; |
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490 | |
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491 | /* |
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492 | * The On board PMCQ1 on an EP1A has a subVendor ID of 0. |
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493 | * A real PMCQ1 also has the sub vendor ID set up. |
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494 | */ |
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495 | if ((busNo == 0) && (slotNo == 1)) { |
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496 | *(unsigned long *)rsPMCQ1eeprom = 0; |
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497 | } else { |
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498 | *(unsigned long *)rsPMCQ1eeprom = PCI_ID(PCI_VEN_ID_RADSTONE, PCI_DEV_ID_PMCQ1); |
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499 | } |
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500 | |
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501 | for (i = 0; i < 23; i++) { |
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502 | /* Wait until interface not active */ |
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503 | while(read32(bridgeaddr + 0x804) & 0x80000000) { |
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504 | rtems_bsp_delay(1); |
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505 | } |
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506 | |
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507 | /* Write value */ |
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508 | write32(bridgeaddr + 0x804, (rsPMCQ1eeprom[i] << 8) | i); |
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509 | |
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510 | /* delay for > 31 usec to allow active bit to become set */ |
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511 | rtems_bsp_delay(100); |
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512 | |
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513 | /* Wait until interface not active */ |
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514 | while(read32(bridgeaddr + 0x804) & 0x80000000) { |
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515 | rtems_bsp_delay(1); |
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516 | } |
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517 | |
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518 | /* Re-read value */ |
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519 | write32(bridgeaddr + 0x804, 0x40000000 | i); |
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520 | |
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521 | /* delay for > 31 usec to allow active bit to become set */ |
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522 | rtems_bsp_delay(100); |
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523 | |
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524 | /* Wait until interface not active */ |
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525 | while((val = read32(bridgeaddr + 0x804)) & 0x80000000) { |
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526 | rtems_bsp_delay(1); |
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527 | } |
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528 | |
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529 | if (((val >> 8) & 0xff) != rsPMCQ1eeprom[i]) { |
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530 | printk("Error writing byte %d expected 0x%02x got 0x%02x\n", |
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531 | i, rsPMCQ1eeprom[i], (unsigned char)(val >> 8)); |
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532 | status = RTEMS_IO_ERROR; |
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533 | break; |
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534 | } |
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535 | } |
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536 | } |
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537 | return(status); |
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538 | } |
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539 | |
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540 | uint32_t PMCQ1_Read_EPLD( uint32_t base, uint32_t reg ) |
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541 | { |
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542 | uint32_t data; |
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543 | |
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544 | data = ( *((unsigned long *) (base + reg)) ); |
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545 | #ifdef DEBUG_360 |
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546 | printk("EPLD Read 0x%x: 0x%08x\n", reg + base, data ); |
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547 | #endif |
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548 | return data; |
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549 | } |
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550 | |
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551 | void PMCQ1_Write_EPLD( uint32_t base, uint32_t reg, uint32_t data ) |
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552 | { |
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553 | *((unsigned long *) (base + reg)) = data; |
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554 | #ifdef DEBUG_360 |
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555 | printk("EPLD Write 0x%x: 0x%08x\n", reg+base, data ); |
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556 | #endif |
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557 | } |
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558 | |
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