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m68360.h @ e160e41

4.115

Last change on this file since e160e41 was e160e41, checked in by Joel Sherrill <joel.sherrill@…>, on 10/09/14 at 20:15:55

powerpc/ep1a: Remove if 0 sections

There may be useful nuggets for debug and alternate configurations
in this code. There may be methods directly called by the application
which are beyond normal APIs. We have no way of knowing this based
on the comments in these files. There were no public prototypes
so the routines and code in question should have be unused private
methods.

These will always be in the source code control system as a deletion.
If some of the code is needed, justify it and provide a patch to restore
it along with a prototype in a public place if needed and a better name.

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File size: 33.0 KB

Line
1	/*
2	* MOTOROLA MC68360 QUAD INTEGRATED COMMUNICATIONS CONTROLLER (QUICC)
3	*
4	* HARDWARE DECLARATIONS
5	*
6	*
7	* Submitted By:
8	*
9	* W. Eric Norum
10	* Saskatchewan Accelerator Laboratory
11	* University of Saskatchewan
12	* 107 North Road
13	* Saskatoon, Saskatchewan, CANADA
14	* S7N 5C6
15	*
16	* eric@skatter.usask.ca
17	*
18	*
19	* COPYRIGHT (c) 1989-1999.
20	* On-Line Applications Research Corporation (OAR).
21	*
22	* The license and distribution terms for this file may be
23	* found in the file LICENSE in this distribution or at
24	* http://www.rtems.org/license/LICENSE.
25	*/
26
27	#ifndef __MC68360_h
28	#define __MC68360_h
29
30	#include "rsPMCQ1.h"
31
32	/*
33	*************************************************************************
34	* REGISTER SUBBLOCKS *
35	*************************************************************************
36	*/
37
38	/*
39	* Memory controller registers
40	*/
41	typedef struct m360MEMCRegisters_ {
42	uint32_t br;
43	uint32_t or;
44	uint32_t _pad[2];
45	} m360MEMCRegisters_t;
46
47
48	#define M360_GSMR_RFW 0x00000020
49
50	#define M360_GSMR_RINV 0x02000000
51	#define M360_GSMR_TINV 0x01000000
52	#define M360_GSMR_TDCR_16X 0x00020000
53	#define M360_GSMR_RDCR_16X 0x00008000
54	#define M360_GSMR_DIAG_LLOOP 0x00000040
55	#define M360_GSMR_ENR 0x00000020
56	#define M360_GSMR_ENT 0x00000010
57	#define M360_GSMR_MODE_UART 0x00000004
58
59	#define M360_PSMR_FLC 0x8000
60	#define M360_PSMR_SL_1 0x0000
61	#define M360_PSMR_SL_2 0x4000
62	#define M360_PSMR_CL5 0x0000
63	#define M360_PSMR_CL6 0x1000
64	#define M360_PSMR_CL7 0x2000
65	#define M360_PSMR_CL8 0x3000
66	#define M360_PSMR_UM_NORMAL 0x0000
67	#define M360_PSMR_FRZ 0x0200
68	#define M360_PSMR_RZS 0x0100
69	#define M360_PSMR_SYN 0x0080
70	#define M360_PSMR_DRT 0x0040
71	#define M360_PSMR_PEN 0x0010
72	#define M360_PSMR_RPM_ODD 0x0000
73	#define M360_PSMR_RPM_LOW 0x0004
74	#define M360_PSMR_RPM_EVEN 0x0008
75	#define M360_PSMR_RPM_HI 0x000c
76	#define M360_PSMR_TPM_ODD 0x0000
77	#define M360_PSMR_TPM_LOW 0x0001
78	#define M360_PSMR_TPM_EVEN 0x0002
79	#define M360_PSMR_TPM_HI 0x0003
80
81	/*
82	* Serial Communications Controller registers
83	*/
84	typedef struct m360SCCRegisters_ {
85	uint32_t gsmr_l;
86	uint32_t gsmr_h;
87	uint16_t psmr;
88	uint16_t _pad0;
89	uint16_t todr;
90	uint16_t dsr;
91	uint16_t scce;
92	uint16_t _pad1;
93	uint16_t sccm;
94	uint8_t _pad2;
95	uint8_t sccs;
96	uint32_t _pad3[2];
97	} m360SCCRegisters_t;
98
99	/*
100	* Serial Management Controller registers
101	*/
102	typedef struct m360SMCRegisters_ {
103	uint16_t _pad0;
104	uint16_t smcmr;
105	uint16_t _pad1;
106	uint8_t smce;
107	uint8_t _pad2;
108	uint16_t _pad3;
109	uint8_t smcm;
110	uint8_t _pad4;
111	uint32_t _pad5;
112	} m360SMCRegisters_t;
113
114
115	/*
116	*************************************************************************
117	* Miscellaneous Parameters *
118	*************************************************************************
119	*/
120	typedef struct m360MiscParms_ {
121	uint16_t rev_num;
122	uint16_t _res1;
123	uint32_t _res2;
124	uint32_t _res3;
125	} m360MiscParms_t;
126
127	/*
128	*************************************************************************
129	* RISC Timers *
130	*************************************************************************
131	*/
132	typedef struct m360TimerParms_ {
133	uint16_t tm_base;
134	uint16_t _tm_ptr;
135	uint16_t _r_tmr;
136	uint16_t _r_tmv;
137	uint32_t tm_cmd;
138	uint32_t tm_cnt;
139	} m360TimerParms_t;
140
141	/*
142	* RISC Controller Configuration Register (RCCR)
143	* All other bits in this register are either reserved or
144	* used only with a Motorola-supplied RAM microcode packge.
145	*/
146	#define M360_RCCR_TIME (1<<15) /* Enable timer */
147	#define M360_RCCR_TIMEP(x) ((x)<<8) /* Timer period */
148
149	/*
150	* Command register
151	* Set up this register before issuing a M360_CR_OP_SET_TIMER command.
152	*/
153	#define M360_TM_CMD_V (1<<31) /* Set to enable timer */
154	#define M360_TM_CMD_R (1<<30) /* Set for automatic restart */
155	#define M360_TM_CMD_TIMER(x) ((x)<<16) /* Select timer */
156	#define M360_TM_CMD_PERIOD(x) (x) /* Timer period (16 bits) */
157
158	/*
159	*************************************************************************
160	* DMA Controllers *
161	*************************************************************************
162	*/
163	typedef struct m360IDMAparms_ {
164	uint16_t ibase;
165	uint16_t ibptr;
166	uint32_t _istate;
167	uint32_t _itemp;
168	} m360IDMAparms_t;
169
170	/*
171	*************************************************************************
172	* Serial Communication Controllers *
173	*************************************************************************
174	*/
175	typedef struct m360SCCparms_ {
176	uint16_t rbase;
177	uint16_t tbase;
178	uint8_t rfcr;
179	uint8_t tfcr;
180	uint16_t mrblr;
181	uint32_t _rstate;
182	uint32_t _pad0;
183	uint16_t _rbptr;
184	uint16_t _pad1;
185	uint32_t _pad2;
186	uint32_t _tstate;
187	uint32_t _pad3;
188	uint16_t _tbptr;
189	uint16_t _pad4;
190	uint32_t _pad5;
191	uint32_t _rcrc;
192	uint32_t _tcrc;
193	union {
194	struct {
195	uint32_t _res0;
196	uint32_t _res1;
197	uint16_t max_idl;
198	uint16_t _idlc;
199	uint16_t brkcr;
200	uint16_t parec;
201	uint16_t frmec;
202	uint16_t nosec;
203	uint16_t brkec;
204	uint16_t brklen;
205	uint16_t uaddr[2];
206	uint16_t _rtemp;
207	uint16_t toseq;
208	uint16_t character[8];
209	uint16_t rccm;
210	uint16_t rccr;
211	uint16_t rlbc;
212	} uart;
213	struct {
214	uint32_t crc_p;
215	uint32_t crc_c;
216	} transparent;
217
218	} un;
219	} m360SCCparms_t;
220
221	typedef struct m360SCCENparms_ {
222	uint16_t rbase;
223	uint16_t tbase;
224	uint8_t rfcr;
225	uint8_t tfcr;
226	uint16_t mrblr;
227	uint32_t _rstate;
228	uint32_t _pad0;
229	uint16_t _rbptr;
230	uint16_t _pad1;
231	uint32_t _pad2;
232	uint32_t _tstate;
233	uint32_t _pad3;
234	uint16_t _tbptr;
235	uint16_t _pad4;
236	uint32_t _pad5;
237	uint32_t _rcrc;
238	uint32_t _tcrc;
239	union {
240	struct {
241	uint32_t _res0;
242	uint32_t _res1;
243	uint16_t max_idl;
244	uint16_t _idlc;
245	uint16_t brkcr;
246	uint16_t parec;
247	uint16_t frmec;
248	uint16_t nosec;
249	uint16_t brkec;
250	uint16_t brklen;
251	uint16_t uaddr[2];
252	uint16_t _rtemp;
253	uint16_t toseq;
254	uint16_t character[8];
255	uint16_t rccm;
256	uint16_t rccr;
257	uint16_t rlbc;
258	} uart;
259	struct {
260	uint32_t c_pres;
261	uint32_t c_mask;
262	uint32_t crcec;
263	uint32_t alec;
264	uint32_t disfc;
265	uint16_t pads;
266	uint16_t ret_lim;
267	uint16_t _ret_cnt;
268	uint16_t mflr;
269	uint16_t minflr;
270	uint16_t maxd1;
271	uint16_t maxd2;
272	uint16_t _maxd;
273	uint16_t dma_cnt;
274	uint16_t _max_b;
275	uint16_t gaddr1;
276	uint16_t gaddr2;
277	uint16_t gaddr3;
278	uint16_t gaddr4;
279	uint32_t _tbuf0data0;
280	uint32_t _tbuf0data1;
281	uint32_t _tbuf0rba0;
282	uint32_t _tbuf0crc;
283	uint16_t _tbuf0bcnt;
284	uint16_t paddr_h;
285	uint16_t paddr_m;
286	uint16_t paddr_l;
287	uint16_t p_per;
288	uint16_t _rfbd_ptr;
289	uint16_t _tfbd_ptr;
290	uint16_t _tlbd_ptr;
291	uint32_t _tbuf1data0;
292	uint32_t _tbuf1data1;
293	uint32_t _tbuf1rba0;
294	uint32_t _tbuf1crc;
295	uint16_t _tbuf1bcnt;
296	uint16_t _tx_len;
297	uint16_t iaddr1;
298	uint16_t iaddr2;
299	uint16_t iaddr3;
300	uint16_t iaddr4;
301	uint16_t _boff_cnt;
302	uint16_t taddr_h;
303	uint16_t taddr_m;
304	uint16_t taddr_l;
305	} ethernet;
306	struct {
307	uint32_t crc_p;
308	uint32_t crc_c;
309	} transparent;
310	} un;
311	} m360SCCENparms_t;
312
313	/*
314	* Receive and transmit function code register bits
315	* These apply to the function code registers of all devices, not just SCC.
316	*/
317	#define M360_RFCR_MOT (1<<4)
318	#define M360_RFCR_DMA_SPACE 0x8
319	#define M360_TFCR_MOT (1<<4)
320	#define M360_TFCR_DMA_SPACE 0x8
321
322	/*
323	*************************************************************************
324	* Serial Management Controllers *
325	*************************************************************************
326	*/
327	typedef struct m360SMCparms_ {
328	uint16_t rbase;
329	uint16_t tbase;
330	uint8_t rfcr;
331	uint8_t tfcr;
332	uint16_t mrblr;
333	uint32_t _rstate;
334	uint32_t _pad0;
335	uint16_t _rbptr;
336	uint16_t _pad1;
337	uint32_t _pad2;
338	uint32_t _tstate;
339	uint32_t _pad3;
340	uint16_t _tbptr;
341	uint16_t _pad4;
342	uint32_t _pad5;
343	union {
344	struct {
345	uint16_t max_idl;
346	uint16_t _pad0;
347	uint16_t brklen;
348	uint16_t brkec;
349	uint16_t brkcr;
350	uint16_t _r_mask;
351	} uart;
352	struct {
353	uint16_t _pad0[5];
354	} transparent;
355	} un;
356	} m360SMCparms_t;
357
358	/*
359	* Mode register
360	*/
361	#define M360_SMCMR_CLEN(x) ((x)<<11) /* Character length */
362	#define M360_SMCMR_2STOP (1<<10) /* 2 stop bits */
363	#define M360_SMCMR_PARITY (1<<9) /* Enable parity */
364	#define M360_SMCMR_EVEN (1<<8) /* Even parity */
365	#define M360_SMCMR_SM_GCI (0<<4) /* GCI Mode */
366	#define M360_SMCMR_SM_UART (2<<4) /* UART Mode */
367	#define M360_SMCMR_SM_TRANSPARENT (3<<4) /* Transparent Mode */
368	#define M360_SMCMR_DM_LOOPBACK (1<<2) /* Local loopback mode */
369	#define M360_SMCMR_DM_ECHO (2<<2) /* Echo mode */
370	#define M360_SMCMR_TEN (1<<1) /* Enable transmitter */
371	#define M360_SMCMR_REN (1<<0) /* Enable receiver */
372
373	/*
374	* Event and mask registers (SMCE, SMCM)
375	*/
376	#define M360_SMCE_BRK (1<<4)
377	#define M360_SMCE_BSY (1<<2)
378	#define M360_SMCE_TX (1<<1)
379	#define M360_SMCE_RX (1<<0)
380
381	/*
382	*************************************************************************
383	* Serial Peripheral Interface *
384	*************************************************************************
385	*/
386	typedef struct m360SPIparms_ {
387	uint16_t rbase;
388	uint16_t tbase;
389	uint8_t rfcr;
390	uint8_t tfcr;
391	uint16_t mrblr;
392	uint32_t _rstate;
393	uint32_t _pad0;
394	uint16_t _rbptr;
395	uint16_t _pad1;
396	uint32_t _pad2;
397	uint32_t _tstate;
398	uint32_t _pad3;
399	uint16_t _tbptr;
400	uint16_t _pad4;
401	uint32_t _pad5;
402	} m360SPIparms_t;
403
404	/*
405	* Mode register (SPMODE)
406	*/
407	#define M360_SPMODE_LOOP (1<<14) /* Local loopback mode */
408	#define M360_SPMODE_CI (1<<13) /* Clock invert */
409	#define M360_SPMODE_CP (1<<12) /* Clock phase */
410	#define M360_SPMODE_DIV16 (1<<11) /* Divide BRGCLK by 16 */
411	#define M360_SPMODE_REV (1<<10) /* Reverse data */
412	#define M360_SPMODE_MASTER (1<<9) /* SPI is master */
413	#define M360_SPMODE_EN (1<<8) /* Enable SPI */
414	#define M360_SPMODE_CLEN(x) ((x)<<4) /* Character length */
415	#define M360_SPMODE_PM(x) (x) /* Prescaler modulus */
416
417	/*
418	* Mode register (SPCOM)
419	*/
420	#define M360_SPCOM_STR (1<<7) /* Start transmit */
421
422	/*
423	* Event and mask registers (SPIE, SPIM)
424	*/
425	#define M360_SPIE_MME (1<<5) /* Multi-master error */
426	#define M360_SPIE_TXE (1<<4) /* Tx error */
427	#define M360_SPIE_BSY (1<<2) /* Busy condition*/
428	#define M360_SPIE_TXB (1<<1) /* Tx buffer */
429	#define M360_SPIE_RXB (1<<0) /* Rx buffer */
430
431	/*
432	*************************************************************************
433	* SDMA (SCC, SMC, SPI) Buffer Descriptors *
434	*************************************************************************
435	*/
436	typedef struct m360BufferDescriptor_ {
437	uint16_t status;
438	uint16_t length;
439	uint32_t buffer; /* this is a void * to the 360 */
440	} m360BufferDescriptor_t;
441
442	/*
443	* Bits in receive buffer descriptor status word
444	*/
445	#define M360_BD_EMPTY (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */
446	#define M360_BD_WRAP (1<<13) /* Ethernet, SCC UART, SMC UART, SPI */
447	#define M360_BD_INTERRUPT (1<<12) /* Ethernet, SCC UART, SMC UART, SPI */
448	#define M360_BD_LAST (1<<11) /* Ethernet, SPI */
449	#define M360_BD_CONTROL_CHAR (1<<11) /* SCC UART */
450	#define M360_BD_FIRST_IN_FRAME (1<<10) /* Ethernet */
451	#define M360_BD_ADDRESS (1<<10) /* SCC UART */
452	#define M360_BD_CONTINUOUS (1<<9) /* SCC UART, SMC UART, SPI */
453	#define M360_BD_MISS (1<<8) /* Ethernet */
454	#define M360_BD_IDLE (1<<8) /* SCC UART, SMC UART */
455	#define M360_BD_ADDRSS_MATCH (1<<7) /* SCC UART */
456	#define M360_BD_LONG (1<<5) /* Ethernet */
457	#define M360_BD_BREAK (1<<5) /* SCC UART, SMC UART */
458	#define M360_BD_NONALIGNED (1<<4) /* Ethernet */
459	#define M360_BD_FRAMING_ERROR (1<<4) /* SCC UART, SMC UART */
460	#define M360_BD_SHORT (1<<3) /* Ethernet */
461	#define M360_BD_PARITY_ERROR (1<<3) /* SCC UART, SMC UART */
462	#define M360_BD_CRC_ERROR (1<<2) /* Ethernet */
463	#define M360_BD_OVERRUN (1<<1) /* Ethernet, SCC UART, SMC UART, SPI */
464	#define M360_BD_COLLISION (1<<0) /* Ethernet */
465	#define M360_BD_CARRIER_LOST (1<<0) /* SCC UART */
466	#define M360_BD_MASTER_ERROR (1<<0) /* SPI */
467
468	/*
469	* Bits in transmit buffer descriptor status word
470	* Many bits have the same meaning as those in receiver buffer descriptors.
471	*/
472	#define M360_BD_READY (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */
473	#define M360_BD_PAD (1<<14) /* Ethernet */
474	#define M360_BD_CTS_REPORT (1<<11) /* SCC UART */
475	#define M360_BD_TX_CRC (1<<10) /* Ethernet */
476	#define M360_BD_DEFER (1<<9) /* Ethernet */
477	#define M360_BD_HEARTBEAT (1<<8) /* Ethernet */
478	#define M360_BD_PREAMBLE (1<<8) /* SCC UART, SMC UART */
479	#define M360_BD_LATE_COLLISION (1<<7) /* Ethernet */
480	#define M360_BD_NO_STOP_BIT (1<<7) /* SCC UART */
481	#define M360_BD_RETRY_LIMIT (1<<6) /* Ethernet */
482	#define M360_BD_RETRY_COUNT(x) (((x)&0x3C)>>2) /* Ethernet */
483	#define M360_BD_UNDERRUN (1<<1) /* Ethernet, SPI */
484	#define M360_BD_CARRIER_LOST (1<<0) /* Ethernet */
485	#define M360_BD_CTS_LOST (1<<0) /* SCC UART */
486
487	/*
488	*************************************************************************
489	* IDMA Buffer Descriptors *
490	*************************************************************************
491	*/
492	typedef struct m360IDMABufferDescriptor_ {
493	uint16_t status;
494	uint16_t _pad;
495	uint32_t length;
496	void *source;
497	void *destination;
498	} m360IDMABufferDescriptor_t;
499
500	/*
501	*************************************************************************
502	* RISC Communication Processor Module Command Register (CR) *
503	*************************************************************************
504	*/
505	#define M360_CR_RST (1<<15) /* Reset communication processor */
506	#define M360_CR_OP_INIT_RX_TX (0<<8) /* SCC, SMC UART, SMC GCI, SPI */
507	#define M360_CR_OP_INIT_RX (1<<8) /* SCC, SMC UART, SPI */
508	#define M360_CR_OP_INIT_TX (2<<8) /* SCC, SMC UART, SPI */
509	#define M360_CR_OP_INIT_HUNT (3<<8) /* SCC, SMC UART */
510	#define M360_CR_OP_STOP_TX (4<<8) /* SCC, SMC UART */
511	#define M360_CR_OP_GR_STOP_TX (5<<8) /* SCC */
512	#define M360_CR_OP_INIT_IDMA (5<<8) /* IDMA */
513	#define M360_CR_OP_RESTART_TX (6<<8) /* SCC, SMC UART */
514	#define M360_CR_OP_CLOSE_RX_BD (7<<8) /* SCC, SMC UART, SPI */
515	#define M360_CR_OP_SET_GRP_ADDR (8<<8) /* SCC */
516	#define M360_CR_OP_SET_TIMER (8<<8) /* Timer */
517	#define M360_CR_OP_GCI_TIMEOUT (9<<8) /* SMC GCI */
518	#define M360_CR_OP_RESERT_BCS (10<<8) /* SCC */
519	#define M360_CR_OP_GCI_ABORT (10<<8) /* SMC GCI */
520	#define M360_CR_CHAN_SCC1 (0<<4) /* Channel selection */
521	#define M360_CR_CHAN_SCC2 (4<<4)
522	#define M360_CR_CHAN_SPI (5<<4)
523	#define M360_CR_CHAN_TIMER (5<<4)
524	#define M360_CR_CHAN_SCC3 (8<<4)
525	#define M360_CR_CHAN_SMC1 (9<<4)
526	#define M360_CR_CHAN_IDMA1 (9<<4)
527	#define M360_CR_CHAN_SCC4 (12<<4)
528	#define M360_CR_CHAN_SMC2 (13<<4)
529	#define M360_CR_CHAN_IDMA2 (13<<4)
530	#define M360_CR_FLG (1<<0) /* Command flag */
531
532	/*
533	*************************************************************************
534	* System Protection Control Register (SYPCR) *
535	*************************************************************************
536	*/
537	#define M360_SYPCR_SWE (1<<7) /* Software watchdog enable */
538	#define M360_SYPCR_SWRI (1<<6) /* Software watchdog reset select */
539	#define M360_SYPCR_SWT1 (1<<5) /* Software watchdog timing bit 1 */
540	#define M360_SYPCR_SWT0 (1<<4) /* Software watchdog timing bit 0 */
541	#define M360_SYPCR_DBFE (1<<3) /* Double bus fault monitor enable */
542	#define M360_SYPCR_BME (1<<2) /* Bus monitor external enable */
543	#define M360_SYPCR_BMT1 (1<<1) /* Bus monitor timing bit 1 */
544	#define M360_SYPCR_BMT0 (1<<0) /* Bus monitor timing bit 0 */
545
546	/*
547	*************************************************************************
548	* Memory Control Registers *
549	*************************************************************************
550	*/
551	#define M360_GMR_RCNT(x) ((x)<<24) /* Refresh count */
552	#define M360_GMR_RFEN (1<<23) /* Refresh enable */
553	#define M360_GMR_RCYC(x) ((x)<<21) /* Refresh cycle length */
554	#define M360_GMR_PGS(x) ((x)<<18) /* Page size */
555	#define M360_GMR_DPS_32BIT (0<<16) /* DRAM port size */
556	#define M360_GMR_DPS_16BIT (1<<16)
557	#define M360_GMR_DPS_8BIT (2<<16)
558	#define M360_GMR_DPS_DSACK (3<<16)
559	#define M360_GMR_WBT40 (1<<15) /* Wait between 040 transfers */
560	#define M360_GMR_WBTQ (1<<14) /* Wait between 360 transfers */
561	#define M360_GMR_SYNC (1<<13) /* Synchronous external access */
562	#define M360_GMR_EMWS (1<<12) /* External master wait state */
563	#define M360_GMR_OPAR (1<<11) /* Odd parity */
564	#define M360_GMR_PBEE (1<<10) /* Parity bus error enable */
565	#define M360_GMR_TSS40 (1<<9) /* TS* sample for 040 */
566	#define M360_GMR_NCS (1<<8) /* No CPU space */
567	#define M360_GMR_DWQ (1<<7) /* Delay write for 360 */
568	#define M360_GMR_DW40 (1<<6) /* Delay write for 040 */
569	#define M360_GMR_GAMX (1<<5) /* Global address mux enable */
570
571	#define M360_MEMC_BR_FC(x) ((x)<<7) /* Function code limit */
572	#define M360_MEMC_BR_TRLXQ (1<<6) /* Relax timing requirements */
573	#define M360_MEMC_BR_BACK40 (1<<5) /* Burst acknowledge to 040 */
574	#define M360_MEMC_BR_CSNT40 (1<<4) /* CS* negate timing for 040 */
575	#define M360_MEMC_BR_CSNTQ (1<<3) /* CS* negate timing for 360 */
576	#define M360_MEMC_BR_PAREN (1<<2) /* Enable parity checking */
577	#define M360_MEMC_BR_WP (1<<1) /* Write Protect */
578	#define M360_MEMC_BR_V (1<<0) /* Base/Option register are valid */
579
580	#define M360_MEMC_OR_TCYC(x) ((x)<<28) /* Cycle length (clocks) */
581	#define M360_MEMC_OR_WAITS(x) M360_MEMC_OR_TCYC((x)+1)
582	#define M360_MEMC_OR_2KB 0x0FFFF800 /* Address range */
583	#define M360_MEMC_OR_4KB 0x0FFFF000
584	#define M360_MEMC_OR_8KB 0x0FFFE000
585	#define M360_MEMC_OR_16KB 0x0FFFC000
586	#define M360_MEMC_OR_32KB 0x0FFF8000
587	#define M360_MEMC_OR_64KB 0x0FFF0000
588	#define M360_MEMC_OR_128KB 0x0FFE0000
589	#define M360_MEMC_OR_256KB 0x0FFC0000
590	#define M360_MEMC_OR_512KB 0x0FF80000
591	#define M360_MEMC_OR_1MB 0x0FF00000
592	#define M360_MEMC_OR_2MB 0x0FE00000
593	#define M360_MEMC_OR_4MB 0x0FC00000
594	#define M360_MEMC_OR_8MB 0x0F800000
595	#define M360_MEMC_OR_16MB 0x0F000000
596	#define M360_MEMC_OR_32MB 0x0E000000
597	#define M360_MEMC_OR_64MB 0x0C000000
598	#define M360_MEMC_OR_128MB 0x08000000
599	#define M360_MEMC_OR_256MB 0x00000000
600	#define M360_MEMC_OR_FCMC(x) ((x)<<7) /* Function code mask */
601	#define M360_MEMC_OR_BCYC(x) ((x)<<5) /* Burst cycle length (clocks) */
602	#define M360_MEMC_OR_PGME (1<<3) /* Page mode enable */
603	#define M360_MEMC_OR_32BIT (0<<1) /* Port size */
604	#define M360_MEMC_OR_16BIT (1<<1)
605	#define M360_MEMC_OR_8BIT (2<<1)
606	#define M360_MEMC_OR_DSACK (3<<1)
607	#define M360_MEMC_OR_DRAM (1<<0) /* Dynamic RAM select */
608
609	/*
610	*************************************************************************
611	* SI Mode Register (SIMODE) *
612	*************************************************************************
613	*/
614	#define M360_SI_SMC2_BITS 0xFFFF0000 /* All SMC2 bits */
615	#define M360_SI_SMC2_TDM (1<<31) /* Multiplexed SMC2 */
616	#define M360_SI_SMC2_BRG1 (0<<28) /* SMC2 clock souce */
617	#define M360_SI_SMC2_BRG2 (1<<28)
618	#define M360_SI_SMC2_BRG3 (2<<28)
619	#define M360_SI_SMC2_BRG4 (3<<28)
620	#define M360_SI_SMC2_CLK5 (0<<28)
621	#define M360_SI_SMC2_CLK6 (1<<28)
622	#define M360_SI_SMC2_CLK7 (2<<28)
623	#define M360_SI_SMC2_CLK8 (3<<28)
624	#define M360_SI_SMC1_BITS 0x0000FFFF /* All SMC1 bits */
625	#define M360_SI_SMC1_TDM (1<<15) /* Multiplexed SMC1 */
626	#define M360_SI_SMC1_BRG1 (0<<12) /* SMC1 clock souce */
627	#define M360_SI_SMC1_BRG2 (1<<12)
628	#define M360_SI_SMC1_BRG3 (2<<12)
629	#define M360_SI_SMC1_BRG4 (3<<12)
630	#define M360_SI_SMC1_CLK1 (0<<12)
631	#define M360_SI_SMC1_CLK2 (1<<12)
632	#define M360_SI_SMC1_CLK3 (2<<12)
633	#define M360_SI_SMC1_CLK4 (3<<12)
634
635	/*
636	*************************************************************************
637	* SDMA Configuration Register (SDMA) *
638	*************************************************************************
639	*/
640	#define M360_SDMA_FREEZE (2<<13) /* Freeze on next bus cycle */
641	#define M360_SDMA_SISM_7 (7<<8) /* Normal interrupt service mask */
642	#define M360_SDMA_SAID_4 (4<<4) /* Normal arbitration ID */
643	#define M360_SDMA_INTE (1<<1) /* SBER interrupt enable */
644	#define M360_SDMA_INTB (1<<0) /* SBKP interrupt enable */
645
646	/*
647	*************************************************************************
648	* Baud (sic) Rate Generators *
649	*************************************************************************
650	*/
651	#define M360_BRG_RST (1<<17) /* Reset generator */
652	#define M360_BRG_EN (1<<16) /* Enable generator */
653	#define M360_BRG_EXTC_BRGCLK (0<<14) /* Source is BRGCLK */
654	#define M360_BRG_EXTC_CLK2 (1<<14) /* Source is CLK2 pin */
655	#define M360_BRG_EXTC_CLK6 (2<<14) /* Source is CLK6 pin */
656	#define M360_BRG_ATB (1<<13) /* Autobaud */
657	#define M360_BRG_115200 (13<<1) /* Assume 25 MHz clock */
658	#define M360_BRG_57600 (26<<1)
659	#define M360_BRG_38400 (40<<1)
660	#define M360_BRG_19200 (80<<1)
661	#define M360_BRG_9600 (162<<1)
662	#define M360_BRG_4800 (324<<1)
663	#define M360_BRG_2400 (650<<1)
664	#define M360_BRG_1200 (1301<<1)
665	#define M360_BRG_600 (2603<<1)
666	#define M360_BRG_300 ((324<<1) \| 1)
667	#define M360_BRG_150 ((650<<1) \| 1)
668	#define M360_BRG_75 ((1301<<1) \| 1)
669
670	/*
671	*************************************************************************
672	* sccm Bit Settings *
673	*************************************************************************
674	*/
675	#define M360_SCCE_TX 0x02
676	#define M360_SCCE_RX 0x01
677
678	#define M360_CR_INIT_TX_RX_PARAMS 0x0000
679	#define M360_CR_CH_NUM 0x0040
680
681	#define M360_NUM_DPRAM_REAGONS 4
682	/*
683	*************************************************************************
684	* MC68360 DUAL-PORT RAM AND REGISTERS *
685	*************************************************************************
686	*/
687	typedef struct m360_ {
688	/*
689	* Dual-port RAM
690	*/
691	volatile uint8_t dpram0[0x400]; /* Microcode program */
692	volatile uint8_t dpram1[0x200];
693	volatile uint8_t dpram2[0x100]; /* Microcode scratch */
694	volatile uint8_t dpram3[0x100]; /* Not on REV A or B masks */
695	volatile uint8_t _rsv0[0xC00-0x800];
696	volatile m360SCCENparms_t scc1p;
697	volatile uint8_t _rsv1[0xCB0-0xC00-sizeof(m360SCCENparms_t)];
698	volatile m360MiscParms_t miscp;
699	volatile uint8_t _rsv2[0xD00-0xCB0-sizeof(m360MiscParms_t)];
700	volatile m360SCCparms_t scc2p;
701	volatile uint8_t _rsv3[0xD80-0xD00-sizeof(m360SCCparms_t)];
702	volatile m360SPIparms_t spip;
703	volatile uint8_t _rsv4[0xDB0-0xD80-sizeof(m360SPIparms_t)];
704	volatile m360TimerParms_t tmp;
705	volatile uint8_t _rsv5[0xE00-0xDB0-sizeof(m360TimerParms_t)];
706	volatile m360SCCparms_t scc3p;
707	volatile uint8_t _rsv6[0xE70-0xE00-sizeof(m360SCCparms_t)];
708	volatile m360IDMAparms_t idma1p;
709	volatile uint8_t _rsv7[0xE80-0xE70-sizeof(m360IDMAparms_t)];
710	volatile m360SMCparms_t smc1p;
711	volatile uint8_t _rsv8[0xF00-0xE80-sizeof(m360SMCparms_t)];
712	volatile m360SCCparms_t scc4p;
713	volatile uint8_t _rsv9[0xF70-0xF00-sizeof(m360SCCparms_t)];
714	volatile m360IDMAparms_t idma2p;
715	volatile uint8_t _rsv10[0xF80-0xF70-sizeof(m360IDMAparms_t)];
716	volatile m360SMCparms_t smc2p;
717	volatile uint8_t _rsv11[0x1000-0xF80-sizeof(m360SMCparms_t)];
718
719	/*
720	* SIM Block
721	*/
722	volatile uint32_t mcr;
723	volatile uint32_t _pad00;
724	volatile uint8_t avr;
725	volatile uint8_t rsr;
726	volatile uint16_t _pad01;
727	volatile uint8_t clkocr;
728	volatile uint8_t _pad02;
729	volatile uint16_t _pad03;
730	volatile uint16_t pllcr;
731	volatile uint16_t _pad04;
732	volatile uint16_t cdvcr;
733	volatile uint16_t pepar;
734	volatile uint32_t _pad05[2];
735	volatile uint16_t _pad06;
736	volatile uint8_t sypcr;
737	volatile uint8_t swiv;
738	volatile uint16_t _pad07;
739	volatile uint16_t picr;
740	volatile uint16_t _pad08;
741	volatile uint16_t pitr;
742	volatile uint16_t _pad09;
743	volatile uint8_t _pad10;
744	volatile uint8_t swsr;
745	volatile uint32_t bkar;
746	volatile uint32_t bcar;
747	volatile uint32_t _pad11[2];
748
749	/*
750	* MEMC Block
751	*/
752	volatile uint32_t gmr;
753	volatile uint16_t mstat;
754	volatile uint16_t _pad12;
755	volatile uint32_t _pad13[2];
756	volatile m360MEMCRegisters_t memc[8];
757	volatile uint8_t _pad14[0xF0-0xD0];
758	volatile uint8_t _pad15[0x100-0xF0];
759	volatile uint8_t _pad16[0x500-0x100];
760
761	/*
762	* IDMA1 Block
763	*/
764	volatile uint16_t iccr;
765	volatile uint16_t _pad17;
766	volatile uint16_t cmr1;
767	volatile uint16_t _pad18;
768	volatile uint32_t sapr1;
769	volatile uint32_t dapr1;
770	volatile uint32_t bcr1;
771	volatile uint8_t fcr1;
772	volatile uint8_t _pad19;
773	volatile uint8_t cmar1;
774	volatile uint8_t _pad20;
775	volatile uint8_t csr1;
776	volatile uint8_t _pad21;
777	volatile uint16_t _pad22;
778
779	/*
780	* SDMA Block
781	*/
782	volatile uint8_t sdsr;
783	volatile uint8_t _pad23;
784	volatile uint16_t sdcr;
785	volatile uint32_t sdar;
786
787	/*
788	* IDMA2 Block
789	*/
790	volatile uint16_t _pad24;
791	volatile uint16_t cmr2;
792	volatile uint32_t sapr2;
793	volatile uint32_t dapr2;
794	volatile uint32_t bcr2;
795	volatile uint8_t fcr2;
796	volatile uint8_t _pad26;
797	volatile uint8_t cmar2;
798	volatile uint8_t _pad27;
799	volatile uint8_t csr2;
800	volatile uint8_t _pad28;
801	volatile uint16_t _pad29;
802	volatile uint32_t _pad30;
803
804	/*
805	* CPIC Block
806	*/
807	volatile uint32_t cicr;
808	volatile uint32_t cipr;
809	volatile uint32_t cimr;
810	volatile uint32_t cisr;
811
812	/*
813	* Parallel I/O Block
814	*/
815	volatile uint16_t padir;
816	volatile uint16_t papar;
817	volatile uint16_t paodr;
818	volatile uint16_t padat;
819	volatile uint32_t _pad31[2];
820	volatile uint16_t pcdir;
821	volatile uint16_t pcpar;
822	volatile uint16_t pcso;
823	volatile uint16_t pcdat;
824	volatile uint16_t pcint;
825	volatile uint16_t _pad32;
826	volatile uint32_t _pad33[5];
827
828	/*
829	* TIMER Block
830	*/
831	volatile uint16_t tgcr;
832	volatile uint16_t _pad34;
833	volatile uint32_t _pad35[3];
834	volatile uint16_t tmr1;
835	volatile uint16_t tmr2;
836	volatile uint16_t trr1;
837	volatile uint16_t trr2;
838	volatile uint16_t tcr1;
839	volatile uint16_t tcr2;
840	volatile uint16_t tcn1;
841	volatile uint16_t tcn2;
842	volatile uint16_t tmr3;
843	volatile uint16_t tmr4;
844	volatile uint16_t trr3;
845	volatile uint16_t trr4;
846	volatile uint16_t tcr3;
847	volatile uint16_t tcr4;
848	volatile uint16_t tcn3;
849	volatile uint16_t tcn4;
850	volatile uint16_t ter1;
851	volatile uint16_t ter2;
852	volatile uint16_t ter3;
853	volatile uint16_t ter4;
854	volatile uint32_t _pad36[2];
855
856	/*
857	* CP Block
858	*/
859	volatile uint16_t cr;
860	volatile uint16_t _pad37;
861	volatile uint16_t rccr;
862	volatile uint16_t _pad38;
863	volatile uint32_t _pad39[3];
864	volatile uint16_t _pad40;
865	volatile uint16_t rter;
866	volatile uint16_t _pad41;
867	volatile uint16_t rtmr;
868	volatile uint32_t _pad42[5];
869
870	/*
871	* BRG Block
872	*/
873	volatile uint32_t brgc1;
874	volatile uint32_t brgc2;
875	volatile uint32_t brgc3;
876	volatile uint32_t brgc4;
877
878	/*
879	* SCC Block
880	*/
881	volatile m360SCCRegisters_t scc1;
882	volatile m360SCCRegisters_t scc2;
883	volatile m360SCCRegisters_t scc3;
884	volatile m360SCCRegisters_t scc4;
885
886	/*
887	* SMC Block
888	*/
889	volatile m360SMCRegisters_t smc1;
890	volatile m360SMCRegisters_t smc2;
891
892	/*
893	* SPI Block
894	*/
895	volatile uint16_t spmode;
896	volatile uint16_t _pad43[2];
897	volatile uint8_t spie;
898	volatile uint8_t _pad44;
899	volatile uint16_t _pad45;
900	volatile uint8_t spim;
901	volatile uint8_t _pad46[2];
902	volatile uint8_t spcom;
903	volatile uint16_t _pad47[2];
904
905	/*
906	* PIP Block
907	*/
908	volatile uint16_t pipc;
909	volatile uint16_t _pad48;
910	volatile uint16_t ptpr;
911	volatile uint32_t pbdir;
912	volatile uint32_t pbpar;
913	volatile uint16_t _pad49;
914	volatile uint16_t pbodr;
915	volatile uint32_t pbdat;
916	volatile uint32_t _pad50[6];
917
918	/*
919	* SI Block
920	*/
921	volatile uint32_t simode;
922	volatile uint8_t sigmr;
923	volatile uint8_t _pad51;
924	volatile uint8_t sistr;
925	volatile uint8_t sicmr;
926	volatile uint32_t _pad52;
927	volatile uint32_t sicr;
928	volatile uint16_t _pad53;
929	volatile uint16_t sirp[2];
930	volatile uint16_t _pad54;
931	volatile uint32_t _pad55[2];
932	volatile uint8_t siram[256];
933	} m360_t;
934
935	struct bdregions_t {
936	volatile unsigned char *base;
937	unsigned int size;
938	unsigned int used;
939	};
940
941	#define M68360_RX_BUF_SIZE 1
942	#define M68360_TX_BUF_SIZE 0x100
943
944	struct _m68360_per_chip;
945	typedef struct _m68360_per_chip *M68360_t;
946
947	typedef struct _m68360_per_port {
948	uint32_t channel;
949	M68360_t chip;
950	volatile uint32_t pBRGC; / m360->brgc# */
951	volatile m360SCCparms_t pSCCB; / m360->scc#p */
952	volatile m360SCCRegisters_t pSCCR; / m360->scc# */
953	uint32_t baud;
954	int minor;
955	volatile uint8_t *rxBuf;
956	volatile uint8_t *txBuf;
957	volatile m360BufferDescriptor_t *sccRxBd;
958	volatile m360BufferDescriptor_t *sccTxBd;
959	}m68360_per_port_t, *M68360_serial_ports_t;
960
961	typedef struct _m68360_per_chip {
962	struct _m68360_per_chip *next;
963	struct bdregions_t bdregions[4];
964	volatile m360_t m360; / Pointer to base Address */
965	int m360_interrupt;
966	int m360_clock_rate;
967	PPMCQ1BoardData board_data;
968	m68360_per_port_t port[4];
969	} m68360_per_chip_t;
970
971	extern M68360_t M68360_chips;
972
973	void M360SetupMemory( M68360_t ptr );
974	void *M360AllocateBufferDescriptors (M68360_t ptr, int count);
975	void M360ExecuteRISC( volatile m360_t *m360, uint16_t command);
976	int mc68360_scc_create_chip( PPMCQ1BoardData BoardData, uint8_t int_vector );
977
978	#endif /* __MC68360_h */

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source: rtems/c/src/lib/libbsp/powerpc/ep1a/console/m68360.h @ e160e41

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