source: rtems/c/src/lib/libbsp/powerpc/ep1a/console/init68360.c @ 0329aae

4.104.114.84.95
Last change on this file since 0329aae was 0329aae, checked in by Jennifer Averett <Jennifer.Averett@…>, on 04/28/05 at 14:05:14

2005-04-28 Jennifer Averett <jennifer.averett@…>

  • acinclude.m4: Initial release of ep1a bsp
  • ep1a/Makefile.am, ep1a/bsp_specs, ep1a/configure.ac, ep1a/console/alloc360.c, ep1a/console/console.c, ep1a/console/console.h, ep1a/console/init68360.c, ep1a/console/m68360.h, ep1a/console/mc68360_scc.c, ep1a/console/ns16550cfg.c, ep1a/console/ns16550cfg.h, ep1a/console/rsPMCQ1.c, ep1a/console/rsPMCQ1.h, ep1a/include/bsp.h, ep1a/irq/irq.c, ep1a/irq/irq_init.c, ep1a/pci/no_host_bridge.c, ep1a/start/start.S, ep1a/startup/bspstart.c, ep1a/startup/linkcmds, ep1a/vme/vmeconfig.c: New files.
  • Property mode set to 100644
File size: 19.0 KB
Line 
1/*
2 *  MC68360 support routines
3 *
4 *  W. Eric Norum
5 *  Saskatchewan Accelerator Laboratory
6 *  University of Saskatchewan
7 *  Saskatoon, Saskatchewan, CANADA
8 *  eric@skatter.usask.ca
9 *
10 *  COPYRIGHT (c) 1989-1999.
11 *  On-Line Applications Research Corporation (OAR).
12 *
13 *  The license and distribution terms for this file may be
14 *  found in the file LICENSE in this distribution or at
15 *  http://www.rtems.com/license/LICENSE.
16 *
17 *  $Id$
18 */
19
20#include <rtems.h>
21#include <bsp.h>
22#include "m68360.h"
23
24/*
25 * Send a command to the CPM RISC processer
26 */
27
28void M360ExecuteRISC( volatile m360_t *m360, rtems_unsigned16 command)
29{
30        rtems_unsigned16 sr;
31
32        rtems_interrupt_disable(sr);
33        while (m360->cr & M360_CR_FLG)
34                continue;
35        m360->cr = command | M360_CR_FLG;
36        rtems_interrupt_enable(sr);
37}
38
39
40#if 0
41/*
42 * Initialize MC68360
43 */
44void _Init68360 (void)
45{
46        int i;
47        m68k_isr_entry *vbr;
48        unsigned long ramSize;
49        extern void _CopyDataClearBSSAndStart (unsigned long ramSize);
50
51#if (defined (__mc68040__))
52        /*
53         *******************************************
54         * Motorola 68040 and companion-mode 68360 *
55         *******************************************
56         */
57
58        /*
59         * Step 6: Is this a power-up reset?
60         * For now we just ignore this and do *all* the steps
61         * Someday we might want to:
62         *      if (Hard, Loss of Clock, Power-up)
63         *              Do all steps
64         *      else if (Double bus fault, watchdog or soft reset)
65         *              Skip to step 12
66         *      else (must be a reset command)
67         *              Skip to step 14
68         */
69
70        /*
71         * Step 7: Deal with clock synthesizer
72         * HARDWARE:
73         *      Change if you're not using an external 25 MHz oscillator.
74         */
75        m360.clkocr = 0x83;     /* No more writes, full-power CLKO2 */
76        m360.pllcr = 0xD000;    /* PLL, no writes, no prescale,
77                                   no LPSTOP slowdown, PLL X1 */
78        m360.cdvcr = 0x8000;    /* No more writes, no clock division */
79
80        /*
81         * Step 8: Initialize system protection
82         *      Enable watchdog
83         *      Watchdog causes system reset
84         *      Next-to-slowest watchdog timeout (21 seconds with 25 MHz oscillator)
85         *      Enable double bus fault monitor
86         *      Enable bus monitor for external cycles
87         *      1024 clocks for external timeout
88         */
89        m360.sypcr = 0xEC;
90
91        /*
92         * Step 9: Clear parameter RAM and reset communication processor module
93         */
94        for (i = 0 ; i < 192  ; i += sizeof (long)) {
95                *((long *)((char *)&m360 + 0xC00 + i)) = 0;
96                *((long *)((char *)&m360 + 0xD00 + i)) = 0;
97                *((long *)((char *)&m360 + 0xE00 + i)) = 0;
98                *((long *)((char *)&m360 + 0xF00 + i)) = 0;
99        }
100        M360ExecuteRISC (M360_CR_RST);
101
102        /*
103         * Step 10: Write PEPAR
104         *      SINTOUT standard M68000 family interrupt level encoding
105         *      CF1MODE=10 (BCLRO* output)
106         *      No RAS1* double drive
107         *      A31 - A28
108         *      AMUX output
109         *      CAS2* - CAS3*
110         *      CAS0* - CAS1*
111         *      CS7*
112         *      AVEC*
113         */
114        m360.pepar = 0x3440;
115
116        /*
117         * Step 11: Remap Chip Select 0 (CS0*), set up GMR
118         */
119        /*
120         * 512 addresses per DRAM page (256K DRAM chips)
121         * 70 nsec DRAM
122         * 180 nsec ROM (3 wait states)
123         */
124        m360.gmr = M360_GMR_RCNT(23) | M360_GMR_RFEN |
125                                M360_GMR_RCYC(0) | M360_GMR_PGS(1) |
126                                M360_GMR_DPS_32BIT | M360_GMR_NCS |
127                                M360_GMR_TSS40;
128        m360.memc[0].br = (unsigned long)&_RomBase | M360_MEMC_BR_WP |
129                                                        M360_MEMC_BR_V;
130        m360.memc[0].or = M360_MEMC_OR_WAITS(3) | M360_MEMC_OR_1MB |
131                                                M360_MEMC_OR_32BIT;
132
133        /*
134         * Step 12: Initialize the system RAM
135         */
136        /*
137         *      Set up option/base registers
138         *              1M DRAM
139         *              70 nsec DRAM
140         *      Enable burst mode
141         *      No parity checking
142         *      Wait for chips to power up
143         *      Perform 8 read cycles
144         */
145        ramSize = 1 * 1024 * 1024;
146        m360.memc[1].or = M360_MEMC_OR_TCYC(0) |
147                                        M360_MEMC_OR_1MB |
148                                        M360_MEMC_OR_DRAM;
149        m360.memc[1].br = (unsigned long)&_RamBase |
150                                        M360_MEMC_BR_BACK40 |
151                                        M360_MEMC_BR_V;
152        for (i = 0; i < 50000; i++)
153                continue;
154        for (i = 0; i < 8; ++i)
155                *((volatile unsigned long *)(unsigned long)&_RamBase);
156
157        /*
158         * Step 13: Copy  the exception vector table to system RAM
159         */
160        m68k_get_vbr (vbr);
161        for (i = 0; i < 256; ++i)
162                M68Kvec[i] = vbr[i];
163        m68k_set_vbr (M68Kvec);
164       
165        /*
166         * Step 14: More system initialization
167         * SDCR (Serial DMA configuration register)
168         *      Enable SDMA during FREEZE
169         *      Give SDMA priority over all interrupt handlers
170         *      Set DMA arbiration level to 4
171         * CICR (CPM interrupt configuration register):
172         *      SCC1 requests at SCCa position
173         *      SCC2 requests at SCCb position
174         *      SCC3 requests at SCCc position
175         *      SCC4 requests at SCCd position
176         *      Interrupt request level 4
177         *      Maintain original priority order
178         *      Vector base 128
179         *      SCCs priority grouped at top of table
180         */
181        m360.sdcr = M360_SDMA_SISM_7 | M360_SDMA_SAID_4;
182        m360.cicr = (3 << 22) | (2 << 20) | (1 << 18) | (0 << 16) |
183                                                (4 << 13) | (0x1F << 8) | (128);
184
185        /*
186         * Step 15: Set module configuration register
187         *      Bus request MC68040 Arbitration ID 3
188         *      Bus asynchronous timing mode (work around bug in Rev. B)
189         *      Arbitration asynchronous timing mode
190         *      Disable timers during FREEZE
191         *      Disable bus monitor during FREEZE
192         *      BCLRO* arbitration level 3
193         *      No show cycles
194         *      User/supervisor access
195         *      Bus clear in arbitration ID level  3
196         *      SIM60 interrupt sources higher priority than CPM
197         */
198        m360.mcr = 0x6000EC3F;
199
200#elif (defined (M68360_ATLAS_HSB))
201        /*
202         ******************************************
203         * Standalone Motorola 68360 -- ATLAS HSB *
204         ******************************************
205         */
206
207        /*
208         * Step 6: Is this a power-up reset?
209         * For now we just ignore this and do *all* the steps
210         * Someday we might want to:
211         *      if (Hard, Loss of Clock, Power-up)
212         *              Do all steps
213         *      else if (Double bus fault, watchdog or soft reset)
214         *              Skip to step 12
215         *      else (must be a CPU32+ reset command)
216         *              Skip to step 14
217         */
218
219        /*
220         * Step 7: Deal with clock synthesizer
221         * HARDWARE:
222         *      Change if you're not using an external 25 MHz oscillator.
223         */
224        m360.clkocr = 0x8F;     /* No more writes, no clock outputs */
225        m360.pllcr = 0xD000;    /* PLL, no writes, no prescale,
226                                   no LPSTOP slowdown, PLL X1 */
227        m360.cdvcr = 0x8000;    /* No more writes, no clock division */
228
229        /*
230         * Step 8: Initialize system protection
231         *      Enable watchdog
232         *      Watchdog causes system reset
233         *      Next-to-slowest watchdog timeout (21 seconds with 25 MHz oscillator)
234         *      Enable double bus fault monitor
235         *      Enable bus monitor for external cycles
236         *      1024 clocks for external timeout
237         */
238        m360.sypcr = 0xEC;
239
240        /*
241         * Step 9: Clear parameter RAM and reset communication processor module
242         */
243        for (i = 0 ; i < 192  ; i += sizeof (long)) {
244                *((long *)((char *)&m360 + 0xC00 + i)) = 0;
245                *((long *)((char *)&m360 + 0xD00 + i)) = 0;
246                *((long *)((char *)&m360 + 0xE00 + i)) = 0;
247                *((long *)((char *)&m360 + 0xF00 + i)) = 0;
248        }
249        M360ExecuteRISC (M360_CR_RST);
250
251        /*
252         * Step 10: Write PEPAR
253         *      SINTOUT not used (CPU32+ mode)
254         *      CF1MODE=00 (CONFIG1 input)
255         *      RAS1* double drive
256         *      WE0* - WE3*
257         *      OE* output
258         *      CAS2* - CAS3*
259         *      CAS0* - CAS1*
260         *      CS7*
261         *      AVEC*
262         * HARDWARE:
263         *      Change if you are using a different memory configuration
264         *      (static RAM, external address multiplexing, etc).
265         */
266        m360.pepar = 0x0180;
267
268        /*
269         * Step 11: Remap Chip Select 0 (CS0*), set up GMR
270         */
271        m360.gmr = M360_GMR_RCNT(12) | M360_GMR_RFEN |
272                                M360_GMR_RCYC(0) | M360_GMR_PGS(1) |
273                                M360_GMR_DPS_32BIT | M360_GMR_DWQ |
274                                M360_GMR_GAMX;
275        m360.memc[0].br = (unsigned long)&_RomBase | M360_MEMC_BR_WP |
276                                                                M360_MEMC_BR_V;
277        m360.memc[0].or = M360_MEMC_OR_WAITS(3) | M360_MEMC_OR_1MB |
278                                                        M360_MEMC_OR_8BIT;
279
280        /*
281         * Step 12: Initialize the system RAM
282         */
283        ramSize = 2 * 1024 * 1024;
284        /* first bank 1MByte DRAM */
285        m360.memc[1].or = M360_MEMC_OR_TCYC(2) | M360_MEMC_OR_1MB |
286                                        M360_MEMC_OR_PGME | M360_MEMC_OR_DRAM;
287        m360.memc[1].br = (unsigned long)&_RamBase | M360_MEMC_BR_V;
288
289        /* second bank 1MByte DRAM */
290        m360.memc[2].or = M360_MEMC_OR_TCYC(2) | M360_MEMC_OR_1MB |
291                                        M360_MEMC_OR_PGME | M360_MEMC_OR_DRAM;
292        m360.memc[2].br = ((unsigned long)&_RamBase + 0x100000) |
293                                        M360_MEMC_BR_V;
294
295        /* flash rom socket U6 on CS5 */
296        m360.memc[5].br = (unsigned long)ATLASHSB_ROM_U6 | M360_MEMC_BR_WP |
297                                                                M360_MEMC_BR_V;
298        m360.memc[5].or = M360_MEMC_OR_WAITS(2) | M360_MEMC_OR_512KB |
299                                                                M360_MEMC_OR_8BIT;
300
301        /* CSRs on CS7 */
302        m360.memc[7].or = M360_MEMC_OR_TCYC(4) | M360_MEMC_OR_64KB |
303                                        M360_MEMC_OR_8BIT;
304        m360.memc[7].br = ATLASHSB_ESR | 0x01;
305        for (i = 0; i < 50000; i++)
306                continue;
307        for (i = 0; i < 8; ++i)
308                *((volatile unsigned long *)(unsigned long)&_RamBase);
309
310        /*
311         * Step 13: Copy  the exception vector table to system RAM
312         */
313        m68k_get_vbr (vbr);
314        for (i = 0; i < 256; ++i)
315                M68Kvec[i] = vbr[i];
316        m68k_set_vbr (M68Kvec);
317       
318        /*
319         * Step 14: More system initialization
320         * SDCR (Serial DMA configuration register)
321         *      Enable SDMA during FREEZE
322         *      Give SDMA priority over all interrupt handlers
323         *      Set DMA arbiration level to 4
324         * CICR (CPM interrupt configuration register):
325         *      SCC1 requests at SCCa position
326         *      SCC2 requests at SCCb position
327         *      SCC3 requests at SCCc position
328         *      SCC4 requests at SCCd position
329         *      Interrupt request level 4
330         *      Maintain original priority order
331         *      Vector base 128
332         *      SCCs priority grouped at top of table
333         */
334        m360.sdcr = M360_SDMA_SISM_7 | M360_SDMA_SAID_4;
335        m360.cicr = (3 << 22) | (2 << 20) | (1 << 18) | (0 << 16) |
336                                                (4 << 13) | (0x1F << 8) | (128);
337
338        /*
339         * Step 15: Set module configuration register
340         *      Disable timers during FREEZE
341         *      Enable bus monitor during FREEZE
342         *      BCLRO* arbitration level 3
343         */
344
345#elif (defined (GEN68360_WITH_SRAM))
346   /*
347    ***************************************************
348    * Generic Standalone Motorola 68360               *
349    *           As described in MC68360 User's Manual *
350    * But uses SRAM instead of DRAM                   *
351    *  CS0* - 512kx8 flash memory                     *
352    *  CS1* - 512kx32 static RAM                      *
353    *  CS2* - 512kx32 static RAM                      *
354    ***************************************************
355    */
356
357   /*
358    * Step 7: Deal with clock synthesizer
359    * HARDWARE:
360    * Change if you're not using an external oscillator which
361    * oscillates at the system clock rate.
362    */
363   m360.clkocr = 0x8F;     /* No more writes, no clock outputs */
364   m360.pllcr = 0xD000;    /* PLL, no writes, no prescale,
365                              no LPSTOP slowdown, PLL X1 */
366   m360.cdvcr = 0x8000;    /* No more writes, no clock division */
367
368   /*
369    * Step 8: Initialize system protection
370    * Enable watchdog
371    * Watchdog causes system reset
372    * Next-to-slowest watchdog timeout (21 seconds with 25 MHz oscillator)
373    * Enable double bus fault monitor
374    * Enable bus monitor for external cycles
375    * 1024 clocks for external timeout
376    */
377    m360.sypcr = 0xEC;
378
379   /*
380    * Step 9: Clear parameter RAM and reset communication processor module
381    */
382   for (i = 0 ; i < 192  ; i += sizeof (long)) {
383      *((long *)((char *)&m360 + 0xC00 + i)) = 0;
384      *((long *)((char *)&m360 + 0xD00 + i)) = 0;
385      *((long *)((char *)&m360 + 0xE00 + i)) = 0;
386      *((long *)((char *)&m360 + 0xF00 + i)) = 0;
387   }
388   M360ExecuteRISC (M360_CR_RST);
389
390   /*
391    * Step 10: Write PEPAR
392    * SINTOUT not used (CPU32+ mode)
393    * CF1MODE=00 (CONFIG1 input)
394    * IPIPE1*
395    * WE0* - WE3*
396    * OE* output
397    * CAS2* - CAS3*
398    * CAS0* - CAS1*
399    * CS7*
400    * AVEC*
401    * HARDWARE:
402    * Change if you are using a different memory configuration
403    * (static RAM, external address multiplexing, etc).
404    */
405   m360.pepar = 0x0080;
406
407   /*
408    * Step 11: Set up GMR
409    *     
410    */
411   m360.gmr = 0x0;
412
413   /*
414    * Step 11a: Remap 512Kx8 flash memory on CS0*
415    * 2 wait states
416    * Make it read-only for now
417    */
418   m360.memc[0].br = (unsigned long)&_RomBase | M360_MEMC_BR_WP |
419                                                   M360_MEMC_BR_V;
420   m360.memc[0].or = M360_MEMC_OR_WAITS(2) | M360_MEMC_OR_512KB |
421                                                   M360_MEMC_OR_8BIT;
422   /*
423    * Step 12: Set up main memory
424    * 512Kx32 SRAM on CS1*
425    * 512Kx32 SRAM on CS2*
426    * 0 wait states
427    */
428   ramSize = 4 * 1024 * 1024;
429   m360.memc[1].br = (unsigned long)&_RamBase | M360_MEMC_BR_V;
430   m360.memc[1].or = M360_MEMC_OR_WAITS(0) | M360_MEMC_OR_2MB |
431                                                   M360_MEMC_OR_32BIT;
432   m360.memc[2].br = ((unsigned long)&_RamBase + 0x200000) | M360_MEMC_BR_V;
433   m360.memc[2].or = M360_MEMC_OR_WAITS(0) | M360_MEMC_OR_2MB |
434                                                   M360_MEMC_OR_32BIT;
435   /*
436    * Step 13: Copy  the exception vector table to system RAM
437    */
438   m68k_get_vbr (vbr);
439   for (i = 0; i < 256; ++i)
440           M68Kvec[i] = vbr[i];
441   m68k_set_vbr (M68Kvec);
442
443   /*
444    * Step 14: More system initialization
445    * SDCR (Serial DMA configuration register)
446    * Enable SDMA during FREEZE
447    * Give SDMA priority over all interrupt handlers
448    * Set DMA arbiration level to 4
449    * CICR (CPM interrupt configuration register):
450    * SCC1 requests at SCCa position
451    * SCC2 requests at SCCb position
452    * SCC3 requests at SCCc position
453    * SCC4 requests at SCCd position
454    * Interrupt request level 4
455    * Maintain original priority order
456    * Vector base 128
457    * SCCs priority grouped at top of table
458    */
459   m360.sdcr = M360_SDMA_SISM_7 | M360_SDMA_SAID_4;
460   m360.cicr = (3 << 22) | (2 << 20) | (1 << 18) | (0 << 16) |
461                  (4 << 13) | (0x1F << 8) | (128);
462
463   /*
464    * Step 15: Set module configuration register
465    * Disable timers during FREEZE
466    * Enable bus monitor during FREEZE
467    * BCLRO* arbitration level 3
468    * No show cycles
469    * User/supervisor access
470    * Bus clear interrupt service level 7
471    * SIM60 interrupt sources higher priority than CPM
472    */
473   m360.mcr = 0x4C7F;
474
475#else
476        /*
477         ***************************************************
478         * Generic Standalone Motorola 68360               *
479         *           As described in MC68360 User's Manual *
480         *           Atlas ACE360                          *
481         ***************************************************
482         */
483
484        /*
485         * Step 6: Is this a power-up reset?
486         * For now we just ignore this and do *all* the steps
487         * Someday we might want to:
488         *      if (Hard, Loss of Clock, Power-up)
489         *              Do all steps
490         *      else if (Double bus fault, watchdog or soft reset)
491         *              Skip to step 12
492         *      else (must be a CPU32+ reset command)
493         *              Skip to step 14
494         */
495
496        /*
497         * Step 7: Deal with clock synthesizer
498         * HARDWARE:
499         *      Change if you're not using an external 25 MHz oscillator.
500         */
501        m360.clkocr = 0x8F;     /* No more writes, no clock outputs */
502        m360.pllcr = 0xD000;    /* PLL, no writes, no prescale,
503                                   no LPSTOP slowdown, PLL X1 */
504        m360.cdvcr = 0x8000;    /* No more writes, no clock division */
505
506        /*
507         * Step 8: Initialize system protection
508         *      Enable watchdog
509         *      Watchdog causes system reset
510         *      Next-to-slowest watchdog timeout (21 seconds with 25 MHz oscillator)
511         *      Enable double bus fault monitor
512         *      Enable bus monitor for external cycles
513         *      1024 clocks for external timeout
514         */
515        m360.sypcr = 0xEC;
516
517        /*
518         * Step 9: Clear parameter RAM and reset communication processor module
519         */
520        for (i = 0 ; i < 192  ; i += sizeof (long)) {
521                *((long *)((char *)&m360 + 0xC00 + i)) = 0;
522                *((long *)((char *)&m360 + 0xD00 + i)) = 0;
523                *((long *)((char *)&m360 + 0xE00 + i)) = 0;
524                *((long *)((char *)&m360 + 0xF00 + i)) = 0;
525        }
526        M360ExecuteRISC (M360_CR_RST);
527
528        /*
529         * Step 10: Write PEPAR
530         *      SINTOUT not used (CPU32+ mode)
531         *      CF1MODE=00 (CONFIG1 input)
532         *      RAS1* double drive
533         *      WE0* - WE3*
534         *      OE* output
535         *      CAS2* - CAS3*
536         *      CAS0* - CAS1*
537         *      CS7*
538         *      AVEC*
539         * HARDWARE:
540         *      Change if you are using a different memory configuration
541         *      (static RAM, external address multiplexing, etc).
542         */
543        m360.pepar = 0x0180;
544
545        /*
546         * Step 11: Remap Chip Select 0 (CS0*), set up GMR
547         *      32-bit DRAM
548         *      Internal DRAM address multiplexing
549         *      60 nsec DRAM
550         *      180 nsec ROM (3 wait states)
551         *      15.36 usec DRAM refresh interval
552         *      The DRAM page size selection is not modified since this
553         *      startup code may be running in a bootstrap PROM or in
554         *      a program downloaded by the bootstrap PROM.
555         */
556        m360.gmr = (m360.gmr & 0x001C0000) | M360_GMR_RCNT(23) |
557                                        M360_GMR_RFEN | M360_GMR_RCYC(0) |
558                                        M360_GMR_DPS_32BIT | M360_GMR_NCS |
559                                        M360_GMR_GAMX;
560        m360.memc[0].br = (unsigned long)&_RomBase | M360_MEMC_BR_WP |
561                                                                M360_MEMC_BR_V;
562        m360.memc[0].or = M360_MEMC_OR_WAITS(3) | M360_MEMC_OR_1MB |
563                                                        M360_MEMC_OR_8BIT;
564
565        /*
566         * Step 12: Initialize the system RAM
567         * Do this only if the DRAM has not already been set up
568         */
569        if ((m360.memc[1].br & M360_MEMC_BR_V) == 0) {
570                /*
571                 * Set up GMR DRAM page size, option and  base registers
572                 *      Assume 16Mbytes of DRAM
573                 *      60 nsec DRAM
574                 */
575                m360.gmr = (m360.gmr & ~0x001C0000) | M360_GMR_PGS(5);
576                m360.memc[1].or = M360_MEMC_OR_TCYC(0) |
577                                                M360_MEMC_OR_16MB |
578                                                M360_MEMC_OR_DRAM;
579                m360.memc[1].br = (unsigned long)&_RamBase | M360_MEMC_BR_V;
580
581                /*
582                 * Wait for chips to power up
583                 *      Perform 8 read cycles
584                 */
585                for (i = 0; i < 50000; i++)
586                        continue;
587                for (i = 0; i < 8; ++i)
588                        *((volatile unsigned long *)(unsigned long)&_RamBase);
589
590                /*
591                 * Determine memory size (1, 4, or 16 Mbytes)
592                 * Set GMR DRAM page size appropriately.
593                 * The OR is left at 16 Mbytes.  The bootstrap PROM places its
594                 * .data and .bss segments at the top of the 16 Mbyte space.
595                 * A 1 Mbyte or 4 Mbyte DRAM will show up several times in
596                 * the memory map, but will work with the same bootstrap PROM.
597                 */
598                *(volatile char *)&_RamBase = 0;
599                *((volatile char *)&_RamBase+0x00C01800) = 1;
600                if (*(volatile char *)&_RamBase) {
601                        m360.gmr = (m360.gmr & ~0x001C0000) | M360_GMR_PGS(1);
602                }
603                else {
604                        *((volatile char *)&_RamBase+0x00801000) = 1;
605                        if (*(volatile char *)&_RamBase) {
606                                m360.gmr = (m360.gmr & ~0x001C0000) | M360_GMR_PGS(3);
607                        }
608                }
609
610                /*
611                 * Enable parity checking
612                 */
613                m360.memc[1].br |= M360_MEMC_BR_PAREN;
614        }
615        switch (m360.gmr & 0x001C0000) {
616        default:                ramSize =  4 * 1024 * 1024;     break;
617        case M360_GMR_PGS(1):   ramSize =  1 * 1024 * 1024;     break;
618        case M360_GMR_PGS(3):   ramSize =  4 * 1024 * 1024;     break;
619        case M360_GMR_PGS(5):   ramSize = 16 * 1024 * 1024;     break;
620        }
621
622        /*
623         * Step 13: Copy  the exception vector table to system RAM
624         */
625        m68k_get_vbr (vbr);
626        for (i = 0; i < 256; ++i)
627                M68Kvec[i] = vbr[i];
628        m68k_set_vbr (M68Kvec);
629       
630        /*
631         * Step 14: More system initialization
632         * SDCR (Serial DMA configuration register)
633         *      Enable SDMA during FREEZE
634         *      Give SDMA priority over all interrupt handlers
635         *      Set DMA arbiration level to 4
636         * CICR (CPM interrupt configuration register):
637         *      SCC1 requests at SCCa position
638         *      SCC2 requests at SCCb position
639         *      SCC3 requests at SCCc position
640         *      SCC4 requests at SCCd position
641         *      Interrupt request level 4
642         *      Maintain original priority order
643         *      Vector base 128
644         *      SCCs priority grouped at top of table
645         */
646        m360.sdcr = M360_SDMA_SISM_7 | M360_SDMA_SAID_4;
647        m360.cicr = (3 << 22) | (2 << 20) | (1 << 18) | (0 << 16) |
648                                                (4 << 13) | (0x1F << 8) | (128);
649
650        /*
651         * Step 15: Set module configuration register
652         *      Disable timers during FREEZE
653         *      Enable bus monitor during FREEZE
654         *      BCLRO* arbitration level 3
655         *      No show cycles
656         *      User/supervisor access
657         *      Bus clear interrupt service level 7
658         *      SIM60 interrupt sources higher priority than CPM
659         */
660        m360.mcr = 0x4C7F;
661#endif
662
663        /*
664         * Copy data, clear BSS, switch stacks and call main()
665         * Must pass ramSize as argument since the data/bss segment
666         * may be overwritten.
667         */
668        _CopyDataClearBSSAndStart (ramSize);
669}
670#endif
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