| 1 | /* |
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| 2 | ******************************************************************* |
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| 3 | ******************************************************************* |
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| 4 | ** ** |
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| 5 | ** DECLARATIONS FOR NATIONAL DP83932 `SONIC' ** |
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| 6 | ** SYSTEMS-ORIENTED NETWORK INTERFACE CONTROLLER ** |
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| 7 | ** ** |
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| 8 | ******************************************************************* |
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| 9 | ******************************************************************* |
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| 10 | */ |
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| 11 | |
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| 12 | /* |
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| 13 | * $Revision$ $Date$ $Author$ |
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| 14 | * $State$ |
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| 15 | */ |
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| 16 | |
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| 17 | #ifndef _SONIC_DP83932_ |
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| 18 | #define _SONIC_DP83932_ |
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| 19 | |
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| 20 | #include <bsp.h> |
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| 21 | |
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| 22 | /* |
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| 23 | ****************************************************************** |
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| 24 | * * |
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| 25 | * Device Registers * |
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| 26 | * * |
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| 27 | ****************************************************************** |
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| 28 | */ |
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| 29 | #define SONIC_REG_CR 0x00 /* Command */ |
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| 30 | #define SONIC_REG_DCR 0x01 /* Data configuration */ |
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| 31 | #define SONIC_REG_RCR 0x02 /* Receive control */ |
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| 32 | #define SONIC_REG_TCR 0x03 /* Transmit control */ |
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| 33 | #define SONIC_REG_IMR 0x04 /* Interrupt mask */ |
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| 34 | #define SONIC_REG_ISR 0x05 /* Interrupt status */ |
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| 35 | #define SONIC_REG_UTDA 0x06 /* Upper transmit descriptor address */ |
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| 36 | #define SONIC_REG_CTDA 0x07 /* Current transmit descriptor address */ |
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| 37 | #define SONIC_REG_URDA 0x0D /* Upper receive descriptor address */ |
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| 38 | #define SONIC_REG_CRDA 0x0E /* Current receive descriptor address */ |
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| 39 | #define SONIC_REG_EOBC 0x13 /* End of buffer word count */ |
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| 40 | #define SONIC_REG_URRA 0x14 /* Upper receive resource */ |
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| 41 | #define SONIC_REG_RSA 0x15 /* Resource start address */ |
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| 42 | #define SONIC_REG_REA 0x16 /* Resource end address */ |
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| 43 | #define SONIC_REG_RRP 0x17 /* Resouce read pointer */ |
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| 44 | #define SONIC_REG_RWP 0x18 /* Resouce write pointer */ |
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| 45 | #define SONIC_REG_CEP 0x21 /* CAM entry pointer */ |
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| 46 | #define SONIC_REG_CAP2 0x22 /* CAM address port 2 */ |
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| 47 | #define SONIC_REG_CAP1 0x23 /* CAM address port 1 */ |
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| 48 | #define SONIC_REG_CAP0 0x24 /* CAM address port 0 */ |
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| 49 | #define SONIC_REG_CE 0x25 /* CAM enable */ |
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| 50 | #define SONIC_REG_CDP 0x26 /* CAM descriptor pointer */ |
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| 51 | #define SONIC_REG_CDC 0x27 /* CAM descriptor count */ |
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| 52 | #define SONIC_REG_SR 0x28 /* Silicon revision */ |
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| 53 | #define SONIC_REG_WT0 0x29 /* Watchdog timer 0 */ |
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| 54 | #define SONIC_REG_WT1 0x2A /* Watchdog timer 1 */ |
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| 55 | #define SONIC_REG_RSC 0x2B /* Receive sequence counter */ |
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| 56 | #define SONIC_REG_CRCT 0x2C /* CRC error tally */ |
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| 57 | #define SONIC_REG_FAET 0x2D /* FAE tally */ |
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| 58 | #define SONIC_REG_MPT 0x2E /* Missed packet tally */ |
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| 59 | #define SONIC_REG_MDT 0x2F /* TX Maximum Deferral */ |
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| 60 | #define SONIC_REG_DCR2 0x3F /* Data configuration 2 */ |
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| 61 | |
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| 62 | #if 0 |
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| 63 | struct SonicRegisters { |
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| 64 | /* |
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| 65 | * Command and status registers |
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| 66 | */ |
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| 67 | rtems_unsigned32 cr; /* 0x00 - Command */ |
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| 68 | rtems_unsigned32 dcr; /* 0x01 - Data configuration */ |
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| 69 | rtems_unsigned32 rcr; /* 0x02 - Receive control */ |
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| 70 | rtems_unsigned32 tcr; /* 0x03 - Transmit control */ |
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| 71 | rtems_unsigned32 imr; /* 0x04 - Interrupt mask */ |
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| 72 | rtems_unsigned32 isr; /* 0x05 - Interrupt status */ |
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| 73 | |
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| 74 | /* |
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| 75 | * Transmit registers |
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| 76 | */ |
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| 77 | rtems_unsigned32 utda; /* 0x06 - Upper transmit descriptor address */ |
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| 78 | rtems_unsigned32 ctda; /* 0x07 - Current transmit descriptor address */ |
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| 79 | |
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| 80 | /* |
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| 81 | * Receive registers |
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| 82 | */ |
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| 83 | rtems_unsigned32 pad0[5]; /* 0x08 - 0x0C */ |
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| 84 | rtems_unsigned32 urda; /* 0x0D - Upper receive descriptor address */ |
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| 85 | rtems_unsigned32 crda; /* 0x0E - Current receive descriptor address */ |
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| 86 | rtems_unsigned32 pad1[4]; /* 0x0F - 0x12 */ |
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| 87 | rtems_unsigned32 eobc; /* 0x13 - End of buffer word count */ |
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| 88 | rtems_unsigned32 urra; /* 0x14 - Upper receive resource */ |
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| 89 | rtems_unsigned32 rsa; /* 0x15 - Resource start address */ |
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| 90 | rtems_unsigned32 rea; /* 0x16 - Resource end address */ |
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| 91 | rtems_unsigned32 rrp; /* 0x17 - Resouce read pointer */ |
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| 92 | rtems_unsigned32 rwp; /* 0x18 - Resouce write pointer */ |
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| 93 | |
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| 94 | /* |
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| 95 | * Content-addressable memory registers |
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| 96 | */ |
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| 97 | rtems_unsigned32 pad2[8]; /* 0x19 - 0x20 */ |
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| 98 | rtems_unsigned32 cep; /* 0x21 - CAM entry pointer */ |
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| 99 | rtems_unsigned32 cap2; /* 0x22 - CAM address port 2 */ |
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| 100 | rtems_unsigned32 cap1; /* 0x23 - CAM address port 1 */ |
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| 101 | rtems_unsigned32 cap0; /* 0x24 - CAM address port 0 */ |
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| 102 | rtems_unsigned32 ce; /* 0x25 - CAM enable */ |
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| 103 | rtems_unsigned32 cdp; /* 0x26 - CAM descriptor pointer */ |
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| 104 | rtems_unsigned32 cdc; /* 0x27 - CAM descriptor count */ |
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| 105 | |
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| 106 | /* |
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| 107 | * Silicon revision |
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| 108 | */ |
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| 109 | rtems_unsigned32 sr; /* 0x28 - Silicon revision */ |
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| 110 | |
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| 111 | /* |
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| 112 | * Watchdog counters |
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| 113 | */ |
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| 114 | rtems_unsigned32 wt0; /* 0x29 - Watchdog timer 0 */ |
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| 115 | rtems_unsigned32 wt1; /* 0x2A - Watchdog timer 1 */ |
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| 116 | |
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| 117 | /* |
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| 118 | * Another receive register |
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| 119 | */ |
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| 120 | rtems_unsigned32 rsc; /* 0x2B - Receive sequence counter */ |
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| 121 | |
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| 122 | /* |
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| 123 | * Tally counters |
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| 124 | */ |
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| 125 | rtems_unsigned32 crct; /* 0x2C - CRC error tally */ |
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| 126 | rtems_unsigned32 faet; /* 0x2D - FAE tally */ |
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| 127 | rtems_unsigned32 mpt; /* 0x2E - Missed packet tally */ |
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| 128 | |
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| 129 | /* |
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| 130 | * Another Transmitter register |
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| 131 | */ |
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| 132 | rtems_unsigned32 mdt; /* 0x2F - TX Maximum Deferral */ |
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| 133 | |
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| 134 | /* |
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| 135 | * Another command and status register |
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| 136 | */ |
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| 137 | rtems_unsigned32 pad3[15]; /* 0x30 - 0x3E */ |
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| 138 | rtems_unsigned32 dcr2; /* 0x3F - Data configuration 2 */ |
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| 139 | }; |
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| 140 | #endif |
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| 141 | |
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| 142 | /* |
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| 143 | * Command register |
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| 144 | */ |
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| 145 | #define CR_LCAM 0x0200 |
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| 146 | #define CR_RRRA 0x0100 |
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| 147 | #define CR_RST 0x0080 |
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| 148 | #define CR_ST 0x0020 |
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| 149 | #define CR_STP 0x0010 |
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| 150 | #define CR_RXEN 0x0008 |
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| 151 | #define CR_RXDIS 0x0004 |
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| 152 | #define CR_TXP 0x0002 |
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| 153 | #define CR_HTX 0x0001 |
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| 154 | |
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| 155 | /* |
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| 156 | * Data configuration register |
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| 157 | */ |
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| 158 | #define DCR_EXBUS 0x8000 |
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| 159 | #define DCR_LBR 0x2000 |
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| 160 | #define DCR_PO1 0x1000 |
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| 161 | #define DCR_PO0 0x0800 |
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| 162 | #define DCR_SBUS 0x0400 |
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| 163 | #define DCR_USR1 0x0200 |
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| 164 | #define DCR_USR0 0x0100 |
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| 165 | #define DCR_WC1 0x0080 |
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| 166 | #define DCR_WC0 0x0040 |
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| 167 | #define DCR_DW 0x0020 |
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| 168 | #define DCR_BMS 0x0010 |
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| 169 | #define DCR_RFT1 0x0008 |
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| 170 | #define DCR_RFT0 0x0004 |
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| 171 | #define DCR_TFT1 0x0002 |
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| 172 | #define DCR_TFT0 0x0001 |
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| 173 | |
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| 174 | /* |
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| 175 | * Receive control register |
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| 176 | */ |
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| 177 | #define RCR_ERR 0x8000 |
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| 178 | #define RCR_RNT 0x4000 |
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| 179 | #define RCR_BRD 0x2000 |
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| 180 | #define RCR_PRO 0x1000 |
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| 181 | #define RCR_AMC 0x0800 |
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| 182 | #define RCR_LB1 0x0400 |
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| 183 | #define RCR_LB0 0x0200 |
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| 184 | #define RCR_MC 0x0100 |
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| 185 | #define RCR_BC 0x0080 |
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| 186 | #define RCR_LPKT 0x0040 |
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| 187 | #define RCR_CRS 0x0020 |
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| 188 | #define RCR_COL 0x0010 |
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| 189 | #define RCR_CRCR 0x0008 |
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| 190 | #define RCR_FAER 0x0004 |
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| 191 | #define RCR_LBK 0x0002 |
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| 192 | #define RCR_PRX 0x0001 |
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| 193 | |
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| 194 | /* |
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| 195 | * Transmit control register |
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| 196 | */ |
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| 197 | #define TCR_PINT 0x8000 |
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| 198 | #define TCR_POWC 0x4000 |
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| 199 | #define TCR_CRCI 0x2000 |
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| 200 | #define TCR_EXDIS 0x1000 |
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| 201 | #define TCR_EXD 0x0400 |
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| 202 | #define TCR_DEF 0x0200 |
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| 203 | #define TCR_NCRS 0x0100 |
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| 204 | #define TCR_CRSL 0x0080 |
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| 205 | #define TCR_EXC 0x0040 |
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| 206 | #define TCR_OWC 0x0020 |
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| 207 | #define TCR_PMB 0x0008 |
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| 208 | #define TCR_FU 0x0004 |
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| 209 | #define TCR_BCM 0x0002 |
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| 210 | #define TCR_PTX 0x0001 |
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| 211 | |
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| 212 | /* |
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| 213 | * Interrupt mask register |
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| 214 | */ |
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| 215 | #define IMR_BREN 0x4000 |
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| 216 | #define IMR_HBLEN 0x2000 |
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| 217 | #define IMR_LCDEN 0x1000 |
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| 218 | #define IMR_PINTEN 0x0800 |
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| 219 | #define IMR_PRXEN 0x0400 |
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| 220 | #define IMR_PTXEN 0x0200 |
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| 221 | #define IMR_TXEREN 0x0100 |
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| 222 | #define IMR_TCEN 0x0080 |
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| 223 | #define IMR_RDEEN 0x0040 |
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| 224 | #define IMR_RBEEN 0x0020 |
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| 225 | #define IMR_RBAEEN 0x0010 |
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| 226 | #define IMR_CRCEN 0x0008 |
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| 227 | #define IMR_FAEEN 0x0004 |
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| 228 | #define IMR_MPEN 0x0002 |
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| 229 | #define IMR_RFOEN 0x0001 |
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| 230 | |
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| 231 | /* |
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| 232 | * Interrupt status register |
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| 233 | */ |
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| 234 | #define ISR_BR 0x4000 |
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| 235 | #define ISR_HBL 0x2000 |
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| 236 | #define ISR_LCD 0x1000 |
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| 237 | #define ISR_PINT 0x0800 |
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| 238 | #define ISR_PKTRX 0x0400 |
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| 239 | #define ISR_TXDN 0x0200 |
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| 240 | #define ISR_TXER 0x0100 |
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| 241 | #define ISR_TC 0x0080 |
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| 242 | #define ISR_RDE 0x0040 |
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| 243 | #define ISR_RBE 0x0020 |
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| 244 | #define ISR_RBAE 0x0010 |
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| 245 | #define ISR_CRC 0x0008 |
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| 246 | #define ISR_FAE 0x0004 |
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| 247 | #define ISR_MP 0x0002 |
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| 248 | #define ISR_RFO 0x0001 |
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| 249 | |
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| 250 | /* |
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| 251 | * Data configuration register 2 |
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| 252 | */ |
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| 253 | #define DCR2_EXPO3 0x8000 |
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| 254 | #define DCR2_EXPO2 0x4000 |
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| 255 | #define DCR2_EXPO1 0x2000 |
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| 256 | #define DCR2_EXPO0 0x1000 |
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| 257 | #define DCR2_PH 0x0010 |
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| 258 | #define DCR2_PCM 0x0004 |
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| 259 | #define DCR2_PCNM 0x0002 |
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| 260 | #define DCR2_RJCM 0x0001 |
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| 261 | |
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| 262 | /* |
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| 263 | ****************************************************************** |
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| 264 | * * |
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| 265 | * Transmit Buffer Management * |
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| 266 | * * |
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| 267 | ****************************************************************** |
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| 268 | */ |
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| 269 | |
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| 270 | /* |
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| 271 | * Transmit descriptor area entry. |
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| 272 | * There is one transmit descriptor for each packet to be transmitted. |
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| 273 | * Statically reserve space for up to MAXIMUM_FRAGS_PER_PACKET fragments |
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| 274 | * per descriptor. |
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| 275 | */ |
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| 276 | #define MAXIMUM_FRAGS_PER_DESCRIPTOR 6 |
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| 277 | struct TransmitDescriptor { |
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| 278 | rtems_unsigned32 status; |
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| 279 | rtems_unsigned32 pkt_config; |
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| 280 | rtems_unsigned32 pkt_size; |
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| 281 | rtems_unsigned32 frag_count; |
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| 282 | |
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| 283 | /* |
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| 284 | * Packet fragment pointers |
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| 285 | */ |
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| 286 | struct TransmitDescriptorFragLink { |
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| 287 | rtems_unsigned32 frag_lsw; /* LSW of fragment address */ |
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| 288 | #define frag_link frag_lsw |
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| 289 | rtems_unsigned32 frag_msw; /* MSW of fragment address */ |
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| 290 | rtems_unsigned32 frag_size; |
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| 291 | } frag[MAXIMUM_FRAGS_PER_DESCRIPTOR]; |
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| 292 | |
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| 293 | /* |
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| 294 | * Space for link if all fragment pointers are used. |
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| 295 | */ |
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| 296 | rtems_unsigned32 link_pad; |
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| 297 | |
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| 298 | /* |
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| 299 | * Extra RTEMS/KA9Q stuff |
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| 300 | */ |
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| 301 | struct TransmitDescriptor *next; /* Circularly-linked list */ |
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| 302 | struct mbuf *mbufp; /* First mbuf in packet */ |
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| 303 | volatile rtems_unsigned32 *linkp; /* Pointer to un[xxx].link */ |
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| 304 | }; |
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| 305 | typedef struct TransmitDescriptor TransmitDescriptor_t; |
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| 306 | typedef volatile TransmitDescriptor_t *TransmitDescriptorPointer_t; |
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| 307 | |
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| 308 | /* |
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| 309 | * Transmit Configuration. |
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| 310 | * For standard Ethernet transmission, all bits in the transmit |
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| 311 | * configuration field are set to 0. |
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| 312 | */ |
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| 313 | #define TDA_CONFIG_PINT 0x8000 |
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| 314 | #define TDA_CONFIG_POWC 0x4000 |
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| 315 | #define TDA_CONFIG_CRCI 0x2000 |
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| 316 | #define TDA_CONFIG_EXDIS 0x1000 |
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| 317 | |
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| 318 | /* |
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| 319 | * Transmit status |
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| 320 | */ |
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| 321 | #define TDA_STATUS_COLLISION_MASK 0xF800 |
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| 322 | #define TDA_STATUS_COLLISION_SHIFT 11 |
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| 323 | #define TDA_STATUS_EXD 0x0400 |
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| 324 | #define TDA_STATUS_DEF 0x0200 |
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| 325 | #define TDA_STATUS_NCRS 0x0100 |
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| 326 | #define TDA_STATUS_CRSL 0x0080 |
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| 327 | #define TDA_STATUS_EXC 0x0040 |
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| 328 | #define TDA_STATUS_OWC 0x0020 |
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| 329 | #define TDA_STATUS_PMB 0x0008 |
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| 330 | #define TDA_STATUS_FU 0x0004 |
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| 331 | #define TDA_STATUS_BCM 0x0002 |
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| 332 | #define TDA_STATUS_PTX 0x0001 |
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| 333 | |
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| 334 | #define TDA_LINK_EOL 0x1 |
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| 335 | |
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| 336 | |
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| 337 | |
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| 338 | /* |
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| 339 | ****************************************************************** |
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| 340 | * * |
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| 341 | * Receive Buffer Management * |
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| 342 | * * |
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| 343 | ****************************************************************** |
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| 344 | */ |
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| 345 | |
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| 346 | /* |
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| 347 | * Receive resource area entry. |
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| 348 | * There is one receive resource entry for each receive buffer area (RBA). |
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| 349 | * This driver allows only one packet per receive buffer area, so one |
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| 350 | * receive resource entry corresponds to one correctly-received packet. |
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| 351 | */ |
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| 352 | struct ReceiveResource { |
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| 353 | rtems_unsigned32 buff_ptr_lsw; /* LSW of RBA address */ |
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| 354 | rtems_unsigned32 buff_ptr_msw; /* MSW of RBA address */ |
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| 355 | rtems_unsigned32 buff_wc_lsw; /* LSW of RBA size (16-bit words) */ |
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| 356 | rtems_unsigned32 buff_wc_msw; /* MSW of RBA size (16-bit words) */ |
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| 357 | }; |
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| 358 | typedef struct ReceiveResource ReceiveResource_t; |
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| 359 | typedef volatile ReceiveResource_t *ReceiveResourcePointer_t; |
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| 360 | |
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| 361 | /* |
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| 362 | * Receive descriptor area entry. |
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| 363 | * There is one receive descriptor for each packet received. |
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| 364 | */ |
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| 365 | struct ReceiveDescriptor { |
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| 366 | rtems_unsigned32 status; |
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| 367 | rtems_unsigned32 byte_count; |
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| 368 | rtems_unsigned32 pkt_lsw; /* LSW of packet address */ |
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| 369 | rtems_unsigned32 pkt_msw; /* MSW of packet address */ |
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| 370 | rtems_unsigned32 seq_no; |
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| 371 | rtems_unsigned32 link; |
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| 372 | rtems_unsigned32 in_use; |
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| 373 | |
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| 374 | /* |
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| 375 | * Extra RTEMS/KA9Q stuff |
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| 376 | */ |
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| 377 | struct ReceiveDescriptor *next; /* Circularly-linked list */ |
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| 378 | }; |
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| 379 | typedef struct ReceiveDescriptor ReceiveDescriptor_t; |
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| 380 | typedef volatile ReceiveDescriptor_t *ReceiveDescriptorPointer_t; |
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| 381 | |
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| 382 | /* |
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| 383 | * Receive status |
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| 384 | */ |
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| 385 | #define RDA_STATUS_ERR 0x8800 |
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| 386 | #define RDA_STATUS_RNT 0x4000 |
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| 387 | #define RDA_STATUS_BRD 0x2000 |
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| 388 | #define RDA_STATUS_PRO 0x1000 |
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| 389 | #define RDA_STATUS_AMC 0x0800 |
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| 390 | #define RDA_STATUS_LB1 0x0400 |
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| 391 | #define RDA_STATUS_LB0 0x0200 |
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| 392 | #define RDA_STATUS_MC 0x0100 |
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| 393 | #define RDA_STATUS_BC 0x0080 |
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| 394 | #define RDA_STATUS_LPKT 0x0040 |
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| 395 | #define RDA_STATUS_CRS 0x0020 |
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| 396 | #define RDA_STATUS_COL 0x0010 |
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| 397 | #define RDA_STATUS_CRCR 0x0008 |
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| 398 | #define RDA_STATUS_FAER 0x0004 |
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| 399 | #define RDA_STATUS_LBK 0x0002 |
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| 400 | #define RDA_STATUS_PRX 0x0001 |
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| 401 | |
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| 402 | #define RDA_LINK_EOL 0x1 |
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| 403 | |
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| 404 | #endif /* _SONIC_DP83932_ */ |
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