source: rtems/c/src/lib/libbsp/powerpc/dmv177/sonic/sonic.h @ 14faf00

4.104.114.84.9
Last change on this file since 14faf00 was 14faf00, checked in by Joel Sherrill <joel.sherrill@…>, on Feb 2, 1999 at 4:27:37 PM

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1/*
2 ******************************************************************.
3 *******************************************************************
4 **                                                               **
5 **           DECLARATIONS FOR NATIONAL DP83932 `SONIC'           **
6 **         SYSTEMS-ORIENTED NETWORK INTERFACE CONTROLLER         **
7 **                                                               **
8 *******************************************************************
9 *******************************************************************
10 */
11
12/*
13 * $Revision$   $Date$   $Author$
14 * $State$
15 * $Id$
16 */
17
18#ifndef _SONIC_DP83932_
19#define _SONIC_DP83932_
20
21#include <bsp.h>
22
23/*
24 ******************************************************************
25 *                                                                *
26 *                        Device Registers                        *
27 *                                                                *
28 ******************************************************************
29 */
30#define SONIC_REG_CR      0x00 /* Command */
31#define SONIC_REG_DCR     0x01 /* Data configuration */
32#define SONIC_REG_RCR     0x02 /* Receive control */
33#define SONIC_REG_TCR     0x03 /* Transmit control */
34#define SONIC_REG_IMR     0x04 /* Interrupt mask */
35#define SONIC_REG_ISR     0x05 /* Interrupt status */
36#define SONIC_REG_UTDA    0x06 /* Upper transmit descriptor address */
37#define SONIC_REG_CTDA    0x07 /* Current transmit descriptor address */
38#define SONIC_REG_URDA    0x0D /* Upper receive descriptor address */
39#define SONIC_REG_CRDA    0x0E /* Current receive descriptor address */
40#define SONIC_REG_EOBC    0x13 /* End of buffer word count */
41#define SONIC_REG_URRA    0x14 /* Upper receive resource */
42#define SONIC_REG_RSA     0x15 /* Resource start address */
43#define SONIC_REG_REA     0x16 /* Resource end address */
44#define SONIC_REG_RRP     0x17 /* Resouce read pointer */
45#define SONIC_REG_RWP     0x18 /* Resouce write pointer */
46#define SONIC_REG_CEP     0x21 /* CAM entry pointer */
47#define SONIC_REG_CAP2    0x22 /* CAM address port 2 */
48#define SONIC_REG_CAP1    0x23 /* CAM address port 1 */
49#define SONIC_REG_CAP0    0x24 /* CAM address port 0 */
50#define SONIC_REG_CE      0x25 /* CAM enable */
51#define SONIC_REG_CDP     0x26 /* CAM descriptor pointer */
52#define SONIC_REG_CDC     0x27 /* CAM descriptor count */
53#define SONIC_REG_SR      0x28 /* Silicon revision */
54#define SONIC_REG_WT0     0x29 /* Watchdog timer 0 */
55#define SONIC_REG_WT1     0x2A /* Watchdog timer 1 */
56#define SONIC_REG_RSC     0x2B /* Receive sequence counter */
57#define SONIC_REG_CRCT    0x2C /* CRC error tally */
58#define SONIC_REG_FAET    0x2D /* FAE tally */
59#define SONIC_REG_MPT     0x2E /* Missed packet tally */
60#define SONIC_REG_MDT     0x2F /* TX Maximum Deferral */
61#define SONIC_REG_DCR2    0x3F /* Data configuration 2 */
62
63/*
64 * Command register
65 */
66#define CR_LCAM         0x0200
67#define CR_RRRA         0x0100
68#define CR_RST          0x0080
69#define CR_ST           0x0020
70#define CR_STP          0x0010
71#define CR_RXEN         0x0008
72#define CR_RXDIS        0x0004
73#define CR_TXP          0x0002
74#define CR_HTX          0x0001
75
76/*
77 * Data configuration register
78 */
79#define DCR_EXBUS       0x8000
80#define DCR_LBR         0x2000
81#define DCR_PO1         0x1000
82#define DCR_PO0         0x0800
83#define DCR_SBUS        0x0400
84#define DCR_USR1        0x0200
85#define DCR_USR0        0x0100
86#define DCR_WC1         0x0080
87#define DCR_WC0         0x0040
88#define DCR_DW          0x0020
89#define DCR_BMS         0x0010
90#define DCR_RFT1        0x0008
91#define DCR_RFT0        0x0004
92#define DCR_TFT1        0x0002
93#define DCR_TFT0        0x0001
94
95/* data configuration register aliases */
96#define DCR_SYNC        DCR_SBUS  /* synchronous (memory cycle 2 clocks) */
97#define DCR_ASYNC       0         /* asynchronous (memory cycle 3 clocks) */
98
99#define DCR_WAIT0       0                 /* 0 wait states added */
100#define DCR_WAIT1       DCR_WC0           /* 1 wait state added */
101#define DCR_WAIT2       DCR_WC1           /* 2 wait states added */
102#define DCR_WAIT3       (DCR_WC1|DCR_WC0) /* 3 wait states added */
103
104#define DCR_DW16        0       /* use 16-bit DMA accesses */
105#define DCR_DW32        DCR_DW  /* use 32-bit DMA accesses */
106
107#define DCR_DMAEF       0       /* DMA until TX/RX FIFO has emptied/filled */
108#define DCR_DMABLOCK    DCR_BMS /* DMA until RX/TX threshold crossed */
109
110#define DCR_RFT4        0               /* receive threshold 4 bytes */
111#define DCR_RFT8        DCR_RFT0        /* receive threshold 8 bytes */
112#define DCR_RFT16       DCR_RFT1        /* receive threshold 16 bytes */
113#define DCR_RFT24       (DCR_RFT1|DCR_RFT0) /* receive threshold 24 bytes */
114
115#define DCR_TFT8        0               /* transmit threshold 8 bytes */
116#define DCR_TFT16       DCR_TFT0        /* transmit threshold 16 bytes */
117#define DCR_TFT24       DCR_TFT1        /* transmit threshold 24 bytes */
118#define DCR_TFT28       (DCR_TFT1|DCR_TFT0) /* transmit threshold 28 bytes */
119
120/*
121 * Receive control register
122 */
123#define RCR_ERR         0x8000
124#define RCR_RNT         0x4000
125#define RCR_BRD         0x2000
126#define RCR_PRO         0x1000
127#define RCR_AMC         0x0800
128#define RCR_LB1         0x0400
129#define RCR_LB0         0x0200
130#define RCR_MC          0x0100
131#define RCR_BC          0x0080
132#define RCR_LPKT        0x0040
133#define RCR_CRS         0x0020
134#define RCR_COL         0x0010
135#define RCR_CRCR        0x0008
136#define RCR_FAER        0x0004
137#define RCR_LBK         0x0002
138#define RCR_PRX         0x0001
139
140/*
141 * Transmit control register
142 */
143#define TCR_PINT        0x8000
144#define TCR_POWC        0x4000
145#define TCR_CRCI        0x2000
146#define TCR_EXDIS       0x1000
147#define TCR_EXD         0x0400
148#define TCR_DEF         0x0200
149#define TCR_NCRS        0x0100
150#define TCR_CRSL        0x0080
151#define TCR_EXC         0x0040
152#define TCR_OWC         0x0020
153#define TCR_PMB         0x0008
154#define TCR_FU          0x0004
155#define TCR_BCM         0x0002
156#define TCR_PTX         0x0001
157
158/*
159 * Interrupt mask register
160 */
161#define IMR_BREN        0x4000
162#define IMR_HBLEN       0x2000
163#define IMR_LCDEN       0x1000
164#define IMR_PINTEN      0x0800
165#define IMR_PRXEN       0x0400
166#define IMR_PTXEN       0x0200
167#define IMR_TXEREN      0x0100
168#define IMR_TCEN        0x0080
169#define IMR_RDEEN       0x0040
170#define IMR_RBEEN       0x0020
171#define IMR_RBAEEN      0x0010
172#define IMR_CRCEN       0x0008
173#define IMR_FAEEN       0x0004
174#define IMR_MPEN        0x0002
175#define IMR_RFOEN       0x0001
176
177/*
178 * Interrupt status register
179 */
180#define ISR_BR          0x4000
181#define ISR_HBL         0x2000
182#define ISR_LCD         0x1000
183#define ISR_PINT        0x0800
184#define ISR_PKTRX       0x0400
185#define ISR_TXDN        0x0200
186#define ISR_TXER        0x0100
187#define ISR_TC          0x0080
188#define ISR_RDE         0x0040
189#define ISR_RBE         0x0020
190#define ISR_RBAE        0x0010
191#define ISR_CRC         0x0008
192#define ISR_FAE         0x0004
193#define ISR_MP          0x0002
194#define ISR_RFO         0x0001
195
196/*
197 * Data configuration register 2
198 */
199#define DCR2_EXPO3      0x8000
200#define DCR2_EXPO2      0x4000
201#define DCR2_EXPO1      0x2000
202#define DCR2_EXPO0      0x1000
203#define DCR2_PH         0x0010
204#define DCR2_PCM        0x0004
205#define DCR2_PCNM       0x0002
206#define DCR2_RJCM       0x0001
207
208/*
209 *  Known values for the Silicon Revision Register
210 */
211
212#define SONIC_REVISION_B   4
213#define SONIC_REVISION_C   6
214
215/*
216 ******************************************************************
217 *                                                                *
218 *                   Transmit Buffer Management                   *
219 *                                                                *
220 ******************************************************************
221 */
222
223/*
224 * Transmit descriptor area entry.
225 * There is one transmit descriptor for each packet to be transmitted.
226 * Statically reserve space for up to MAXIMUM_FRAGS_PER_PACKET fragments
227 * per descriptor.
228 */
229#define MAXIMUM_FRAGS_PER_DESCRIPTOR    6
230struct TransmitDescriptor {
231  rtems_unsigned32        status;
232  rtems_unsigned32        pkt_config;
233  rtems_unsigned32        pkt_size;
234  rtems_unsigned32        frag_count;
235
236  /*
237   * Packet fragment pointers
238   */
239  struct TransmitDescriptorFragLink {
240      rtems_unsigned32 frag_lsw;  /* LSW of fragment address */
241#define                      frag_link frag_lsw
242      rtems_unsigned32 frag_msw;  /* MSW of fragment address */
243      rtems_unsigned32 frag_size;
244  }                       frag[MAXIMUM_FRAGS_PER_DESCRIPTOR];
245
246  /*
247   * Space for link if all fragment pointers are used.
248   */
249  rtems_unsigned32        link_pad;
250
251  /*
252   * Extra RTEMS stuff
253   */
254  struct TransmitDescriptor       *next;  /* Circularly-linked list */
255  struct mbuf                     *mbufp; /* First mbuf in packet */
256  volatile rtems_unsigned32       *linkp; /* Pointer to un[xxx].link */
257};
258typedef struct TransmitDescriptor TransmitDescriptor_t;
259typedef volatile TransmitDescriptor_t *TransmitDescriptorPointer_t;
260
261/*
262 * Transmit Configuration.
263 * For standard Ethernet transmission, all bits in the transmit
264 * configuration field are set to 0.
265 */
266#define TDA_CONFIG_PINT 0x8000
267#define TDA_CONFIG_POWC 0x4000
268#define TDA_CONFIG_CRCI 0x2000
269#define TDA_CONFIG_EXDIS        0x1000
270
271/*
272 * Transmit status
273 */
274#define TDA_STATUS_COLLISION_MASK       0xF800
275#define TDA_STATUS_COLLISION_SHIFT      11
276#define TDA_STATUS_EXD          0x0400
277#define TDA_STATUS_DEF          0x0200
278#define TDA_STATUS_NCRS         0x0100
279#define TDA_STATUS_CRSL         0x0080
280#define TDA_STATUS_EXC          0x0040
281#define TDA_STATUS_OWC          0x0020
282#define TDA_STATUS_PMB          0x0008
283#define TDA_STATUS_FU           0x0004
284#define TDA_STATUS_BCM          0x0002
285#define TDA_STATUS_PTX          0x0001
286
287#define TDA_LINK_EOL      0x0001
288#define TDA_LINK_EOL_MASK 0xFFFE
289
290
291
292/*
293 ******************************************************************
294 *                                                                *
295 *                    Receive Buffer Management                   *
296 *                                                                *
297 ******************************************************************
298 */
299
300/*
301 * Receive resource area entry.
302 * There is one receive resource entry for each receive buffer area (RBA).
303 * This driver allows only one packet per receive buffer area, so one
304 * receive resource entry corresponds to one correctly-received packet.
305 */
306struct ReceiveResource {
307  rtems_unsigned32        buff_ptr_lsw;   /* LSW of RBA address */
308  rtems_unsigned32        buff_ptr_msw;   /* MSW of RBA address */
309  rtems_unsigned32        buff_wc_lsw;    /* LSW of RBA size (16-bit words) */
310  rtems_unsigned32        buff_wc_msw;    /* MSW of RBA size (16-bit words) */
311};
312typedef struct ReceiveResource ReceiveResource_t;
313typedef volatile ReceiveResource_t *ReceiveResourcePointer_t;
314
315/*
316 * Receive descriptor area entry.
317 * There is one receive descriptor for each packet received.
318 */
319struct ReceiveDescriptor {
320  rtems_unsigned32        status;
321  rtems_unsigned32        byte_count;
322  rtems_unsigned32        pkt_lsw;        /* LSW of packet address */
323  rtems_unsigned32        pkt_msw;        /* MSW of packet address */
324  rtems_unsigned32        seq_no;
325  rtems_unsigned32        link;
326  rtems_unsigned32        in_use;
327
328  /*
329   * Extra RTEMS stuff
330   */
331  volatile struct ReceiveDescriptor  *next;  /* Circularly-linked list */
332  struct mbuf                        *mbufp; /* First mbuf in packet */
333};
334typedef struct ReceiveDescriptor ReceiveDescriptor_t;
335typedef volatile ReceiveDescriptor_t *ReceiveDescriptorPointer_t;
336
337typedef struct {
338  rtems_unsigned32  cep;  /* CAM Entry Pointer */
339  rtems_unsigned32  cap0; /* CAM Address Port 0 xx-xx-xx-xx-YY-YY */
340  rtems_unsigned32  cap1; /* CAM Address Port 1 xx-xx-YY-YY-xxxx */
341  rtems_unsigned32  cap2; /* CAM Address Port 2 YY-YY-xx-xx-xx-xx */
342  rtems_unsigned32  ce;
343} CamDescriptor_t;
344
345typedef volatile CamDescriptor_t *CamDescriptorPointer_t;
346
347/*
348 * Receive status
349 */
350#define RDA_STATUS_ERR          0x8800
351#define RDA_STATUS_RNT          0x4000
352#define RDA_STATUS_BRD          0x2000
353#define RDA_STATUS_PRO          0x1000
354#define RDA_STATUS_AMC          0x0800
355#define RDA_STATUS_LB1          0x0400
356#define RDA_STATUS_LB0          0x0200
357#define RDA_STATUS_MC           0x0100
358#define RDA_STATUS_BC           0x0080
359#define RDA_STATUS_LPKT         0x0040
360#define RDA_STATUS_CRS          0x0020
361#define RDA_STATUS_COL          0x0010
362#define RDA_STATUS_CRCR         0x0008
363#define RDA_STATUS_FAER         0x0004
364#define RDA_STATUS_LBK          0x0002
365#define RDA_STATUS_PRX          0x0001
366
367#define RDA_LINK_EOL        0x0001
368#define RDA_LINK_EOL_MASK   0xFFFE
369#define RDA_IN_USE          0x0000  /* SONIC has finished with the packet */
370                                    /*   and the driver can process it */
371#define RDA_FREE            0xFFFF  /* SONIC can use it */
372 
373#endif /* _SONIC_DP83932_ */
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