source: rtems/c/src/lib/libbsp/powerpc/dmv177/sonic/sonic.h @ 1253f39

4.104.114.84.9
Last change on this file since 1253f39 was 7344fba9, checked in by Joel Sherrill <joel.sherrill@…>, on Aug 10, 1998 at 9:45:01 PM

Can now reply to multiple successive pings successfully without being in
promiscuous mode.

It still dies somewhere between 16 and 20 pings.

  • Property mode set to 100644
File size: 12.6 KB
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1/*
2 *******************************************************************
3 *******************************************************************
4 **                                                               **
5 **           DECLARATIONS FOR NATIONAL DP83932 `SONIC'           **
6 **         SYSTEMS-ORIENTED NETWORK INTERFACE CONTROLLER         **
7 **                                                               **
8 *******************************************************************
9 *******************************************************************
10 */
11
12/*
13 * $Revision$   $Date$   $Author$
14 * $State$
15 */
16
17#ifndef _SONIC_DP83932_
18#define _SONIC_DP83932_
19
20#include <bsp.h>
21
22/*
23 ******************************************************************
24 *                                                                *
25 *                        Device Registers                        *
26 *                                                                *
27 ******************************************************************
28 */
29#define SONIC_REG_CR      0x00 /* Command */
30#define SONIC_REG_DCR     0x01 /* Data configuration */
31#define SONIC_REG_RCR     0x02 /* Receive control */
32#define SONIC_REG_TCR     0x03 /* Transmit control */
33#define SONIC_REG_IMR     0x04 /* Interrupt mask */
34#define SONIC_REG_ISR     0x05 /* Interrupt status */
35#define SONIC_REG_UTDA    0x06 /* Upper transmit descriptor address */
36#define SONIC_REG_CTDA    0x07 /* Current transmit descriptor address */
37#define SONIC_REG_URDA    0x0D /* Upper receive descriptor address */
38#define SONIC_REG_CRDA    0x0E /* Current receive descriptor address */
39#define SONIC_REG_EOBC    0x13 /* End of buffer word count */
40#define SONIC_REG_URRA    0x14 /* Upper receive resource */
41#define SONIC_REG_RSA     0x15 /* Resource start address */
42#define SONIC_REG_REA     0x16 /* Resource end address */
43#define SONIC_REG_RRP     0x17 /* Resouce read pointer */
44#define SONIC_REG_RWP     0x18 /* Resouce write pointer */
45#define SONIC_REG_CEP     0x21 /* CAM entry pointer */
46#define SONIC_REG_CAP2    0x22 /* CAM address port 2 */
47#define SONIC_REG_CAP1    0x23 /* CAM address port 1 */
48#define SONIC_REG_CAP0    0x24 /* CAM address port 0 */
49#define SONIC_REG_CE      0x25 /* CAM enable */
50#define SONIC_REG_CDP     0x26 /* CAM descriptor pointer */
51#define SONIC_REG_CDC     0x27 /* CAM descriptor count */
52#define SONIC_REG_SR      0x28 /* Silicon revision */
53#define SONIC_REG_WT0     0x29 /* Watchdog timer 0 */
54#define SONIC_REG_WT1     0x2A /* Watchdog timer 1 */
55#define SONIC_REG_RSC     0x2B /* Receive sequence counter */
56#define SONIC_REG_CRCT    0x2C /* CRC error tally */
57#define SONIC_REG_FAET    0x2D /* FAE tally */
58#define SONIC_REG_MPT     0x2E /* Missed packet tally */
59#define SONIC_REG_MDT     0x2F /* TX Maximum Deferral */
60#define SONIC_REG_DCR2    0x3F /* Data configuration 2 */
61
62/*
63 * Command register
64 */
65#define CR_LCAM         0x0200
66#define CR_RRRA         0x0100
67#define CR_RST          0x0080
68#define CR_ST           0x0020
69#define CR_STP          0x0010
70#define CR_RXEN         0x0008
71#define CR_RXDIS        0x0004
72#define CR_TXP          0x0002
73#define CR_HTX          0x0001
74
75/*
76 * Data configuration register
77 */
78#define DCR_EXBUS       0x8000
79#define DCR_LBR         0x2000
80#define DCR_PO1         0x1000
81#define DCR_PO0         0x0800
82#define DCR_SBUS        0x0400
83#define DCR_USR1        0x0200
84#define DCR_USR0        0x0100
85#define DCR_WC1         0x0080
86#define DCR_WC0         0x0040
87#define DCR_DW          0x0020
88#define DCR_BMS         0x0010
89#define DCR_RFT1        0x0008
90#define DCR_RFT0        0x0004
91#define DCR_TFT1        0x0002
92#define DCR_TFT0        0x0001
93
94/* data configuration register aliases */
95#define DCR_SYNC        DCR_SBUS  /* synchronous (memory cycle 2 clocks) */
96#define DCR_ASYNC       0         /* asynchronous (memory cycle 3 clocks) */
97
98#define DCR_WAIT0       0                 /* 0 wait states added */
99#define DCR_WAIT1       DCR_WC0           /* 1 wait state added */
100#define DCR_WAIT2       DCR_WC1           /* 2 wait states added */
101#define DCR_WAIT3       (DCR_WC1|DCR_WC0) /* 3 wait states added */
102
103#define DCR_DW16        0       /* use 16-bit DMA accesses */
104#define DCR_DW32        DCR_DW  /* use 32-bit DMA accesses */
105
106#define DCR_DMAEF       0       /* DMA until TX/RX FIFO has emptied/filled */
107#define DCR_DMABLOCK    DCR_BMS /* DMA until RX/TX threshold crossed */
108
109#define DCR_RFT4        0               /* receive threshold 4 bytes */
110#define DCR_RFT8        DCR_RFT0        /* receive threshold 8 bytes */
111#define DCR_RFT16       DCR_RFT1        /* receive threshold 16 bytes */
112#define DCR_RFT24       (DCR_RFT1|DCR_RFT0) /* receive threshold 24 bytes */
113
114#define DCR_TFT8        0               /* transmit threshold 8 bytes */
115#define DCR_TFT16       DCR_TFT0        /* transmit threshold 16 bytes */
116#define DCR_TFT24       DCR_TFT1        /* transmit threshold 24 bytes */
117#define DCR_TFT28       (DCR_TFT1|DCR_TFT0) /* transmit threshold 28 bytes */
118
119/*
120 * Receive control register
121 */
122#define RCR_ERR         0x8000
123#define RCR_RNT         0x4000
124#define RCR_BRD         0x2000
125#define RCR_PRO         0x1000
126#define RCR_AMC         0x0800
127#define RCR_LB1         0x0400
128#define RCR_LB0         0x0200
129#define RCR_MC          0x0100
130#define RCR_BC          0x0080
131#define RCR_LPKT        0x0040
132#define RCR_CRS         0x0020
133#define RCR_COL         0x0010
134#define RCR_CRCR        0x0008
135#define RCR_FAER        0x0004
136#define RCR_LBK         0x0002
137#define RCR_PRX         0x0001
138
139/*
140 * Transmit control register
141 */
142#define TCR_PINT        0x8000
143#define TCR_POWC        0x4000
144#define TCR_CRCI        0x2000
145#define TCR_EXDIS       0x1000
146#define TCR_EXD         0x0400
147#define TCR_DEF         0x0200
148#define TCR_NCRS        0x0100
149#define TCR_CRSL        0x0080
150#define TCR_EXC         0x0040
151#define TCR_OWC         0x0020
152#define TCR_PMB         0x0008
153#define TCR_FU          0x0004
154#define TCR_BCM         0x0002
155#define TCR_PTX         0x0001
156
157/*
158 * Interrupt mask register
159 */
160#define IMR_BREN        0x4000
161#define IMR_HBLEN       0x2000
162#define IMR_LCDEN       0x1000
163#define IMR_PINTEN      0x0800
164#define IMR_PRXEN       0x0400
165#define IMR_PTXEN       0x0200
166#define IMR_TXEREN      0x0100
167#define IMR_TCEN        0x0080
168#define IMR_RDEEN       0x0040
169#define IMR_RBEEN       0x0020
170#define IMR_RBAEEN      0x0010
171#define IMR_CRCEN       0x0008
172#define IMR_FAEEN       0x0004
173#define IMR_MPEN        0x0002
174#define IMR_RFOEN       0x0001
175
176/*
177 * Interrupt status register
178 */
179#define ISR_BR          0x4000
180#define ISR_HBL         0x2000
181#define ISR_LCD         0x1000
182#define ISR_PINT        0x0800
183#define ISR_PKTRX       0x0400
184#define ISR_TXDN        0x0200
185#define ISR_TXER        0x0100
186#define ISR_TC          0x0080
187#define ISR_RDE         0x0040
188#define ISR_RBE         0x0020
189#define ISR_RBAE        0x0010
190#define ISR_CRC         0x0008
191#define ISR_FAE         0x0004
192#define ISR_MP          0x0002
193#define ISR_RFO         0x0001
194
195/*
196 * Data configuration register 2
197 */
198#define DCR2_EXPO3      0x8000
199#define DCR2_EXPO2      0x4000
200#define DCR2_EXPO1      0x2000
201#define DCR2_EXPO0      0x1000
202#define DCR2_PH         0x0010
203#define DCR2_PCM        0x0004
204#define DCR2_PCNM       0x0002
205#define DCR2_RJCM       0x0001
206
207/*
208 *  Known values for the Silicon Revision Register
209 */
210
211#define SONIC_REVISION_B   4
212#define SONIC_REVISION_C   6
213
214/*
215 ******************************************************************
216 *                                                                *
217 *                   Transmit Buffer Management                   *
218 *                                                                *
219 ******************************************************************
220 */
221
222/*
223 * Transmit descriptor area entry.
224 * There is one transmit descriptor for each packet to be transmitted.
225 * Statically reserve space for up to MAXIMUM_FRAGS_PER_PACKET fragments
226 * per descriptor.
227 */
228#define MAXIMUM_FRAGS_PER_DESCRIPTOR    6
229struct TransmitDescriptor {
230  rtems_unsigned32        status;
231  rtems_unsigned32        pkt_config;
232  rtems_unsigned32        pkt_size;
233  rtems_unsigned32        frag_count;
234
235  /*
236   * Packet fragment pointers
237   */
238  struct TransmitDescriptorFragLink {
239      rtems_unsigned32 frag_lsw;  /* LSW of fragment address */
240#define                      frag_link frag_lsw
241      rtems_unsigned32 frag_msw;  /* MSW of fragment address */
242      rtems_unsigned32 frag_size;
243  }                       frag[MAXIMUM_FRAGS_PER_DESCRIPTOR];
244
245  /*
246   * Space for link if all fragment pointers are used.
247   */
248  rtems_unsigned32        link_pad;
249
250  /*
251   * Extra RTEMS/KA9Q stuff
252   */
253  struct TransmitDescriptor       *next;  /* Circularly-linked list */
254  struct mbuf                     *mbufp; /* First mbuf in packet */
255  volatile rtems_unsigned32       *linkp; /* Pointer to un[xxx].link */
256};
257typedef struct TransmitDescriptor TransmitDescriptor_t;
258typedef volatile TransmitDescriptor_t *TransmitDescriptorPointer_t;
259
260/*
261 * Transmit Configuration.
262 * For standard Ethernet transmission, all bits in the transmit
263 * configuration field are set to 0.
264 */
265#define TDA_CONFIG_PINT 0x8000
266#define TDA_CONFIG_POWC 0x4000
267#define TDA_CONFIG_CRCI 0x2000
268#define TDA_CONFIG_EXDIS        0x1000
269
270/*
271 * Transmit status
272 */
273#define TDA_STATUS_COLLISION_MASK       0xF800
274#define TDA_STATUS_COLLISION_SHIFT      11
275#define TDA_STATUS_EXD          0x0400
276#define TDA_STATUS_DEF          0x0200
277#define TDA_STATUS_NCRS         0x0100
278#define TDA_STATUS_CRSL         0x0080
279#define TDA_STATUS_EXC          0x0040
280#define TDA_STATUS_OWC          0x0020
281#define TDA_STATUS_PMB          0x0008
282#define TDA_STATUS_FU           0x0004
283#define TDA_STATUS_BCM          0x0002
284#define TDA_STATUS_PTX          0x0001
285
286#define TDA_LINK_EOL      0x0001
287#define TDA_LINK_EOL_MASK 0xFFFE
288
289
290
291/*
292 ******************************************************************
293 *                                                                *
294 *                    Receive Buffer Management                   *
295 *                                                                *
296 ******************************************************************
297 */
298
299/*
300 * Receive resource area entry.
301 * There is one receive resource entry for each receive buffer area (RBA).
302 * This driver allows only one packet per receive buffer area, so one
303 * receive resource entry corresponds to one correctly-received packet.
304 */
305struct ReceiveResource {
306  rtems_unsigned32        buff_ptr_lsw;   /* LSW of RBA address */
307  rtems_unsigned32        buff_ptr_msw;   /* MSW of RBA address */
308  rtems_unsigned32        buff_wc_lsw;    /* LSW of RBA size (16-bit words) */
309  rtems_unsigned32        buff_wc_msw;    /* MSW of RBA size (16-bit words) */
310};
311typedef struct ReceiveResource ReceiveResource_t;
312typedef volatile ReceiveResource_t *ReceiveResourcePointer_t;
313
314/*
315 * Receive descriptor area entry.
316 * There is one receive descriptor for each packet received.
317 */
318struct ReceiveDescriptor {
319  rtems_unsigned32        status;
320  rtems_unsigned32        byte_count;
321  rtems_unsigned32        pkt_lsw;        /* LSW of packet address */
322  rtems_unsigned32        pkt_msw;        /* MSW of packet address */
323  rtems_unsigned32        seq_no;
324  rtems_unsigned32        link;
325  rtems_unsigned32        in_use;
326
327  /*
328   * Extra RTEMS/KA9Q stuff
329   */
330  volatile struct ReceiveDescriptor  *next;  /* Circularly-linked list */
331};
332typedef struct ReceiveDescriptor ReceiveDescriptor_t;
333typedef volatile ReceiveDescriptor_t *ReceiveDescriptorPointer_t;
334
335typedef struct {
336  rtems_unsigned32  cep;  /* CAM Entry Pointer */
337  rtems_unsigned32  cap0; /* CAM Address Port 0 xx-xx-xx-xx-YY-YY */
338  rtems_unsigned32  cap1; /* CAM Address Port 1 xx-xx-YY-YY-xxxx */
339  rtems_unsigned32  cap2; /* CAM Address Port 2 YY-YY-xx-xx-xx-xx */
340  rtems_unsigned32  ce;
341} CamDescriptor_t;
342
343typedef volatile CamDescriptor_t *CamDescriptorPointer_t;
344
345/*
346 * Receive status
347 */
348#define RDA_STATUS_ERR          0x8800
349#define RDA_STATUS_RNT          0x4000
350#define RDA_STATUS_BRD          0x2000
351#define RDA_STATUS_PRO          0x1000
352#define RDA_STATUS_AMC          0x0800
353#define RDA_STATUS_LB1          0x0400
354#define RDA_STATUS_LB0          0x0200
355#define RDA_STATUS_MC           0x0100
356#define RDA_STATUS_BC           0x0080
357#define RDA_STATUS_LPKT         0x0040
358#define RDA_STATUS_CRS          0x0020
359#define RDA_STATUS_COL          0x0010
360#define RDA_STATUS_CRCR         0x0008
361#define RDA_STATUS_FAER         0x0004
362#define RDA_STATUS_LBK          0x0002
363#define RDA_STATUS_PRX          0x0001
364
365#define RDA_LINK_EOL        0x0001
366#define RDA_LINK_EOL_MASK   0xFFFE
367#define RDA_IN_USE          0x0000  /* SONIC has finished with the packet */
368                                    /*   and the driver can process it */
369#define RDA_FREE            0xFFFF  /* SONIC can use it */
370 
371#endif /* _SONIC_DP83932_ */
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