source: rtems/c/src/lib/libbsp/powerpc/dmv177/sonic/sonic.c @ 3fbd528

4.104.114.84.9
Last change on this file since 3fbd528 was 3fbd528, checked in by Joel Sherrill <joel.sherrill@…>, on Aug 10, 1998 at 10:23:33 PM

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1void break_when_you_get_here();
2/*
3 *******************************************************************
4 *******************************************************************
5 **                                                               **
6 **         RTEMS/KA9Q DRIVER FOR NATIONAL DP83932 `SONIC'        **
7 **         SYSTEMS-ORIENTED NETWORK INTERFACE CONTROLLER         **
8 **                                                               **
9 *******************************************************************
10 *******************************************************************
11 */
12
13/*
14 * $Revision$   $Date$   $Author$
15 * $State$
16 */
17
18/*
19 * References:
20 * 1) DP83932C-20/25/33 MHz SONIC(TM) Systems-Oriented Network Interface
21 *    Controller data sheet.  TL/F/10492, RRD-B30M105, National Semiconductor,
22 *    1995.
23 *
24 * 2) Software Driver Programmer's Guide for the DP83932 SONIC(TM),
25 *    Application Note 746, Wesley Lee and Mike Lui, TL/F/11140,
26 *    RRD-B30M75, National Semiconductor, March, 1991.
27 *
28 * 3) SVME/DMV-171 Single Board Computer Documentation Package, #805905,
29 *    DY 4 Systems Inc., Kanata, Ontario, September, 1996.
30 */
31
32#include "sonic.h"
33
34#include <rtems/error.h>
35#include <ka9q/rtems_ka9q.h>
36#include <ka9q/global.h>
37#include <ka9q/domain.h>
38#include <ka9q/enet.h>
39#include <ka9q/iface.h>
40#include <ka9q/netuser.h>
41#include <ka9q/trace.h>
42#include <ka9q/commands.h>
43
44/*
45 * Debug levels
46 *
47 */
48
49#define SONIC_DEBUG_NONE             0x0000
50#define SONIC_DEBUG_ALL              0xFFFF
51#define SONIC_DEBUG_PRINT_REGISTERS  0x0001
52#define SONIC_DEBUG_MEMORY           0x0002
53#define SONIC_DEBUG_MEMORY_ALLOCATE  0x0004
54#define SONIC_DEBUG_FRAGMENTS        0x0008
55#define SONIC_DEBUG_CAM              0x0008
56
57#define SONIC_DEBUG      (SONIC_DEBUG_MEMORY|SONIC_DEBUG_CAM)
58/* SONIC_DEBUG_ALL */
59
60
61/*
62 * XXX
63 */
64
65#include <dmv170.h>
66
67/*
68 *  Use the top line if you want more symbols.
69 */
70
71#define SONIC_STATIC
72/* #define SONIC_STATIC static */
73
74/*
75 * Number of devices supported by this driver
76 */
77#ifndef NSONIC
78# define NSONIC 1
79#endif
80
81/*
82 * Default location of device registers
83 */
84#ifndef SONIC_BASE_ADDRESS
85# define SONIC_BASE_ADDRESS 0xF3000000
86# warning "Using default SONIC_BASE_ADDRESS."
87#endif
88
89/*
90 * Default interrupt vector
91 */
92#ifndef SONIC_VECTOR
93# define SONIC_VECTOR 1
94# warning "Using default SONIC_VECTOR."
95#endif
96
97/*
98 * Default device configuration register values
99 * Conservative, generic values.
100 * DCR:
101 *      No extended bus mode
102 *      Unlatched bus retry
103 *      Programmable outputs unused
104 *      Asynchronous bus mode
105 *      User definable pins unused
106 *      No wait states (access time controlled by DTACK*)
107 *      32-bit DMA
108 *      Empty/Fill DMA mode
109 *      Maximum Transmit/Receive FIFO
110 * DC2:
111 *      Extended programmable outputs unused
112 *      Normal HOLD request
113 *      Packet compress output unused
114 *      No reject on CAM match
115 */
116#define SONIC_DCR \
117   (DCR_DW32 | DCR_WAIT0 | DCR_PO0 | DCR_PO1  | DCR_RFT24 | DCR_TFT28)
118#ifndef SONIC_DCR
119# define SONIC_DCR (DCR_DW32 | DCR_TFT28)
120#endif
121#ifndef SONIC_DC2
122# define SONIC_DC2 (0)
123#endif
124
125/*
126 * Default sizes of transmit and receive descriptor areas
127 */
128#define RDA_COUNT     20
129#define TDA_COUNT     10
130
131/*
132 *
133 * As suggested by National Application Note 746, make the
134 * receive resource area bigger than the receive descriptor area.
135 */
136#define RRA_EXTRA_COUNT  3
137
138/*
139 * RTEMS event used by interrupt handler to signal daemons.
140 */
141#define INTERRUPT_EVENT  RTEMS_EVENT_1
142
143/*
144 * Largest Ethernet frame.
145 */
146#define MAXIMUM_FRAME_SIZE  1518
147
148/*
149 * Receive buffer size.
150 * Allow for a pointer, plus a full ethernet frame (including Frame
151 * Check Sequence) rounded up to a 4-byte boundary.
152 */
153#define RBUF_SIZE  ((sizeof (void *) + (MAXIMUM_FRAME_SIZE) + 3) & ~3)
154#define RBUF_WC    ((((MAXIMUM_FRAME_SIZE) + 3) & ~3) / 2)
155
156/*
157 * Macros for manipulating 32-bit pointers as 16-bit fragments
158 */
159#define LSW(p)   ((rtems_unsigned16)((rtems_unsigned32)(p)))
160#define MSW(p)   ((rtems_unsigned16)((rtems_unsigned32)(p) >> 16))
161#define PTR(m,l) ((void*)(((rtems_unsigned16)(m)<<16)|(rtems_unsigned16)(l)))
162
163/*
164 * Hardware-specific storage
165 */
166struct sonic {
167  /*
168   * Connection to KA9Q
169   */
170  struct iface                     *iface;
171
172  /*
173   * Default location of device registers
174   * ===CACHE===
175   * This area must be non-cacheable, guarded.
176   */
177  void                             *sonic;
178
179  /*
180   * Interrupt vector
181   */
182  rtems_vector_number             vector;
183
184  /*
185   * Task waiting for transmit resources
186   */
187  rtems_id                        txWaitTid;
188
189  /*
190   * Receive resource area
191   */
192  int                             rdaCount;
193  ReceiveResourcePointer_t        rsa;
194  CamDescriptorPointer_t          cdp;
195  ReceiveDescriptorPointer_t      rda;
196  ReceiveDescriptorPointer_t      rdp_last;
197
198  /*
199   * Transmit descriptors
200   */
201  int                             tdaCount;
202  TransmitDescriptorPointer_t     tdaHead;  /* Last filled */
203  TransmitDescriptorPointer_t     tdaTail;  /* Next to retire */
204  int                             tdaActiveCount;
205
206  /*
207   * Statistics
208   */
209  unsigned long                   Interrupts;
210  unsigned long                   rxInterrupts;
211  unsigned long                   rxMissed;
212  unsigned long                   rxGiant;
213  unsigned long                   rxNonOctet;
214  unsigned long                   rxBadCRC;
215  unsigned long                   rxCollision;
216
217  unsigned long                   txInterrupts;
218  unsigned long                   txSingleCollision;
219  unsigned long                   txMultipleCollision;
220  unsigned long                   txCollision;
221  unsigned long                   txDeferred;
222  unsigned long                   txUnderrun;
223  unsigned long                   txLateCollision;
224  unsigned long                   txExcessiveCollision;
225  unsigned long                   txExcessiveDeferral;
226  unsigned long                   txLostCarrier;
227  unsigned long                   txRawWait;
228};
229SONIC_STATIC struct sonic sonic[NSONIC];
230
231/*
232 ******************************************************************
233 *                                                                *
234 *                        Support Routines                        *
235 *                                                                *
236 ******************************************************************
237 */
238
239void sonic_write_register(
240  void       *base,
241  unsigned32  regno,
242  unsigned32  value
243);
244
245unsigned32 sonic_read_register(
246  void       *base,
247  unsigned32  regno
248);
249
250/*
251 * Allocate non-cacheable memory on a single 64k page.
252 * Very simple minded -- just keeps trying till the memory is on a single page.
253 */
254SONIC_STATIC void * sonic_allocate(unsigned int nbytes)
255{
256  void *p;
257  unsigned long a1, a2;
258
259  for (;;) {
260    /*
261     * ===CACHE===
262     * Change malloc to malloc_noncacheable_guarded.
263     */
264    p = calloc(1, nbytes);
265    if (p == NULL)
266      rtems_panic ("No memory!");
267    a1 = (unsigned long)p;
268    a2 = a1 + nbytes - 1;
269    if ((a1 >> 16) == (a2 >> 16))
270      break;
271  }
272#if (SONIC_DEBUG & SONIC_DEBUG_MEMORY_ALLOCATE)
273  printf( "sonic_allocate %d bytes at %p\n", nbytes, p );
274#endif
275  return p;
276}
277
278/*
279 * Shut down the interface.
280 * This is a pretty simple-minded routine.  It doesn't worry
281 * about cleaning up mbufs, shutting down daemons, etc.
282 */
283
284SONIC_STATIC int sonic_stop (struct iface *iface)
285{
286  int i;
287  struct sonic *dp = &sonic[iface->dev];
288  void *rp = dp->sonic;
289
290  /*
291   * Stop the transmitter and receiver.
292   */
293  sonic_write_register( rp, SONIC_REG_CR, CR_HTX | CR_RXDIS );
294
295  /*
296   * Wait for things to stop.
297   * For safety's sake, there is an alternate exit.
298   */
299  i = 0;
300  while (sonic_read_register( rp, SONIC_REG_CR ) & (CR_RXEN | CR_TXP)) {
301    if (++i == 10000)
302      break;
303  }
304
305  /*
306   * Reset the device
307   */
308  sonic_write_register( rp, SONIC_REG_CR, CR_RST );
309  sonic_write_register( rp, SONIC_REG_IMR, 0 );
310  return 0;
311}
312
313/*
314 * Show interface statistics
315 */
316
317SONIC_STATIC void sonic_show (struct iface *iface)
318{
319  struct sonic *dp = &sonic[iface->dev];
320
321  printf (" Total Interrupts:%-8lu", dp->Interrupts);
322  printf ("    Rx Interrupts:%-8lu", dp->rxInterrupts);
323  printf ("            Giant:%-8lu", dp->rxGiant);
324  printf ("        Non-octet:%-8lu\n", dp->rxNonOctet);
325  printf ("          Bad CRC:%-8lu", dp->rxBadCRC);
326  printf ("        Collision:%-8lu", dp->rxCollision);
327  printf ("           Missed:%-8lu\n", dp->rxMissed);
328
329  printf (    "    Tx Interrupts:%-8lu", dp->txInterrupts);
330  printf (  "           Deferred:%-8lu", dp->txDeferred);
331  printf ("        Lost Carrier:%-8lu\n", dp->txLostCarrier);
332  printf (   "Single Collisions:%-8lu", dp->txSingleCollision);
333  printf ( "Multiple Collisions:%-8lu", dp->txMultipleCollision);
334  printf ("Excessive Collisions:%-8lu\n", dp->txExcessiveCollision);
335  printf (   " Total Collisions:%-8lu", dp->txCollision);
336  printf ( "     Late Collision:%-8lu", dp->txLateCollision);
337  printf ("            Underrun:%-8lu\n", dp->txUnderrun);
338  printf (   "  Raw output wait:%-8lu\n", dp->txRawWait);
339}
340
341/*
342 ******************************************************************
343 *                                                                *
344 *                        Interrupt Handler                       *
345 *                                                                *
346 ******************************************************************
347 */
348
349SONIC_STATIC rtems_isr sonic_interrupt_handler (rtems_vector_number v)
350{
351  struct sonic *dp = sonic;
352  void *rp;
353
354#if (NSONIC > 1)
355  /*
356   * Find the device which requires service
357   */
358  for (;;) {
359    if (dp->vector == v)
360      break;
361    if (++dp == &sonic[NSONIC])
362      return;  /* Spurious interrupt? */
363  }
364#endif /* NSONIC > 1 */
365
366  /*
367   * Get pointer to SONIC registers
368   */
369  rp = dp->sonic;
370
371  dp->Interrupts++;
372
373  /*
374   * Packet received or receive buffer area exceeded?
375   */
376  if ((sonic_read_register( rp, SONIC_REG_IMR ) & (IMR_PRXEN | IMR_RBAEEN)) &&
377      (sonic_read_register( rp, SONIC_REG_ISR ) & (ISR_PKTRX | ISR_RBAE))) {
378    sonic_write_register(
379       rp,
380       SONIC_REG_IMR,
381       sonic_read_register( rp, SONIC_REG_IMR) & ~(IMR_PRXEN | IMR_RBAEEN)
382    );
383    dp->rxInterrupts++;
384    rtems_event_send (dp->iface->rxproc, INTERRUPT_EVENT);
385  }
386
387  /*
388   * Packet started, transmitter done or transmitter error?
389   */
390  if ((sonic_read_register( rp, SONIC_REG_IMR ) & (IMR_PINTEN | IMR_PTXEN | IMR_TXEREN))
391   && (sonic_read_register( rp, SONIC_REG_ISR ) & (ISR_PINT | ISR_TXDN | ISR_TXER))) {
392    sonic_write_register(
393       rp,
394       SONIC_REG_IMR,
395       sonic_read_register( rp, SONIC_REG_IMR) &
396                  ~(IMR_PINTEN | IMR_PTXEN | IMR_TXEREN)
397    );
398    dp->txInterrupts++;
399    rtems_event_send (dp->txWaitTid, INTERRUPT_EVENT);
400  }
401}
402
403/*
404 ******************************************************************
405 *                                                                *
406 *                      Transmitter Routines                      *
407 *                                                                *
408 ******************************************************************
409 */
410
411/*
412 * Soak up transmit descriptors that have been sent.
413 */
414
415SONIC_STATIC void sonic_retire_tda (struct sonic *dp)
416{
417  rtems_unsigned16 status;
418  unsigned int collisions;
419
420  /*
421   * Repeat for all completed transmit descriptors.
422   */
423  while ((dp->tdaActiveCount != 0)
424      && ((status = dp->tdaTail->status) != 0)) {
425
426printf( "retire TDA %p (0x%04x)\n", dp->tdaTail, status );
427    /*
428     * Check for errors which stop the transmitter.
429     */
430    if (status & (TDA_STATUS_EXD |
431        TDA_STATUS_EXC |
432        TDA_STATUS_FU |
433        TDA_STATUS_BCM)) {
434      /*
435       * Restart the transmitter if there are
436       * packets waiting to go.
437       */
438      rtems_unsigned16 link;
439      link = *(dp->tdaTail->linkp);
440
441      if ((link & TDA_LINK_EOL) == 0) {
442        void *rp = dp->sonic;
443
444        sonic_write_register( rp, SONIC_REG_CTDA, link );
445        sonic_write_register( rp, SONIC_REG_CR, CR_TXP );
446      }
447    }
448
449    /*
450     * Update network statistics
451     */
452    collisions = (status & TDA_STATUS_COLLISION_MASK) >> TDA_STATUS_COLLISION_SHIFT;
453    if (collisions) {
454      if (collisions == 1)
455        dp->txSingleCollision++;
456      else
457        dp->txMultipleCollision++;
458      dp->txCollision += collisions;
459    }
460    if (status & TDA_STATUS_EXC)
461      dp->txExcessiveCollision++;
462    if (status & TDA_STATUS_OWC)
463      dp->txLateCollision++;
464    if (status & TDA_STATUS_EXD)
465      dp->txExcessiveDeferral++;
466    if (status & TDA_STATUS_DEF)
467      dp->txDeferred++;
468    if (status & TDA_STATUS_FU)
469      dp->txUnderrun++;
470    if (status & TDA_STATUS_CRSL)
471      dp->txLostCarrier++;
472
473    /*
474     * Free the packet
475     */
476    dp->tdaActiveCount--;
477    free_p ((struct mbuf **)&dp->tdaTail->mbufp);
478
479    /*
480     * Move to the next transmit descriptor
481     */
482    dp->tdaTail = dp->tdaTail->next;
483printf( "next TDA %p\n", dp->tdaTail );
484  }
485}
486
487/*
488 * Send raw packet (caller provides header).
489 * This code runs in the context of the interface transmit
490 * task (most packets)  or in the context of the network
491 * task (for ARP requests).
492 */
493
494SONIC_STATIC int sonic_raw (struct iface *iface, struct mbuf **bpp)
495{
496  struct sonic *dp = &sonic[iface->dev];
497  void *rp = dp->sonic;
498  struct mbuf *bp;
499  TransmitDescriptorPointer_t tdp;
500  volatile struct TransmitDescriptorFragLink *fp;
501  unsigned int packetSize;
502  int i;
503  static char padBuf[64];
504
505  /*
506   * Update the log.
507   */
508  iface->rawsndcnt++;
509  iface->lastsent = secclock ();
510  dump (iface, IF_TRACE_OUT, *bpp);
511
512  /*
513   * It would not do to have two tasks active in the transmit
514   * loop at the same time.
515   * The blocking is simple-minded since the odds of two tasks
516   * simultaneously attempting to use this code are low.  The only
517   * way that two tasks can try to run here is:
518   *  1) Task A enters this code and ends up having to
519   *     wait for a transmit buffer descriptor.
520   *  2) Task B gains control and tries to transmit a packet.
521   * The RTEMS/KA9Q scheduling semaphore ensures that there
522   * are no race conditions associated with manipulating the
523   * txWaitTid variable.
524   */
525  if (dp->txWaitTid) {
526    dp->txRawWait++;
527    while (dp->txWaitTid)
528      rtems_ka9q_ppause (10);
529  }
530
531  /*
532   * Free up transmit descriptors.
533   */
534  sonic_retire_tda (dp);
535
536  /*
537   * Wait for transmit descriptor to become available.
538   */
539  if (dp->tdaActiveCount == dp->tdaCount) {
540puts( "Wait for more TDAs" );
541    /*
542     * Find out who we are
543     */
544    if (dp->txWaitTid == 0)
545      rtems_task_ident (RTEMS_SELF, 0, &dp->txWaitTid);
546
547    /*
548     * Clear old events.
549     */
550    sonic_write_register( rp, SONIC_REG_ISR, ISR_PINT | ISR_TXDN | ISR_TXER );
551
552    /*
553     * Wait for transmit descriptor to become available.
554     * Note that the transmit descriptors are checked
555     * *before* * entering the wait loop -- this catches
556     * the possibility that a transmit descriptor became
557     * available between the `if' the started this block,
558     * and the clearing of the interrupt status register.
559     */
560    sonic_retire_tda (dp);
561    while (dp->tdaActiveCount == dp->tdaCount) {
562      /*
563       * Enable transmitter interrupts.
564       */
565      sonic_write_register(
566         rp,
567         SONIC_REG_IMR,
568         sonic_read_register( rp, SONIC_REG_IMR) |
569                (IMR_PINTEN | IMR_PTXEN | IMR_TXEREN)
570      );
571
572      /*
573       * Wait for interrupt
574       */
575      rtems_ka9q_event_receive (INTERRUPT_EVENT,
576            RTEMS_WAIT|RTEMS_EVENT_ANY,
577            RTEMS_NO_TIMEOUT);
578      sonic_write_register( rp, SONIC_REG_ISR, ISR_PINT | ISR_TXDN | ISR_TXER );
579      sonic_retire_tda (dp);
580    }
581  }
582
583  /*
584   * Get the head of the packet mbuf chain.
585   */
586  bp = *bpp;
587
588  /*
589   * Fill in the transmit descriptor fragment descriptors.
590   * ===CACHE===
591   * If data cache is operating in write-back mode, flush cached
592   * data to memory.
593   */
594  tdp = dp->tdaHead->next;
595  tdp->mbufp = bp;
596  packetSize = 0;
597  fp = tdp->frag;
598  for (i = 0 ; i < MAXIMUM_FRAGS_PER_DESCRIPTOR ; i++, fp++) {
599    fp->frag_lsw = LSW(bp->data);
600    fp->frag_msw = MSW(bp->data);
601    fp->frag_size = bp->cnt;
602    packetSize += bp->cnt;
603
604#if (SONIC_DEBUG & SONIC_DEBUG_FRAGMENTS)
605    printf( "fp %p 0x%04x%04x %d\n",
606      fp, fp->frag_msw, fp->frag_lsw, fp->frag_size );
607#endif
608    /*
609     * Break out of the loop if this mbuf is the last in the frame.
610     */
611    if ((bp = bp->next) == NULL)
612      break;
613  }
614
615  /*
616   * Pad short packets.
617   */
618  if  ((packetSize < 64) && (i < MAXIMUM_FRAGS_PER_DESCRIPTOR)) {
619    int padSize = 64 - packetSize;
620    fp++;
621    fp->frag_lsw = LSW(padBuf);
622    fp->frag_msw = MSW(padBuf);
623    fp->frag_size = padSize;
624#if (SONIC_DEBUG & SONIC_DEBUG_FRAGMENTS)
625    printf( "PAD fp %p 0x%04x%04x %d\n",
626         fp, fp->frag_msw, fp->frag_lsw, fp->frag_size );
627#endif
628    packetSize += padSize;
629    i++;
630  }
631
632  /*
633   * Fill Transmit Descriptor
634   */
635  tdp->pkt_size = packetSize;
636  tdp->frag_count = i + 1;
637  tdp->status = 0;
638
639  /*
640   * Chain onto list and start transmission.
641   */
642  tdp->linkp = &(fp+1)->frag_link;
643  *tdp->linkp = LSW(tdp->next) | TDA_LINK_EOL;
644  *dp->tdaHead->linkp &= ~TDA_LINK_EOL;
645  dp->tdaActiveCount++;
646  dp->tdaHead = tdp;
647
648  sonic_write_register(
649     rp,
650     SONIC_REG_IMR,
651     sonic_read_register( rp, SONIC_REG_IMR) |
652            (IMR_PINTEN | IMR_PTXEN | IMR_TXEREN)
653  );
654  sonic_write_register( rp, SONIC_REG_CR, CR_TXP );
655
656  /*
657   * Let KA9Q know the packet is on the way
658   */
659
660  dp->txWaitTid = 0;
661  *bpp = NULL;
662  return 0;
663}
664
665/*
666 ******************************************************************
667 *                                                                *
668 *                        Receiver Routines                       *
669 *                                                                *
670 ******************************************************************
671 */
672
673/*
674 * Wait for SONIC to hand over a Receive Descriptor.
675 */
676
677SONIC_STATIC void sonic_rda_wait(
678  struct sonic *dp,
679  ReceiveDescriptorPointer_t rdp
680)
681{
682  int i;
683  void *rp = dp->sonic;
684
685  /*
686   * Wait for Receive Descriptor.
687   * The order of the tests is very important.
688   *    The RDA is checked after RBAE is detected.  This ensures that
689   *    the driver processes all RDA entries before reusing the RRA
690   *    entry holding the giant packet.
691   *    The event wait is done after the RDA and RBAE checks.  This
692   *    catches the possibility that a Receive Descriptor became ready
693   *    between the call to this function and the clearing of the
694   *    interrupt status register bit.
695   */
696  for (;;) {
697    /*
698     * Has a giant packet arrived?
699     * The National DP83932C data sheet is very vague on what
700     * happens under this condition.  The description of the
701     * Interrupt Status Register (Section 4.3.6) states,
702     * ``Reception is aborted and the SONIC fetches the next
703     * available resource descriptors in the RRA.  The buffer
704     * space is not re-used and an RDA is not setup for the
705     * truncated packet.''
706     * I take ``Reception is aborted''  to mean that the RXEN
707     * bit in the Command Register is cleared and must be set
708     * by the driver to begin reception again.
709     * Unfortunately, an alternative interpretation could be
710     * that only reception of the current packet is aborted.
711     * This would be more difficult to recover from....
712     */
713    if (sonic_read_register( rp, SONIC_REG_ISR ) & ISR_RBAE) {
714      /*
715       * One more check to soak up any Receive Descriptors
716       * that may already have been handed back to the driver.
717       */
718      if (rdp->in_use == RDA_IN_USE)
719        break;
720
721      /*
722       * Check my interpretation of the SONIC manual.
723       */
724      if (sonic_read_register( rp, SONIC_REG_CR ) & CR_RXEN)
725        rtems_panic ("SONIC RBAE/RXEN");
726
727      /*
728       * Update statistics
729       */
730      dp->rxGiant++;
731
732      /*
733       * Reuse receive buffer.
734       * Again, the manual is subject to interpretation.  The
735       * RRP register is described as, `the lower address of
736       * the next descriptor the SONIC will read.''
737       * Since, acording to the ISR/RBAE notes, the SONIC has
738       * ``fetched the next available resource descriptor in
739       * the RRA'', I interpret this to mean that that the
740       * driver has to move the RRP back *two* entries to
741       * reuse the receive buffer holding the giant packet.
742       */
743      for (i = 0 ; i < 2 ; i++) {
744        if (sonic_read_register( rp, SONIC_REG_RRP ) ==
745            sonic_read_register( rp, SONIC_REG_RSA ))
746          sonic_write_register(
747            rp,
748            SONIC_REG_RRP,
749            sonic_read_register( rp, SONIC_REG_REA )
750          );
751          sonic_write_register(
752             rp,
753             SONIC_REG_RRP,
754             sonic_read_register(rp, SONIC_REG_RRP) - sizeof(ReceiveResource_t)
755          );
756      }
757
758      /*
759       * Restart reception
760       */
761      sonic_write_register( rp, SONIC_REG_ISR, ISR_RBAE );
762      sonic_write_register( rp, SONIC_REG_CR, CR_RXEN );
763    }
764
765    /*
766     * Clear old packet-received events.
767     */
768    sonic_write_register( rp, SONIC_REG_ISR, ISR_PKTRX );
769
770    /*
771     * Has Receive Descriptor become available?
772     */
773    if (rdp->in_use == RDA_IN_USE)
774      break;
775
776    /*
777     * Enable interrupts.
778     */
779    sonic_write_register(
780       rp,
781       SONIC_REG_IMR,
782       sonic_read_register( rp, SONIC_REG_IMR) | (IMR_PRXEN | IMR_RBAEEN)
783    );
784
785    /*
786     * Wait for interrupt.
787     */
788    rtems_ka9q_event_receive (INTERRUPT_EVENT,
789            RTEMS_WAIT|RTEMS_EVENT_ANY,
790            RTEMS_NO_TIMEOUT);
791  }
792}
793
794/*
795 * SCC reader task
796 */
797
798SONIC_STATIC void sonic_rx (int dev, void *p1, void *p2)
799{
800  struct iface *iface = (struct iface *)p1;
801  struct sonic *dp = (struct sonic *)p2;
802  void *rp = dp->sonic;
803  struct mbuf *bp;
804  rtems_unsigned16 status;
805  ReceiveDescriptorPointer_t rdp;
806  ReceiveResourcePointer_t rwp, rea;
807  rtems_unsigned16 newMissedTally, oldMissedTally;
808  int continuousCount;
809
810  rwp = dp->rsa;
811  rea = rwp;
812  rdp = dp->rda; /* XXX was rdp_last */
813
814  /*
815   * Start the receiver
816   */
817  oldMissedTally = sonic_read_register( rp, SONIC_REG_MPT );
818  sonic_write_register( rp, SONIC_REG_CR, CR_RRRA );
819  sonic_write_register( rp, SONIC_REG_CR, CR_RXEN );
820
821  /*
822   * Input packet handling loop
823   */
824  continuousCount = 0;
825  for (;;) {
826    /*
827     * Wait till SONIC supplies a Receive Descriptor.
828     */
829    if (rdp->in_use == RDA_FREE) {
830      continuousCount = 0;
831      sonic_rda_wait (dp, rdp);
832    }
833
834/* printf( "Incoming packet %p\n", rdp ); */
835
836    /*
837     * Check that packet is valid
838     */
839    status = rdp->status;
840    if (status & RDA_STATUS_PRX) {
841      struct mbuf **mbp;
842      void *p;
843
844/* printf( "Valid packet\n" ); */
845      /*
846       * Get the mbuf pointer
847       */
848      p = PTR(rdp->pkt_msw, rdp->pkt_lsw);
849      mbp = (struct mbuf **)p - 1;
850      bp = *mbp;
851
852      /*
853       * Pass the packet up the chain.
854       * The mbuf count is reduced to remove
855       * the frame check sequence at the end
856       * of the packet.
857       * ===CACHE===
858       * Invalidate cache entries for this memory.
859       */
860      bp->cnt = rdp->byte_count - sizeof (uint32);
861/* printf( "Routing the packet\n" ); */
862      net_route (iface, &bp);
863
864      /*
865       * Give the network code a chance to digest the
866       * packet.  This guards against a flurry of
867       * incoming packets (usually an ARP storm) from
868       * using up all the available memory.
869       */
870      if (++continuousCount >= dp->rdaCount)
871        kwait_null ();
872
873      /*
874       * Sanity check that Receive Resource Area is
875       * still in sync with Receive Descriptor Area
876       * The buffer reported in the Receive Descriptor
877       * should be the same as the buffer in the Receive
878       * Resource we are about to reuse.
879       */
880/* XXX figure out whether this is valid or not */
881#if 0
882      if ((LSW(p) != rwp->buff_ptr_lsw)
883       || (MSW(p) != rwp->buff_ptr_msw))
884        rtems_panic ("SONIC RDA/RRA");
885#endif
886
887      /*
888       * Allocate a new mbuf.
889       */
890      bp = ambufw (RBUF_SIZE);
891      mbp = (struct mbuf **)bp->data;
892      bp->data += sizeof *mbp;
893      *mbp = bp;
894
895      /*
896       * Reuse Receive Resource.
897       */
898      rwp->buff_ptr_lsw = LSW(bp->data);
899      rwp->buff_ptr_msw = MSW(bp->data);
900      rwp++;
901      if (rwp == rea)
902        rwp = dp->rsa;
903      sonic_write_register( rp, SONIC_REG_RWP , LSW(rwp) );
904
905      /*
906       * Tell the SONIC to reread the RRA.
907       */
908      if (sonic_read_register( rp, SONIC_REG_ISR ) & ISR_RBE)
909        sonic_write_register( rp, SONIC_REG_ISR, ISR_RBE );
910    }
911    else {
912      if (status & RDA_STATUS_COL)
913        dp->rxCollision++;
914      if (status & RDA_STATUS_FAER)
915        dp->rxNonOctet++;
916      else if (status & RDA_STATUS_CRCR)
917        dp->rxBadCRC++;
918    }
919
920    /*
921     * Count missed packets
922     */
923    newMissedTally = sonic_read_register( rp, SONIC_REG_MPT );
924    if (newMissedTally != oldMissedTally) {
925      dp->rxMissed += (newMissedTally - oldMissedTally) & 0xFFFF;
926      newMissedTally = oldMissedTally;
927    }
928
929    /*
930     * Move to next receive descriptor
931     */
932    rdp->link |= RDA_LINK_EOL;
933    rdp->in_use = RDA_FREE;
934    rdp = rdp->next;
935    rdp->link &= ~RDA_LINK_EOL;
936  }
937}
938
939/*
940 ******************************************************************
941 *                                                                *
942 *                     Initialization Routines                    *
943 *                                                                *
944 ******************************************************************
945 */
946
947/*
948 * Initialize the SONIC hardware
949 */
950SONIC_STATIC void sonic_initialize_hardware(
951  struct sonic *dp,
952  int broadcastFlag
953)
954{
955  void *rp = dp->sonic;
956  int i;
957  unsigned char *hwaddr;
958  rtems_isr_entry old_handler;
959  TransmitDescriptorPointer_t otdp, tdp;
960  ReceiveDescriptorPointer_t ordp, rdp;
961  ReceiveResourcePointer_t rwp, rea;
962  struct mbuf *bp;
963  CamDescriptorPointer_t cdp;
964
965  /*
966   *  The Revision B SONIC has a horrible bug known as the "Zero
967   *  Length Packet bug".  The initial board used to develop this
968   *  driver had a newer revision of the SONIC so there was no reason
969   *  to check for this.  If you have the Revision B SONIC chip, then
970   *  you need to add some code to the RX path to handle this weirdness.
971   */
972
973  if ( sonic_read_register( rp, SONIC_REG_SR ) < SONIC_REVISION_C ) {
974    rtems_fatal_error_occurred( 0x0BADF00D );  /* don't eat this part :) */
975  }
976 
977  /*
978   *  Set up circular linked list in Transmit Descriptor Area.
979   *  Use the PINT bit in the transmit configuration field to
980   *  request an interrupt on every other transmitted packet.
981   *
982   *  NOTE: sonic_allocate() zeroes all of the memory allocated.
983   */
984
985  dp->tdaActiveCount = 0;
986  dp->tdaTail = sonic_allocate(dp->tdaCount * sizeof *tdp);
987#if (SONIC_DEBUG & SONIC_DEBUG_MEMORY)
988  printf( "tdaTail = %p\n", dp->tdaTail );
989#endif
990  otdp = tdp = dp->tdaTail;
991  for (i = 0 ; i < dp->tdaCount ; i++) {
992    /*
993     *  status, pkt_config, pkt_size, and all fragment fields
994     *  are set to zero by sonic_allocate.
995     */
996
997/* XXX not used by other drivers
998    if (i & 1)
999      tdp->pkt_config = TDA_CONFIG_PINT;
1000*/
1001
1002    tdp->frag_count        = 1;
1003    tdp->frag[0].frag_link = LSW(tdp + 1);
1004    tdp->link_pad          = LSW(tdp + 1) | TDA_LINK_EOL;
1005    otdp->linkp            = &((tdp + 1)->frag[0].frag_link);
1006    tdp->next              = (TransmitDescriptor_t *)(tdp + 1);
1007    otdp = tdp;
1008    tdp++;
1009  }
1010  dp->tdaHead = otdp;  /* XXX why? */
1011  otdp->link_pad = LSW(dp->tdaTail) | TDA_LINK_EOL;
1012  otdp->next = (TransmitDescriptor_t *)dp->tdaTail;
1013  otdp->linkp = &dp->tdaHead->frag[0].frag_link;
1014
1015  /*
1016   *  Set up circular linked list in Receive Descriptor Area.
1017   *  Leaves ordp pointing at the `end' of the list and
1018   *  dp->rda pointing at the `beginning' of the list.
1019   *
1020   *  NOTE: The RDA and CDP must have the same MSW for their addresses.
1021   */
1022
1023  dp->rda = sonic_allocate(
1024              (dp->rdaCount * sizeof(ReceiveDescriptor_t)) + 
1025                sizeof(CamDescriptor_t) );
1026  dp->cdp = (CamDescriptorPointer_t) ((unsigned char *)dp->rda +
1027        (dp->rdaCount * sizeof(ReceiveDescriptor_t)));
1028#if (SONIC_DEBUG & SONIC_DEBUG_MEMORY)
1029  printf( "rda area = %p\n", dp->rda );
1030  printf( "cdp area = %p\n", dp->cdp );
1031#endif
1032
1033  ordp = rdp = dp->rda;
1034  for (i = 0 ; i < dp->rdaCount ; i++) {
1035    /*
1036     *  status, byte_count, pkt_ptr0, pkt_ptr1, and seq_no are set
1037     *  to zero by sonic_allocate.
1038     */
1039    rdp->link   = LSW(rdp + 1);
1040    rdp->in_use = RDA_FREE;
1041    rdp->next   = (ReceiveDescriptor_t *)(rdp + 1);
1042    ordp = rdp;
1043    rdp++;
1044  }
1045  /*
1046   *  Link the last desriptor to the 1st one and mark it as the end
1047   *  of the list.
1048   */
1049  ordp->next  = dp->rda;
1050  ordp->link |= RDA_LINK_EOL;
1051  dp->rdp_last = rdp;
1052 
1053  /*
1054   * Allocate the receive resource area.
1055   * In accordance with National Application Note 746, make the
1056   * receive resource area bigger than the receive descriptor area.
1057   * This has the useful side effect of making the receive resource
1058   * area big enough to hold the CAM descriptor area.
1059   */
1060
1061  dp->rsa = sonic_allocate((dp->rdaCount + RRA_EXTRA_COUNT) * sizeof *dp->rsa);
1062#if (SONIC_DEBUG & SONIC_DEBUG_MEMORY)
1063  printf( "rsa area = %p\n", dp->rsa );
1064#endif
1065
1066  /*
1067   *  Set up list in Receive Resource Area.
1068   *  Allocate space for incoming packets.
1069   */
1070
1071  rwp = dp->rsa;
1072  for (i = 0 ; i < (dp->rdaCount + RRA_EXTRA_COUNT) ; i++, rwp++) {
1073    struct mbuf **mbp;
1074
1075    /*
1076     * Allocate memory for buffer.
1077     * Place a pointer to the mbuf at the beginning of the buffer
1078     * so we can find the mbuf when the SONIC returns the buffer
1079     * to the driver.
1080     */
1081    bp = ambufw (RBUF_SIZE);
1082    mbp = (struct mbuf **)bp->data;
1083    bp->data += sizeof *mbp;
1084    *mbp = bp;
1085
1086    /*
1087     * Set up RRA entry
1088     */
1089
1090    rwp->buff_ptr_lsw = LSW(bp->data);
1091    rwp->buff_ptr_msw = MSW(bp->data);
1092    rwp->buff_wc_lsw = RBUF_WC;
1093    rwp->buff_wc_msw = 0;
1094  }
1095  rea = rwp;
1096
1097  /*
1098   * Issue a software reset.
1099   */
1100  sonic_write_register( rp, SONIC_REG_CR, CR_RST | CR_STP | CR_RXDIS | CR_HTX );
1101
1102  /*
1103   * Set up data configuration registers.
1104   */
1105  sonic_write_register( rp, SONIC_REG_DCR, SONIC_DCR );
1106  sonic_write_register( rp, SONIC_REG_DCR2, SONIC_DC2 );
1107
1108  sonic_write_register( rp, SONIC_REG_CR, CR_STP | CR_RXDIS | CR_HTX );
1109
1110  /*
1111   * Mask all interrupts
1112   */
1113  sonic_write_register( rp, SONIC_REG_IMR, 0x3fff );
1114
1115  /*
1116   * Clear outstanding interrupts.
1117   */
1118  sonic_write_register( rp, SONIC_REG_ISR, 0x7FFF );
1119
1120  /*
1121   *  Clear the tally counters
1122   */
1123
1124  sonic_write_register( rp, SONIC_REG_CRCT, 0xFFFF );
1125  sonic_write_register( rp, SONIC_REG_FAET, 0xFFFF );
1126  sonic_write_register( rp, SONIC_REG_MPT, 0xFFFF );
1127  sonic_write_register( rp, SONIC_REG_RSC, 0 );
1128
1129  /*
1130   *  Set the Receiver mode
1131   *
1132   *  Enable/disable reception of broadcast packets
1133   */
1134
1135  if (broadcastFlag)
1136    sonic_write_register( rp, SONIC_REG_RCR, RCR_BRD );
1137  else
1138    sonic_write_register( rp, SONIC_REG_RCR, 0 );
1139
1140  /*
1141   * Set up Resource Area pointers
1142   */
1143
1144  sonic_write_register( rp, SONIC_REG_URRA, MSW(dp->rsa) );
1145  sonic_write_register( rp, SONIC_REG_RSA, LSW(dp->rsa) );
1146
1147  sonic_write_register( rp, SONIC_REG_REA, LSW(rea) );
1148
1149  sonic_write_register( rp, SONIC_REG_RRP, LSW(dp->rsa) );
1150  sonic_write_register( rp, SONIC_REG_RWP, LSW(dp->rsa) ); /* XXX was rea */
1151
1152  sonic_write_register( rp, SONIC_REG_URDA, MSW(dp->rda) );
1153  sonic_write_register( rp, SONIC_REG_CRDA, LSW(dp->rda) );
1154
1155  sonic_write_register( rp, SONIC_REG_UTDA, MSW(dp->tdaTail) );
1156  sonic_write_register( rp, SONIC_REG_CTDA, LSW(dp->tdaTail) );
1157
1158  /*
1159   * Set End Of Buffer Count register to the value recommended
1160   * in Note 1 of Section 3.4.4.4 of the SONIC data sheet.
1161   */
1162
1163  sonic_write_register( rp, SONIC_REG_EOBC, RBUF_WC - 2 );
1164
1165  /*
1166   *  Issue the load RRA command
1167   */
1168
1169  sonic_write_register( rp, SONIC_REG_CR, CR_RRRA );
1170  while (sonic_read_register( rp, SONIC_REG_CR ) & CR_RRRA)
1171    continue;
1172
1173  /*
1174   * Remove device reset
1175   */
1176
1177  sonic_write_register( rp, SONIC_REG_CR, 0 );
1178
1179  /*
1180   *  Set up the SONIC CAM with our hardware address.
1181   */
1182
1183  hwaddr = dp->iface->hwaddr;
1184  cdp = dp->cdp;
1185
1186#if (SONIC_DEBUG & SONIC_DEBUG_CAM)
1187  printf( "hwaddr: %2x:%2x:%2x:%2x:%2x:%2x\n",
1188     hwaddr[0], hwaddr[1], hwaddr[2], hwaddr[3], hwaddr[4], hwaddr[5] );
1189#endif
1190
1191  cdp->cep  = 0;                     /* Fill first and only entry in CAM */
1192  cdp->cap0 = hwaddr[1] << 8 | hwaddr[0];
1193  cdp->cap1 = hwaddr[3] << 8 | hwaddr[2];
1194  cdp->cap2 = hwaddr[5] << 8 | hwaddr[4];
1195  cdp->ce   = 0x0001;                /* Enable first entry in CAM */
1196
1197  sonic_write_register( rp, SONIC_REG_CDC, 1 );      /* 1 entry in CDA */
1198  sonic_write_register( rp, SONIC_REG_CDP, LSW(cdp) );
1199  sonic_write_register( rp, SONIC_REG_CR,  CR_LCAM );  /* Load the CAM */
1200
1201  while (sonic_read_register( rp, SONIC_REG_CR ) & CR_LCAM)
1202    continue;
1203
1204  /*
1205   * Verify that CAM was properly loaded.
1206   */
1207
1208  sonic_write_register( rp, SONIC_REG_CR, CR_RST | CR_STP | CR_RXDIS | CR_HTX );
1209
1210#if (SONIC_DEBUG & SONIC_DEBUG_CAM)
1211  sonic_write_register( rp, SONIC_REG_CEP, 0 );  /* Select first entry in CAM */
1212    printf ("Loaded Ethernet address into SONIC CAM.\n"
1213      "  Wrote %04x%04x%04x - %#x\n"
1214      "   Read %04x%04x%04x - %#x\n", 
1215        cdp->cap2, cdp->cap1, cdp->cap0, cdp->ce,
1216        sonic_read_register( rp, SONIC_REG_CAP2 ),
1217        sonic_read_register( rp, SONIC_REG_CAP1 ),
1218        sonic_read_register( rp, SONIC_REG_CAP0 ),
1219        sonic_read_register( rp, SONIC_REG_CE ));
1220#endif
1221
1222  sonic_write_register( rp, SONIC_REG_CEP, 0 );  /* Select first entry in CAM */
1223  if ((sonic_read_register( rp, SONIC_REG_CAP2 ) != cdp->cap2)
1224   || (sonic_read_register( rp, SONIC_REG_CAP1 ) != cdp->cap1)
1225   || (sonic_read_register( rp, SONIC_REG_CAP0 ) != cdp->cap0)
1226   || (sonic_read_register( rp, SONIC_REG_CE ) != cdp->ce)) {
1227    printf ("Failed to load Ethernet address into SONIC CAM.\n"
1228      "  Wrote %04x%04x%04x - %#x\n"
1229      "   Read %04x%04x%04x - %#x\n", 
1230        cdp->cap2, cdp->cap1, cdp->cap0, cdp->ce,
1231        sonic_read_register( rp, SONIC_REG_CAP2 ),
1232        sonic_read_register( rp, SONIC_REG_CAP1 ),
1233        sonic_read_register( rp, SONIC_REG_CAP0 ),
1234        sonic_read_register( rp, SONIC_REG_CE ));
1235    rtems_panic ("SONIC LCAM");
1236  }
1237
1238  sonic_write_register(rp, SONIC_REG_CR, CR_TXP | CR_RXEN | CR_STP);
1239
1240  /*
1241   * Attach SONIC interrupt handler
1242   */
1243  sonic_write_register( rp, SONIC_REG_IMR, 0 );
1244  old_handler = set_vector(sonic_interrupt_handler, dp->vector, 0);
1245
1246  /*
1247   * Remainder of hardware initialization is
1248   * done by the receive and transmit daemons.
1249   */
1250}
1251
1252/*
1253 * Attach an SONIC driver to the system
1254 * This is the only `extern' function in the driver.
1255 *
1256 * argv[0]: interface label, e.g. "rtems"
1257 * The remainder of the arguments are optional key/value pairs:
1258 * mtu ##                  --  maximum transmission unit, default 1500
1259 * broadcast y/n           -- accept or ignore broadcast packets, default yes
1260 * rbuf ##                 -- Set number of receive descriptor entries
1261 * tbuf ##                 -- Set number of transmit descriptor entries
1262 * ip ###.###.###.###      -- IP address
1263 * ether ##:##:##:##:##:## -- Ethernet address
1264 * reg ######              -- Address of SONIC device registers
1265 * vector ###              -- SONIC interrupt vector
1266 */
1267int
1268rtems_ka9q_driver_attach (int argc, char *argv[], void *p)
1269{
1270  struct sonic *dp;
1271  struct iface *iface;
1272  char *cp;
1273  int argIndex;
1274  int broadcastFlag;
1275  char cbuf[30];
1276
1277  /*
1278   * Find an unused entry
1279   */
1280  dp = sonic;
1281  for (;;) {
1282    if (dp == &sonic[NSONIC]) {
1283      printf ("No more SONIC devices.\n");
1284      return -1;
1285    }
1286    if (dp->iface == NULL)
1287      break;
1288    dp++;
1289  }
1290  if (if_lookup (argv[0]) != NULL) {
1291    printf ("Interface %s already exists\n", argv[0]);
1292    return -1;
1293  }
1294
1295  /*
1296   *  zero out the control structure
1297   */
1298
1299  memset( dp, 0, sizeof(struct sonic) );
1300
1301  /*
1302   * Create an inteface descriptor
1303   */
1304  iface = callocw (1, sizeof *iface);
1305  iface->name = strdup (argv[0]);
1306  iface->dev = dp - sonic;
1307
1308  /*
1309   * Set default values
1310   */
1311  broadcastFlag = 1;
1312  dp->txWaitTid = 0;
1313  dp->rdaCount = RDA_COUNT;
1314  dp->tdaCount = TDA_COUNT;
1315  iface->mtu = 1500;
1316  iface->addr = Ip_addr;
1317  iface->hwaddr = mallocw (EADDR_LEN);
1318  memset (iface->hwaddr, 0x08, EADDR_LEN);
1319  dp->sonic = (struct SonicRegisters *)SONIC_BASE_ADDRESS;
1320  dp->vector = SONIC_VECTOR;
1321
1322  /*
1323   * Parse remaining arguments
1324   */
1325  for (argIndex = 1 ; argIndex < (argc - 1) ; argIndex++) {
1326    if (strcmp ("mtu", argv[argIndex]) == 0) {
1327      iface->mtu = strtoul (argv[++argIndex], NULL, 0);
1328    }
1329    else if (strcmp ("broadcast", argv[argIndex]) == 0) {
1330      if (*argv[++argIndex] == 'n')
1331        broadcastFlag = 0;
1332    }
1333    else if (strcmp ("rbuf", argv[argIndex]) == 0) {
1334      /*
1335       * The minimum RDA count is 2.  A single-entry RDA
1336       * would be difficult to use since the SONIC does
1337       * not release (in_use = 0) the RDA that has the
1338       * EOL bit set.
1339       */
1340      dp->rdaCount = strtoul (argv[++argIndex], NULL, 0);
1341      if ((dp->rdaCount <= 1) || (dp->rdaCount > 200)) {
1342        printf ("RDA option (%d) is invalid.\n", dp->rdaCount);
1343        return -1;
1344      }
1345    }
1346    else if (strcmp ("tbuf", argv[argIndex]) == 0) {
1347      dp->tdaCount = strtoul (argv[++argIndex], NULL, 0);
1348      if ((dp->tdaCount <= 1) || (dp->tdaCount > 200)) {
1349        printf ("TDA option (%d) is invalid.\n", dp->tdaCount);
1350        return -1;
1351      }
1352    }
1353    else if (strcmp ("ip", argv[argIndex]) == 0) {
1354      iface->addr = resolve (argv[++argIndex]);
1355    }
1356    else if (strcmp ("ether", argv[argIndex]) == 0) {
1357      gether (iface->hwaddr, argv[++argIndex]);
1358    }
1359    else if (strcmp ("reg", argv[argIndex]) == 0) {
1360      dp->sonic = (struct SonicRegisters *)strtoul (argv[++argIndex], NULL, 0);
1361    }
1362    else if (strcmp ("vector", argv[argIndex]) == 0) {
1363      dp->vector = strtoul (argv[++argIndex], NULL, 0);
1364    }
1365    else {
1366      printf ("Argument %d (%s) is invalid.\n", argIndex, argv[argIndex]);
1367      return -1;
1368    }
1369  }
1370  printf ("Ethernet address: %s\n", pether (cbuf, iface->hwaddr));
1371  iface->raw = sonic_raw;
1372  iface->stop = sonic_stop;
1373  iface->show = sonic_show;
1374  dp->iface = iface;
1375  setencap (iface, "Ethernet");
1376
1377  /*
1378   * Set up SONIC hardware
1379   */
1380  sonic_initialize_hardware (dp, broadcastFlag);
1381
1382  /*
1383   * Chain onto list of interfaces
1384   */
1385  iface->next = Ifaces;
1386  Ifaces = iface;
1387
1388  /*
1389   * Start I/O daemons
1390   */
1391  cp = if_name (iface, " tx");
1392  iface->txproc = newproc (cp, 2048, if_tx, iface->dev, iface, NULL, 0);
1393  free (cp);
1394  cp = if_name (iface, " rx");
1395  iface->rxproc = newproc (cp, 2048, sonic_rx, iface->dev, iface, dp, 0);
1396  free (cp);
1397  return 0;
1398}
1399
1400#if (SONIC_DEBUG & SONIC_DEBUG_PRINT_REGISTERS)
1401#include <stdio.h>
1402
1403char SONIC_Reg_name[64][6]= {
1404    "CR",         /* 0x00 */
1405    "DCR",        /* 0x01 */
1406    "RCR",        /* 0x02 */
1407    "TCR",        /* 0x03 */
1408    "IMR",        /* 0x04 */
1409    "ISR",        /* 0x05 */
1410    "UTDA",       /* 0x06 */
1411    "CTDA",       /* 0x07 */
1412    "0x08",       /* 0x08 */
1413    "0x09",       /* 0x09 */
1414    "0x0A",       /* 0x0A */
1415    "0x0B",       /* 0x0B */
1416    "0x0C",       /* 0x0C */
1417    "URDA",       /* 0x0D */
1418    "CRDA",       /* 0x0E */
1419    "0x0F",       /* 0x0F */
1420    "0x10",       /* 0x10 */
1421    "0x11",       /* 0x11 */
1422    "0x12",       /* 0x12 */
1423    "EOBC",       /* 0x13 */
1424    "URRA",       /* 0x14 */
1425    "RSA",        /* 0x15 */
1426    "REA",        /* 0x16 */
1427    "RRP",        /* 0x17 */
1428    "RWP",        /* 0x18 */
1429    "0x19",       /* 0x19 */
1430    "0x1A",       /* 0x1A */
1431    "0x1B",       /* 0x1B */
1432    "0x1C",       /* 0x1C */
1433    "0x0D",       /* 0x1D */
1434    "0x1E",       /* 0x1E */
1435    "0x1F",       /* 0x1F */
1436    "0x20",       /* 0x20 */
1437    "CEP",        /* 0x21 */
1438    "CAP2",       /* 0x22 */
1439    "CAP1",       /* 0x23 */
1440    "CAP0",       /* 0x24 */
1441    "CE",         /* 0x25 */
1442    "CDP",        /* 0x26 */
1443    "CDC",        /* 0x27 */
1444    "SR",         /* 0x28 */
1445    "WT0",        /* 0x29 */
1446    "WT1",        /* 0x2A */
1447    "RSC",        /* 0x2B */
1448    "CRCT",       /* 0x2C */
1449    "FAET",       /* 0x2D */
1450    "MPT",        /* 0x2E */
1451    "MDT",        /* 0x2F */
1452    "0x30",       /* 0x30 */
1453    "0x31",       /* 0x31 */
1454    "0x32",       /* 0x32 */
1455    "0x33",       /* 0x33 */
1456    "0x34",       /* 0x34 */
1457    "0x35",       /* 0x35 */
1458    "0x36",       /* 0x36 */
1459    "0x37",       /* 0x37 */
1460    "0x38",       /* 0x38 */
1461    "0x39",       /* 0x39 */
1462    "0x3A",       /* 0x3A */
1463    "0x3B",       /* 0x3B */
1464    "0x3C",       /* 0x3C */
1465    "0x3D",       /* 0x3D */
1466    "0x3E",       /* 0x3E */
1467    "DCR2"        /* 0x3F */
1468};
1469#endif
1470void sonic_write_register(
1471  void       *base,
1472  unsigned32  regno,
1473  unsigned32  value
1474)
1475{
1476  volatile unsigned32 *p = base;
1477
1478#if (SONIC_DEBUG & SONIC_DEBUG_PRINT_REGISTERS)
1479  printf( "%p Write 0x%04x to %s (0x%02x)\n",
1480      &p[regno], value, SONIC_Reg_name[regno], regno );
1481  fflush( stdout );
1482#endif
1483  p[regno] = value;
1484}
1485
1486unsigned32 sonic_read_register(
1487  void       *base,
1488  unsigned32  regno
1489)
1490{
1491  volatile unsigned32 *p = base;
1492  unsigned32           value;
1493
1494  value = p[regno];
1495#if (SONIC_DEBUG & SONIC_DEBUG_PRINT_REGISTERS)
1496  printf( "%p Read 0x%04x from %s (0x%02x)\n",
1497      &p[regno], value, SONIC_Reg_name[regno], regno );
1498  fflush( stdout );
1499#endif
1500  return value;
1501}
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