source: rtems/c/src/lib/libbsp/powerpc/dmv177/sonic/sonic.c @ 339737b

4.104.114.84.9
Last change on this file since 339737b was 339737b, checked in by Joel Sherrill <joel.sherrill@…>, on Aug 10, 1998 at 11:20:25 PM

Survives 16-20 packets. Appears to be ok on TX buffer management.
Problem appears to be on the RX buffer initialization side.

  • Property mode set to 100644
File size: 40.7 KB
Line 
1void break_when_you_get_here();
2/*
3 *******************************************************************
4 *******************************************************************
5 **                                                               **
6 **         RTEMS/KA9Q DRIVER FOR NATIONAL DP83932 `SONIC'        **
7 **         SYSTEMS-ORIENTED NETWORK INTERFACE CONTROLLER         **
8 **                                                               **
9 *******************************************************************
10 *******************************************************************
11 */
12
13/*
14 * $Revision$   $Date$   $Author$
15 * $State$
16 */
17
18/*
19 * References:
20 * 1) DP83932C-20/25/33 MHz SONIC(TM) Systems-Oriented Network Interface
21 *    Controller data sheet.  TL/F/10492, RRD-B30M105, National Semiconductor,
22 *    1995.
23 *
24 * 2) Software Driver Programmer's Guide for the DP83932 SONIC(TM),
25 *    Application Note 746, Wesley Lee and Mike Lui, TL/F/11140,
26 *    RRD-B30M75, National Semiconductor, March, 1991.
27 *
28 * 3) SVME/DMV-171 Single Board Computer Documentation Package, #805905,
29 *    DY 4 Systems Inc., Kanata, Ontario, September, 1996.
30 */
31
32#include "sonic.h"
33
34#include <rtems/error.h>
35#include <ka9q/rtems_ka9q.h>
36#include <ka9q/global.h>
37#include <ka9q/domain.h>
38#include <ka9q/enet.h>
39#include <ka9q/iface.h>
40#include <ka9q/netuser.h>
41#include <ka9q/trace.h>
42#include <ka9q/commands.h>
43
44/*
45 * Debug levels
46 *
47 */
48
49#define SONIC_DEBUG_NONE             0x0000
50#define SONIC_DEBUG_ALL              0xFFFF
51#define SONIC_DEBUG_PRINT_REGISTERS  0x0001
52#define SONIC_DEBUG_MEMORY           0x0002
53#define SONIC_DEBUG_MEMORY_ALLOCATE  0x0004
54#define SONIC_DEBUG_FRAGMENTS        0x0008
55#define SONIC_DEBUG_CAM              0x0008
56
57#define SONIC_DEBUG      (SONIC_DEBUG_MEMORY|SONIC_DEBUG_CAM)
58/* SONIC_DEBUG_ALL */
59
60
61/*
62 * XXX
63 */
64
65#include <dmv170.h>
66
67/*
68 *  Use the top line if you want more symbols.
69 */
70
71#define SONIC_STATIC
72/* #define SONIC_STATIC static */
73
74/*
75 * Number of devices supported by this driver
76 */
77#ifndef NSONIC
78# define NSONIC 1
79#endif
80
81/*
82 * Default location of device registers
83 */
84#ifndef SONIC_BASE_ADDRESS
85# define SONIC_BASE_ADDRESS 0xF3000000
86# warning "Using default SONIC_BASE_ADDRESS."
87#endif
88
89/*
90 * Default interrupt vector
91 */
92#ifndef SONIC_VECTOR
93# define SONIC_VECTOR 1
94# warning "Using default SONIC_VECTOR."
95#endif
96
97/*
98 * Default device configuration register values
99 * Conservative, generic values.
100 * DCR:
101 *      No extended bus mode
102 *      Unlatched bus retry
103 *      Programmable outputs unused
104 *      Asynchronous bus mode
105 *      User definable pins unused
106 *      No wait states (access time controlled by DTACK*)
107 *      32-bit DMA
108 *      Empty/Fill DMA mode
109 *      Maximum Transmit/Receive FIFO
110 * DC2:
111 *      Extended programmable outputs unused
112 *      Normal HOLD request
113 *      Packet compress output unused
114 *      No reject on CAM match
115 */
116#define SONIC_DCR \
117   (DCR_DW32 | DCR_WAIT0 | DCR_PO0 | DCR_PO1  | DCR_RFT24 | DCR_TFT28)
118#ifndef SONIC_DCR
119# define SONIC_DCR (DCR_DW32 | DCR_TFT28)
120#endif
121#ifndef SONIC_DC2
122# define SONIC_DC2 (0)
123#endif
124
125/*
126 * Default sizes of transmit and receive descriptor areas
127 */
128#define RDA_COUNT     20
129#define TDA_COUNT     10
130
131/*
132 *
133 * As suggested by National Application Note 746, make the
134 * receive resource area bigger than the receive descriptor area.
135 */
136#define RRA_EXTRA_COUNT  3
137
138/*
139 * RTEMS event used by interrupt handler to signal daemons.
140 */
141#define INTERRUPT_EVENT  RTEMS_EVENT_1
142
143/*
144 * Largest Ethernet frame.
145 */
146#define MAXIMUM_FRAME_SIZE  1518
147
148/*
149 * Receive buffer size.
150 * Allow for a pointer, plus a full ethernet frame (including Frame
151 * Check Sequence) rounded up to a 4-byte boundary.
152 */
153#define RBUF_SIZE  ((sizeof (void *) + (MAXIMUM_FRAME_SIZE) + 3) & ~3)
154#define RBUF_WC    ((((MAXIMUM_FRAME_SIZE) + 3) & ~3) / 2)
155
156/*
157 * Macros for manipulating 32-bit pointers as 16-bit fragments
158 */
159#define LSW(p)   ((rtems_unsigned16)((rtems_unsigned32)(p)))
160#define MSW(p)   ((rtems_unsigned16)((rtems_unsigned32)(p) >> 16))
161#define PTR(m,l) ((void*)(((rtems_unsigned16)(m)<<16)|(rtems_unsigned16)(l)))
162
163/*
164 * Hardware-specific storage
165 */
166struct sonic {
167  /*
168   * Connection to KA9Q
169   */
170  struct iface                     *iface;
171
172  /*
173   * Default location of device registers
174   * ===CACHE===
175   * This area must be non-cacheable, guarded.
176   */
177  void                             *sonic;
178
179  /*
180   * Interrupt vector
181   */
182  rtems_vector_number             vector;
183
184  /*
185   * Task waiting for transmit resources
186   */
187  rtems_id                        txWaitTid;
188
189  /*
190   * Receive resource area
191   */
192  int                             rdaCount;
193  ReceiveResourcePointer_t        rsa;
194  CamDescriptorPointer_t          cdp;
195  ReceiveDescriptorPointer_t      rda;
196  ReceiveDescriptorPointer_t      rdp_last;
197
198  /*
199   * Transmit descriptors
200   */
201  int                             tdaCount;
202  TransmitDescriptorPointer_t     tdaHead;  /* Last filled */
203  TransmitDescriptorPointer_t     tdaTail;  /* Next to retire */
204  int                             tdaActiveCount;
205
206  /*
207   * Statistics
208   */
209  unsigned long                   Interrupts;
210  unsigned long                   rxInterrupts;
211  unsigned long                   rxMissed;
212  unsigned long                   rxGiant;
213  unsigned long                   rxNonOctet;
214  unsigned long                   rxBadCRC;
215  unsigned long                   rxCollision;
216
217  unsigned long                   txInterrupts;
218  unsigned long                   txSingleCollision;
219  unsigned long                   txMultipleCollision;
220  unsigned long                   txCollision;
221  unsigned long                   txDeferred;
222  unsigned long                   txUnderrun;
223  unsigned long                   txLateCollision;
224  unsigned long                   txExcessiveCollision;
225  unsigned long                   txExcessiveDeferral;
226  unsigned long                   txLostCarrier;
227  unsigned long                   txRawWait;
228};
229SONIC_STATIC struct sonic sonic[NSONIC];
230
231/*
232 ******************************************************************
233 *                                                                *
234 *                        Support Routines                        *
235 *                                                                *
236 ******************************************************************
237 */
238
239void sonic_write_register(
240  void       *base,
241  unsigned32  regno,
242  unsigned32  value
243);
244
245unsigned32 sonic_read_register(
246  void       *base,
247  unsigned32  regno
248);
249
250/*
251 * Allocate non-cacheable memory on a single 64k page.
252 * Very simple minded -- just keeps trying till the memory is on a single page.
253 */
254SONIC_STATIC void * sonic_allocate(unsigned int nbytes)
255{
256  void *p;
257  unsigned long a1, a2;
258
259  for (;;) {
260    /*
261     * ===CACHE===
262     * Change malloc to malloc_noncacheable_guarded.
263     */
264    p = calloc(1, nbytes);
265    if (p == NULL)
266      rtems_panic ("No memory!");
267    a1 = (unsigned long)p;
268    a2 = a1 + nbytes - 1;
269    if ((a1 >> 16) == (a2 >> 16))
270      break;
271  }
272#if (SONIC_DEBUG & SONIC_DEBUG_MEMORY_ALLOCATE)
273  printf( "sonic_allocate %d bytes at %p\n", nbytes, p );
274#endif
275  return p;
276}
277
278/*
279 * Shut down the interface.
280 * This is a pretty simple-minded routine.  It doesn't worry
281 * about cleaning up mbufs, shutting down daemons, etc.
282 */
283
284SONIC_STATIC int sonic_stop (struct iface *iface)
285{
286  int i;
287  struct sonic *dp = &sonic[iface->dev];
288  void *rp = dp->sonic;
289
290  /*
291   * Stop the transmitter and receiver.
292   */
293  sonic_write_register( rp, SONIC_REG_CR, CR_HTX | CR_RXDIS );
294
295  /*
296   * Wait for things to stop.
297   * For safety's sake, there is an alternate exit.
298   */
299  i = 0;
300  while (sonic_read_register( rp, SONIC_REG_CR ) & (CR_RXEN | CR_TXP)) {
301    if (++i == 10000)
302      break;
303  }
304
305  /*
306   * Reset the device
307   */
308  sonic_write_register( rp, SONIC_REG_CR, CR_RST );
309  sonic_write_register( rp, SONIC_REG_IMR, 0 );
310  return 0;
311}
312
313/*
314 * Show interface statistics
315 */
316
317SONIC_STATIC void sonic_show (struct iface *iface)
318{
319  struct sonic *dp = &sonic[iface->dev];
320
321  printf (" Total Interrupts:%-8lu", dp->Interrupts);
322  printf ("    Rx Interrupts:%-8lu", dp->rxInterrupts);
323  printf ("            Giant:%-8lu", dp->rxGiant);
324  printf ("        Non-octet:%-8lu\n", dp->rxNonOctet);
325  printf ("          Bad CRC:%-8lu", dp->rxBadCRC);
326  printf ("        Collision:%-8lu", dp->rxCollision);
327  printf ("           Missed:%-8lu\n", dp->rxMissed);
328
329  printf (    "    Tx Interrupts:%-8lu", dp->txInterrupts);
330  printf (  "           Deferred:%-8lu", dp->txDeferred);
331  printf ("        Lost Carrier:%-8lu\n", dp->txLostCarrier);
332  printf (   "Single Collisions:%-8lu", dp->txSingleCollision);
333  printf ( "Multiple Collisions:%-8lu", dp->txMultipleCollision);
334  printf ("Excessive Collisions:%-8lu\n", dp->txExcessiveCollision);
335  printf (   " Total Collisions:%-8lu", dp->txCollision);
336  printf ( "     Late Collision:%-8lu", dp->txLateCollision);
337  printf ("            Underrun:%-8lu\n", dp->txUnderrun);
338  printf (   "  Raw output wait:%-8lu\n", dp->txRawWait);
339}
340
341/*
342 ******************************************************************
343 *                                                                *
344 *                        Interrupt Handler                       *
345 *                                                                *
346 ******************************************************************
347 */
348
349SONIC_STATIC rtems_isr sonic_interrupt_handler (rtems_vector_number v)
350{
351  struct sonic *dp = sonic;
352  void *rp;
353
354#if (NSONIC > 1)
355  /*
356   * Find the device which requires service
357   */
358  for (;;) {
359    if (dp->vector == v)
360      break;
361    if (++dp == &sonic[NSONIC])
362      return;  /* Spurious interrupt? */
363  }
364#endif /* NSONIC > 1 */
365
366  /*
367   * Get pointer to SONIC registers
368   */
369  rp = dp->sonic;
370
371  dp->Interrupts++;
372
373  /*
374   * Packet received or receive buffer area exceeded?
375   */
376  if ((sonic_read_register( rp, SONIC_REG_IMR ) & (IMR_PRXEN | IMR_RBAEEN)) &&
377      (sonic_read_register( rp, SONIC_REG_ISR ) & (ISR_PKTRX | ISR_RBAE))) {
378    sonic_write_register(
379       rp,
380       SONIC_REG_IMR,
381       sonic_read_register( rp, SONIC_REG_IMR) & ~(IMR_PRXEN | IMR_RBAEEN)
382    );
383    dp->rxInterrupts++;
384    rtems_event_send (dp->iface->rxproc, INTERRUPT_EVENT);
385  }
386
387  /*
388   * Packet started, transmitter done or transmitter error?
389   */
390  if ((sonic_read_register( rp, SONIC_REG_IMR ) & (IMR_PINTEN | IMR_PTXEN | IMR_TXEREN))
391   && (sonic_read_register( rp, SONIC_REG_ISR ) & (ISR_PINT | ISR_TXDN | ISR_TXER))) {
392    sonic_write_register(
393       rp,
394       SONIC_REG_IMR,
395       sonic_read_register( rp, SONIC_REG_IMR) &
396                  ~(IMR_PINTEN | IMR_PTXEN | IMR_TXEREN)
397    );
398    dp->txInterrupts++;
399    rtems_event_send (dp->txWaitTid, INTERRUPT_EVENT);
400  }
401}
402
403/*
404 ******************************************************************
405 *                                                                *
406 *                      Transmitter Routines                      *
407 *                                                                *
408 ******************************************************************
409 */
410
411/*
412 * Soak up transmit descriptors that have been sent.
413 */
414
415SONIC_STATIC void sonic_retire_tda (struct sonic *dp)
416{
417  rtems_unsigned16 status;
418  unsigned int collisions;
419
420  /*
421   * Repeat for all completed transmit descriptors.
422   */
423  while ((dp->tdaActiveCount != 0)
424      && ((status = dp->tdaTail->status) != 0)) {
425
426printf( "retire TDA %p (0x%04x)\n", dp->tdaTail, status );
427    /*
428     * Check for errors which stop the transmitter.
429     */
430    if (status & (TDA_STATUS_EXD |
431        TDA_STATUS_EXC |
432        TDA_STATUS_FU |
433        TDA_STATUS_BCM)) {
434      /*
435       * Restart the transmitter if there are
436       * packets waiting to go.
437       */
438      rtems_unsigned16 link;
439      link = *(dp->tdaTail->linkp);
440
441      if ((link & TDA_LINK_EOL) == 0) {
442        void *rp = dp->sonic;
443
444        sonic_write_register( rp, SONIC_REG_CTDA, link );
445        sonic_write_register( rp, SONIC_REG_CR, CR_TXP );
446      }
447    }
448
449    /*
450     * Update network statistics
451     */
452    collisions = (status & TDA_STATUS_COLLISION_MASK) >> TDA_STATUS_COLLISION_SHIFT;
453    if (collisions) {
454      if (collisions == 1)
455        dp->txSingleCollision++;
456      else
457        dp->txMultipleCollision++;
458      dp->txCollision += collisions;
459    }
460    if (status & TDA_STATUS_EXC)
461      dp->txExcessiveCollision++;
462    if (status & TDA_STATUS_OWC)
463      dp->txLateCollision++;
464    if (status & TDA_STATUS_EXD)
465      dp->txExcessiveDeferral++;
466    if (status & TDA_STATUS_DEF)
467      dp->txDeferred++;
468    if (status & TDA_STATUS_FU)
469      dp->txUnderrun++;
470    if (status & TDA_STATUS_CRSL)
471      dp->txLostCarrier++;
472
473    /*
474     * Free the packet
475     */
476    dp->tdaActiveCount--;
477    free_p ((struct mbuf **)&dp->tdaTail->mbufp);
478
479/*  XXX this does not help when you wrap
480    dp->tdaTail->frag_count        = 1;
481    dp->tdaTail->frag[0].frag_link = LSW(dp->tdaTail->link_pad);
482*/
483
484    /*
485     * Move to the next transmit descriptor
486     */
487    dp->tdaTail = dp->tdaTail->next;
488printf( "next TDA %p\n", dp->tdaTail );
489  }
490}
491
492/*
493 * Send raw packet (caller provides header).
494 * This code runs in the context of the interface transmit
495 * task (most packets)  or in the context of the network
496 * task (for ARP requests).
497 */
498
499SONIC_STATIC int sonic_raw (struct iface *iface, struct mbuf **bpp)
500{
501  struct sonic *dp = &sonic[iface->dev];
502  void *rp = dp->sonic;
503  struct mbuf *bp;
504  TransmitDescriptorPointer_t tdp;
505  volatile struct TransmitDescriptorFragLink *fp;
506  unsigned int packetSize;
507  int i;
508  static char padBuf[64];
509
510  /*
511   * Update the log.
512   */
513  iface->rawsndcnt++;
514  iface->lastsent = secclock ();
515  dump (iface, IF_TRACE_OUT, *bpp);
516
517  /*
518   * It would not do to have two tasks active in the transmit
519   * loop at the same time.
520   * The blocking is simple-minded since the odds of two tasks
521   * simultaneously attempting to use this code are low.  The only
522   * way that two tasks can try to run here is:
523   *  1) Task A enters this code and ends up having to
524   *     wait for a transmit buffer descriptor.
525   *  2) Task B gains control and tries to transmit a packet.
526   * The RTEMS/KA9Q scheduling semaphore ensures that there
527   * are no race conditions associated with manipulating the
528   * txWaitTid variable.
529   */
530  if (dp->txWaitTid) {
531    dp->txRawWait++;
532    while (dp->txWaitTid)
533      rtems_ka9q_ppause (10);
534  }
535
536  /*
537   * Free up transmit descriptors.
538   */
539  sonic_retire_tda (dp);
540
541  /*
542   * Wait for transmit descriptor to become available.
543   */
544  if (dp->tdaActiveCount == dp->tdaCount) {
545puts( "Wait for more TDAs" );
546    /*
547     * Find out who we are
548     */
549    if (dp->txWaitTid == 0)
550      rtems_task_ident (RTEMS_SELF, 0, &dp->txWaitTid);
551
552    /*
553     * Clear old events.
554     */
555    sonic_write_register( rp, SONIC_REG_ISR, ISR_PINT | ISR_TXDN | ISR_TXER );
556
557    /*
558     * Wait for transmit descriptor to become available.
559     * Note that the transmit descriptors are checked
560     * *before* * entering the wait loop -- this catches
561     * the possibility that a transmit descriptor became
562     * available between the `if' the started this block,
563     * and the clearing of the interrupt status register.
564     */
565    sonic_retire_tda (dp);
566    while (dp->tdaActiveCount == dp->tdaCount) {
567      /*
568       * Enable transmitter interrupts.
569       */
570      sonic_write_register(
571         rp,
572         SONIC_REG_IMR,
573         sonic_read_register( rp, SONIC_REG_IMR) |
574                (IMR_PINTEN | IMR_PTXEN | IMR_TXEREN)
575      );
576
577      /*
578       * Wait for interrupt
579       */
580      rtems_ka9q_event_receive (INTERRUPT_EVENT,
581            RTEMS_WAIT|RTEMS_EVENT_ANY,
582            RTEMS_NO_TIMEOUT);
583      sonic_write_register( rp, SONIC_REG_ISR, ISR_PINT | ISR_TXDN | ISR_TXER );
584      sonic_retire_tda (dp);
585    }
586  }
587
588  /*
589   * Get the head of the packet mbuf chain.
590   */
591  bp = *bpp;
592
593  /*
594   * Fill in the transmit descriptor fragment descriptors.
595   * ===CACHE===
596   * If data cache is operating in write-back mode, flush cached
597   * data to memory.
598   */
599  tdp = dp->tdaHead->next;
600  tdp->mbufp = bp;
601  packetSize = 0;
602  fp = tdp->frag;
603  for (i = 0 ; i < MAXIMUM_FRAGS_PER_DESCRIPTOR ; i++, fp++) {
604    fp->frag_lsw = LSW(bp->data);
605    fp->frag_msw = MSW(bp->data);
606    fp->frag_size = bp->cnt;
607    packetSize += bp->cnt;
608
609#if (SONIC_DEBUG & SONIC_DEBUG_FRAGMENTS)
610    printf( "fp %p 0x%04x%04x %d\n",
611      fp, fp->frag_msw, fp->frag_lsw, fp->frag_size );
612#endif
613    /*
614     * Break out of the loop if this mbuf is the last in the frame.
615     */
616    if ((bp = bp->next) == NULL)
617      break;
618  }
619
620  /*
621   * Pad short packets.
622   */
623  if  ((packetSize < 64) && (i < MAXIMUM_FRAGS_PER_DESCRIPTOR)) {
624    int padSize = 64 - packetSize;
625    fp++;
626    fp->frag_lsw = LSW(padBuf);
627    fp->frag_msw = MSW(padBuf);
628    fp->frag_size = padSize;
629#if (SONIC_DEBUG & SONIC_DEBUG_FRAGMENTS)
630    printf( "PAD fp %p 0x%04x%04x %d\n",
631         fp, fp->frag_msw, fp->frag_lsw, fp->frag_size );
632#endif
633    packetSize += padSize;
634    i++;
635  }
636
637  /*
638   * Fill Transmit Descriptor
639   */
640  tdp->pkt_size = packetSize;
641  tdp->frag_count = i + 1;
642  tdp->status = 0;
643
644  /*
645   * Chain onto list and start transmission.
646   */
647
648  tdp->linkp = &(fp+1)->frag_link;
649  *tdp->linkp = LSW(tdp->next) | TDA_LINK_EOL;
650  *dp->tdaHead->linkp &= ~TDA_LINK_EOL;
651  dp->tdaActiveCount++;
652  dp->tdaHead = tdp;
653
654  sonic_write_register(
655     rp,
656     SONIC_REG_IMR,
657     sonic_read_register( rp, SONIC_REG_IMR) |
658            (IMR_PINTEN | IMR_PTXEN | IMR_TXEREN)
659  );
660  sonic_write_register( rp, SONIC_REG_CR, CR_TXP );
661
662  /*
663   * Let KA9Q know the packet is on the way
664   */
665
666  dp->txWaitTid = 0;
667  *bpp = NULL;
668  return 0;
669}
670
671/*
672 ******************************************************************
673 *                                                                *
674 *                        Receiver Routines                       *
675 *                                                                *
676 ******************************************************************
677 */
678
679/*
680 * Wait for SONIC to hand over a Receive Descriptor.
681 */
682
683SONIC_STATIC void sonic_rda_wait(
684  struct sonic *dp,
685  ReceiveDescriptorPointer_t rdp
686)
687{
688  int i;
689  void *rp = dp->sonic;
690
691  /*
692   * Wait for Receive Descriptor.
693   * The order of the tests is very important.
694   *    The RDA is checked after RBAE is detected.  This ensures that
695   *    the driver processes all RDA entries before reusing the RRA
696   *    entry holding the giant packet.
697   *    The event wait is done after the RDA and RBAE checks.  This
698   *    catches the possibility that a Receive Descriptor became ready
699   *    between the call to this function and the clearing of the
700   *    interrupt status register bit.
701   */
702  for (;;) {
703    /*
704     * Has a giant packet arrived?
705     * The National DP83932C data sheet is very vague on what
706     * happens under this condition.  The description of the
707     * Interrupt Status Register (Section 4.3.6) states,
708     * ``Reception is aborted and the SONIC fetches the next
709     * available resource descriptors in the RRA.  The buffer
710     * space is not re-used and an RDA is not setup for the
711     * truncated packet.''
712     * I take ``Reception is aborted''  to mean that the RXEN
713     * bit in the Command Register is cleared and must be set
714     * by the driver to begin reception again.
715     * Unfortunately, an alternative interpretation could be
716     * that only reception of the current packet is aborted.
717     * This would be more difficult to recover from....
718     */
719    if (sonic_read_register( rp, SONIC_REG_ISR ) & ISR_RBAE) {
720      /*
721       * One more check to soak up any Receive Descriptors
722       * that may already have been handed back to the driver.
723       */
724      if (rdp->in_use == RDA_IN_USE)
725        break;
726
727      /*
728       * Check my interpretation of the SONIC manual.
729       */
730      if (sonic_read_register( rp, SONIC_REG_CR ) & CR_RXEN)
731        rtems_panic ("SONIC RBAE/RXEN");
732
733      /*
734       * Update statistics
735       */
736      dp->rxGiant++;
737
738      /*
739       * Reuse receive buffer.
740       * Again, the manual is subject to interpretation.  The
741       * RRP register is described as, `the lower address of
742       * the next descriptor the SONIC will read.''
743       * Since, acording to the ISR/RBAE notes, the SONIC has
744       * ``fetched the next available resource descriptor in
745       * the RRA'', I interpret this to mean that that the
746       * driver has to move the RRP back *two* entries to
747       * reuse the receive buffer holding the giant packet.
748       */
749      for (i = 0 ; i < 2 ; i++) {
750        if (sonic_read_register( rp, SONIC_REG_RRP ) ==
751            sonic_read_register( rp, SONIC_REG_RSA ))
752          sonic_write_register(
753            rp,
754            SONIC_REG_RRP,
755            sonic_read_register( rp, SONIC_REG_REA )
756          );
757          sonic_write_register(
758             rp,
759             SONIC_REG_RRP,
760             sonic_read_register(rp, SONIC_REG_RRP) - sizeof(ReceiveResource_t)
761          );
762      }
763
764      /*
765       * Restart reception
766       */
767      sonic_write_register( rp, SONIC_REG_ISR, ISR_RBAE );
768      sonic_write_register( rp, SONIC_REG_CR, CR_RXEN );
769    }
770
771    /*
772     * Clear old packet-received events.
773     */
774    sonic_write_register( rp, SONIC_REG_ISR, ISR_PKTRX );
775
776    /*
777     * Has Receive Descriptor become available?
778     */
779    if (rdp->in_use == RDA_IN_USE)
780      break;
781
782    /*
783     * Enable interrupts.
784     */
785    sonic_write_register(
786       rp,
787       SONIC_REG_IMR,
788       sonic_read_register( rp, SONIC_REG_IMR) | (IMR_PRXEN | IMR_RBAEEN)
789    );
790
791    /*
792     * Wait for interrupt.
793     */
794    rtems_ka9q_event_receive (INTERRUPT_EVENT,
795            RTEMS_WAIT|RTEMS_EVENT_ANY,
796            RTEMS_NO_TIMEOUT);
797  }
798}
799
800/*
801 * SCC reader task
802 */
803
804SONIC_STATIC void sonic_rx (int dev, void *p1, void *p2)
805{
806  struct iface *iface = (struct iface *)p1;
807  struct sonic *dp = (struct sonic *)p2;
808  void *rp = dp->sonic;
809  struct mbuf *bp;
810  rtems_unsigned16 status;
811  ReceiveDescriptorPointer_t rdp;
812  ReceiveResourcePointer_t rwp, rea;
813  rtems_unsigned16 newMissedTally, oldMissedTally;
814  int continuousCount;
815
816  rwp = dp->rsa;
817  rea = rwp;
818  rdp = dp->rda; /* XXX was rdp_last */
819
820  /*
821   * Start the receiver
822   */
823  oldMissedTally = sonic_read_register( rp, SONIC_REG_MPT );
824  sonic_write_register( rp, SONIC_REG_CR, CR_RRRA );
825  sonic_write_register( rp, SONIC_REG_CR, CR_RXEN );
826
827  /*
828   * Input packet handling loop
829   */
830  continuousCount = 0;
831  for (;;) {
832    /*
833     * Wait till SONIC supplies a Receive Descriptor.
834     */
835    if (rdp->in_use == RDA_FREE) {
836      continuousCount = 0;
837      sonic_rda_wait (dp, rdp);
838    }
839
840/* printf( "Incoming packet %p\n", rdp ); */
841
842    /*
843     * Check that packet is valid
844     */
845    status = rdp->status;
846    if (status & RDA_STATUS_PRX) {
847      struct mbuf **mbp;
848      void *p;
849
850/* printf( "Valid packet\n" ); */
851      /*
852       * Get the mbuf pointer
853       */
854      p = PTR(rdp->pkt_msw, rdp->pkt_lsw);
855      mbp = (struct mbuf **)p - 1;
856      bp = *mbp;
857
858      /*
859       * Pass the packet up the chain.
860       * The mbuf count is reduced to remove
861       * the frame check sequence at the end
862       * of the packet.
863       * ===CACHE===
864       * Invalidate cache entries for this memory.
865       */
866      bp->cnt = rdp->byte_count - sizeof (uint32);
867/* printf( "Routing the packet\n" ); */
868      net_route (iface, &bp);
869
870      /*
871       * Give the network code a chance to digest the
872       * packet.  This guards against a flurry of
873       * incoming packets (usually an ARP storm) from
874       * using up all the available memory.
875       */
876      if (++continuousCount >= dp->rdaCount)
877        kwait_null ();
878
879      /*
880       * Sanity check that Receive Resource Area is
881       * still in sync with Receive Descriptor Area
882       * The buffer reported in the Receive Descriptor
883       * should be the same as the buffer in the Receive
884       * Resource we are about to reuse.
885       */
886/* XXX figure out whether this is valid or not */
887#if 0
888      if ((LSW(p) != rwp->buff_ptr_lsw)
889       || (MSW(p) != rwp->buff_ptr_msw))
890        rtems_panic ("SONIC RDA/RRA");
891#endif
892
893      /*
894       * Allocate a new mbuf.
895       */
896      bp = ambufw (RBUF_SIZE);
897      mbp = (struct mbuf **)bp->data;
898      bp->data += sizeof *mbp;
899      *mbp = bp;
900
901      /*
902       * Reuse Receive Resource.
903       */
904      rwp->buff_ptr_lsw = LSW(bp->data);
905      rwp->buff_ptr_msw = MSW(bp->data);
906      rwp++;
907      if (rwp == rea)
908        rwp = dp->rsa;
909      sonic_write_register( rp, SONIC_REG_RWP , LSW(rwp) );
910
911      /*
912       * Tell the SONIC to reread the RRA.
913       */
914      if (sonic_read_register( rp, SONIC_REG_ISR ) & ISR_RBE)
915        sonic_write_register( rp, SONIC_REG_ISR, ISR_RBE );
916    }
917    else {
918      if (status & RDA_STATUS_COL)
919        dp->rxCollision++;
920      if (status & RDA_STATUS_FAER)
921        dp->rxNonOctet++;
922      else if (status & RDA_STATUS_CRCR)
923        dp->rxBadCRC++;
924    }
925
926    /*
927     * Count missed packets
928     */
929    newMissedTally = sonic_read_register( rp, SONIC_REG_MPT );
930    if (newMissedTally != oldMissedTally) {
931      dp->rxMissed += (newMissedTally - oldMissedTally) & 0xFFFF;
932      newMissedTally = oldMissedTally;
933    }
934
935    /*
936     * Move to next receive descriptor
937     */
938    rdp->link |= RDA_LINK_EOL;
939    rdp->in_use = RDA_FREE;
940    rdp = rdp->next;
941    rdp->link &= ~RDA_LINK_EOL;
942  }
943}
944
945/*
946 ******************************************************************
947 *                                                                *
948 *                     Initialization Routines                    *
949 *                                                                *
950 ******************************************************************
951 */
952
953/*
954 * Initialize the SONIC hardware
955 */
956SONIC_STATIC void sonic_initialize_hardware(
957  struct sonic *dp,
958  int broadcastFlag
959)
960{
961  void *rp = dp->sonic;
962  int i;
963  unsigned char *hwaddr;
964  rtems_isr_entry old_handler;
965  TransmitDescriptorPointer_t tdp;
966  ReceiveDescriptorPointer_t ordp, rdp;
967  ReceiveResourcePointer_t rwp, rea;
968  struct mbuf *bp;
969  CamDescriptorPointer_t cdp;
970
971  /*
972   *  The Revision B SONIC has a horrible bug known as the "Zero
973   *  Length Packet bug".  The initial board used to develop this
974   *  driver had a newer revision of the SONIC so there was no reason
975   *  to check for this.  If you have the Revision B SONIC chip, then
976   *  you need to add some code to the RX path to handle this weirdness.
977   */
978
979  if ( sonic_read_register( rp, SONIC_REG_SR ) < SONIC_REVISION_C ) {
980    rtems_fatal_error_occurred( 0x0BADF00D );  /* don't eat this part :) */
981  }
982 
983  /*
984   *  Set up circular linked list in Transmit Descriptor Area.
985   *  Use the PINT bit in the transmit configuration field to
986   *  request an interrupt on every other transmitted packet.
987   *
988   *  NOTE: sonic_allocate() zeroes all of the memory allocated.
989   */
990
991  dp->tdaActiveCount = 0;
992  dp->tdaTail = sonic_allocate(dp->tdaCount * sizeof *tdp);
993#if (SONIC_DEBUG & SONIC_DEBUG_MEMORY)
994  printf( "tdaTail = %p\n", dp->tdaTail );
995#endif
996  tdp = dp->tdaTail;
997  for (i = 0 ; i < dp->tdaCount ; i++) {
998    /*
999     *  status, pkt_config, pkt_size, and all fragment fields
1000     *  are set to zero by sonic_allocate.
1001     */
1002
1003/* XXX not used by other drivers we looked at
1004    if (i & 1)
1005      tdp->pkt_config = TDA_CONFIG_PINT;
1006*/
1007
1008    tdp->frag_count        = 1;
1009    tdp->frag[0].frag_link = LSW(tdp + 1);
1010    tdp->link_pad          = LSW(tdp + 1) | TDA_LINK_EOL;
1011    tdp->linkp             = &((tdp + 1)->frag[0].frag_link);
1012    tdp->next              = (TransmitDescriptor_t *)(tdp + 1);
1013    tdp++;
1014  }
1015  tdp--;
1016  dp->tdaHead = tdp;
1017  tdp->link_pad = LSW(dp->tdaTail) | TDA_LINK_EOL;
1018  tdp->next = (TransmitDescriptor_t *)dp->tdaTail;
1019  tdp->linkp = &dp->tdaTail->frag[0].frag_link;
1020
1021  /*
1022   *  Set up circular linked list in Receive Descriptor Area.
1023   *  Leaves dp->rda pointing at the `beginning' of the list.
1024   *
1025   *  NOTE: The RDA and CDP must have the same MSW for their addresses.
1026   */
1027
1028  dp->rda = sonic_allocate(
1029              (dp->rdaCount * sizeof(ReceiveDescriptor_t)) + 
1030                sizeof(CamDescriptor_t) );
1031  dp->cdp = (CamDescriptorPointer_t) ((unsigned char *)dp->rda +
1032        (dp->rdaCount * sizeof(ReceiveDescriptor_t)));
1033#if (SONIC_DEBUG & SONIC_DEBUG_MEMORY)
1034  printf( "rda area = %p\n", dp->rda );
1035  printf( "cdp area = %p\n", dp->cdp );
1036#endif
1037
1038  ordp = rdp = dp->rda;
1039  for (i = 0 ; i < dp->rdaCount ; i++) {
1040    /*
1041     *  status, byte_count, pkt_ptr0, pkt_ptr1, and seq_no are set
1042     *  to zero by sonic_allocate.
1043     */
1044    rdp->link   = LSW(rdp + 1);
1045    rdp->in_use = RDA_FREE;
1046    rdp->next   = (ReceiveDescriptor_t *)(rdp + 1);
1047    ordp = rdp;
1048    rdp++;
1049  }
1050  /*
1051   *  Link the last desriptor to the 1st one and mark it as the end
1052   *  of the list.
1053   */
1054  ordp->next  = dp->rda;
1055  ordp->link |= RDA_LINK_EOL;
1056  dp->rdp_last = rdp;
1057 
1058  /*
1059   * Allocate the receive resource area.
1060   * In accordance with National Application Note 746, make the
1061   * receive resource area bigger than the receive descriptor area.
1062   * This has the useful side effect of making the receive resource
1063   * area big enough to hold the CAM descriptor area.
1064   */
1065
1066  dp->rsa = sonic_allocate((dp->rdaCount + RRA_EXTRA_COUNT) * sizeof *dp->rsa);
1067#if (SONIC_DEBUG & SONIC_DEBUG_MEMORY)
1068  printf( "rsa area = %p\n", dp->rsa );
1069#endif
1070
1071  /*
1072   *  Set up list in Receive Resource Area.
1073   *  Allocate space for incoming packets.
1074   */
1075
1076  rwp = dp->rsa;
1077  for (i = 0 ; i < (dp->rdaCount + RRA_EXTRA_COUNT) ; i++, rwp++) {
1078    struct mbuf **mbp;
1079
1080    /*
1081     * Allocate memory for buffer.
1082     * Place a pointer to the mbuf at the beginning of the buffer
1083     * so we can find the mbuf when the SONIC returns the buffer
1084     * to the driver.
1085     */
1086    bp = ambufw (RBUF_SIZE);
1087    mbp = (struct mbuf **)bp->data;
1088    bp->data += sizeof *mbp;
1089    *mbp = bp;
1090
1091    /*
1092     * Set up RRA entry
1093     */
1094
1095    rwp->buff_ptr_lsw = LSW(bp->data);
1096    rwp->buff_ptr_msw = MSW(bp->data);
1097    rwp->buff_wc_lsw = RBUF_WC;
1098    rwp->buff_wc_msw = 0;
1099  }
1100  rea = rwp;
1101
1102  /*
1103   * Issue a software reset.
1104   */
1105  sonic_write_register( rp, SONIC_REG_CR, CR_RST | CR_STP | CR_RXDIS | CR_HTX );
1106
1107  /*
1108   * Set up data configuration registers.
1109   */
1110  sonic_write_register( rp, SONIC_REG_DCR, SONIC_DCR );
1111  sonic_write_register( rp, SONIC_REG_DCR2, SONIC_DC2 );
1112
1113  sonic_write_register( rp, SONIC_REG_CR, CR_STP | CR_RXDIS | CR_HTX );
1114
1115  /*
1116   * Mask all interrupts
1117   */
1118  sonic_write_register( rp, SONIC_REG_IMR, 0x3fff );
1119
1120  /*
1121   * Clear outstanding interrupts.
1122   */
1123  sonic_write_register( rp, SONIC_REG_ISR, 0x7FFF );
1124
1125  /*
1126   *  Clear the tally counters
1127   */
1128
1129  sonic_write_register( rp, SONIC_REG_CRCT, 0xFFFF );
1130  sonic_write_register( rp, SONIC_REG_FAET, 0xFFFF );
1131  sonic_write_register( rp, SONIC_REG_MPT, 0xFFFF );
1132  sonic_write_register( rp, SONIC_REG_RSC, 0 );
1133
1134  /*
1135   *  Set the Receiver mode
1136   *
1137   *  Enable/disable reception of broadcast packets
1138   */
1139
1140  if (broadcastFlag)
1141    sonic_write_register( rp, SONIC_REG_RCR, RCR_BRD );
1142  else
1143    sonic_write_register( rp, SONIC_REG_RCR, 0 );
1144
1145  /*
1146   * Set up Resource Area pointers
1147   */
1148
1149  sonic_write_register( rp, SONIC_REG_URRA, MSW(dp->rsa) );
1150  sonic_write_register( rp, SONIC_REG_RSA, LSW(dp->rsa) );
1151
1152  sonic_write_register( rp, SONIC_REG_REA, LSW(rea) );
1153
1154  sonic_write_register( rp, SONIC_REG_RRP, LSW(dp->rsa) );
1155  sonic_write_register( rp, SONIC_REG_RWP, LSW(dp->rsa) ); /* XXX was rea */
1156
1157  sonic_write_register( rp, SONIC_REG_URDA, MSW(dp->rda) );
1158  sonic_write_register( rp, SONIC_REG_CRDA, LSW(dp->rda) );
1159
1160  sonic_write_register( rp, SONIC_REG_UTDA, MSW(dp->tdaTail) );
1161  sonic_write_register( rp, SONIC_REG_CTDA, LSW(dp->tdaTail) );
1162
1163  /*
1164   * Set End Of Buffer Count register to the value recommended
1165   * in Note 1 of Section 3.4.4.4 of the SONIC data sheet.
1166   */
1167
1168  sonic_write_register( rp, SONIC_REG_EOBC, RBUF_WC - 2 );
1169
1170  /*
1171   *  Issue the load RRA command
1172   */
1173
1174  sonic_write_register( rp, SONIC_REG_CR, CR_RRRA );
1175  while (sonic_read_register( rp, SONIC_REG_CR ) & CR_RRRA)
1176    continue;
1177
1178  /*
1179   * Remove device reset
1180   */
1181
1182  sonic_write_register( rp, SONIC_REG_CR, 0 );
1183
1184  /*
1185   *  Set up the SONIC CAM with our hardware address.
1186   */
1187
1188  hwaddr = dp->iface->hwaddr;
1189  cdp = dp->cdp;
1190
1191#if (SONIC_DEBUG & SONIC_DEBUG_CAM)
1192  printf( "hwaddr: %2x:%2x:%2x:%2x:%2x:%2x\n",
1193     hwaddr[0], hwaddr[1], hwaddr[2], hwaddr[3], hwaddr[4], hwaddr[5] );
1194#endif
1195
1196  cdp->cep  = 0;                     /* Fill first and only entry in CAM */
1197  cdp->cap0 = hwaddr[1] << 8 | hwaddr[0];
1198  cdp->cap1 = hwaddr[3] << 8 | hwaddr[2];
1199  cdp->cap2 = hwaddr[5] << 8 | hwaddr[4];
1200  cdp->ce   = 0x0001;                /* Enable first entry in CAM */
1201
1202  sonic_write_register( rp, SONIC_REG_CDC, 1 );      /* 1 entry in CDA */
1203  sonic_write_register( rp, SONIC_REG_CDP, LSW(cdp) );
1204  sonic_write_register( rp, SONIC_REG_CR,  CR_LCAM );  /* Load the CAM */
1205
1206  while (sonic_read_register( rp, SONIC_REG_CR ) & CR_LCAM)
1207    continue;
1208
1209  /*
1210   * Verify that CAM was properly loaded.
1211   */
1212
1213  sonic_write_register( rp, SONIC_REG_CR, CR_RST | CR_STP | CR_RXDIS | CR_HTX );
1214
1215#if (SONIC_DEBUG & SONIC_DEBUG_CAM)
1216  sonic_write_register( rp, SONIC_REG_CEP, 0 );  /* Select first entry in CAM */
1217    printf ("Loaded Ethernet address into SONIC CAM.\n"
1218      "  Wrote %04x%04x%04x - %#x\n"
1219      "   Read %04x%04x%04x - %#x\n", 
1220        cdp->cap2, cdp->cap1, cdp->cap0, cdp->ce,
1221        sonic_read_register( rp, SONIC_REG_CAP2 ),
1222        sonic_read_register( rp, SONIC_REG_CAP1 ),
1223        sonic_read_register( rp, SONIC_REG_CAP0 ),
1224        sonic_read_register( rp, SONIC_REG_CE ));
1225#endif
1226
1227  sonic_write_register( rp, SONIC_REG_CEP, 0 );  /* Select first entry in CAM */
1228  if ((sonic_read_register( rp, SONIC_REG_CAP2 ) != cdp->cap2)
1229   || (sonic_read_register( rp, SONIC_REG_CAP1 ) != cdp->cap1)
1230   || (sonic_read_register( rp, SONIC_REG_CAP0 ) != cdp->cap0)
1231   || (sonic_read_register( rp, SONIC_REG_CE ) != cdp->ce)) {
1232    printf ("Failed to load Ethernet address into SONIC CAM.\n"
1233      "  Wrote %04x%04x%04x - %#x\n"
1234      "   Read %04x%04x%04x - %#x\n", 
1235        cdp->cap2, cdp->cap1, cdp->cap0, cdp->ce,
1236        sonic_read_register( rp, SONIC_REG_CAP2 ),
1237        sonic_read_register( rp, SONIC_REG_CAP1 ),
1238        sonic_read_register( rp, SONIC_REG_CAP0 ),
1239        sonic_read_register( rp, SONIC_REG_CE ));
1240    rtems_panic ("SONIC LCAM");
1241  }
1242
1243  sonic_write_register(rp, SONIC_REG_CR, CR_TXP | CR_RXEN | CR_STP);
1244
1245  /*
1246   * Attach SONIC interrupt handler
1247   */
1248  sonic_write_register( rp, SONIC_REG_IMR, 0 );
1249  old_handler = set_vector(sonic_interrupt_handler, dp->vector, 0);
1250
1251  /*
1252   * Remainder of hardware initialization is
1253   * done by the receive and transmit daemons.
1254   */
1255}
1256
1257/*
1258 * Attach an SONIC driver to the system
1259 * This is the only `extern' function in the driver.
1260 *
1261 * argv[0]: interface label, e.g. "rtems"
1262 * The remainder of the arguments are optional key/value pairs:
1263 * mtu ##                  --  maximum transmission unit, default 1500
1264 * broadcast y/n           -- accept or ignore broadcast packets, default yes
1265 * rbuf ##                 -- Set number of receive descriptor entries
1266 * tbuf ##                 -- Set number of transmit descriptor entries
1267 * ip ###.###.###.###      -- IP address
1268 * ether ##:##:##:##:##:## -- Ethernet address
1269 * reg ######              -- Address of SONIC device registers
1270 * vector ###              -- SONIC interrupt vector
1271 */
1272int
1273rtems_ka9q_driver_attach (int argc, char *argv[], void *p)
1274{
1275  struct sonic *dp;
1276  struct iface *iface;
1277  char *cp;
1278  int argIndex;
1279  int broadcastFlag;
1280  char cbuf[30];
1281
1282  /*
1283   * Find an unused entry
1284   */
1285  dp = sonic;
1286  for (;;) {
1287    if (dp == &sonic[NSONIC]) {
1288      printf ("No more SONIC devices.\n");
1289      return -1;
1290    }
1291    if (dp->iface == NULL)
1292      break;
1293    dp++;
1294  }
1295  if (if_lookup (argv[0]) != NULL) {
1296    printf ("Interface %s already exists\n", argv[0]);
1297    return -1;
1298  }
1299
1300  /*
1301   *  zero out the control structure
1302   */
1303
1304  memset( dp, 0, sizeof(struct sonic) );
1305
1306  /*
1307   * Create an inteface descriptor
1308   */
1309  iface = callocw (1, sizeof *iface);
1310  iface->name = strdup (argv[0]);
1311  iface->dev = dp - sonic;
1312
1313  /*
1314   * Set default values
1315   */
1316  broadcastFlag = 1;
1317  dp->txWaitTid = 0;
1318  dp->rdaCount = RDA_COUNT;
1319  dp->tdaCount = TDA_COUNT;
1320  iface->mtu = 1500;
1321  iface->addr = Ip_addr;
1322  iface->hwaddr = mallocw (EADDR_LEN);
1323  memset (iface->hwaddr, 0x08, EADDR_LEN);
1324  dp->sonic = (struct SonicRegisters *)SONIC_BASE_ADDRESS;
1325  dp->vector = SONIC_VECTOR;
1326
1327  /*
1328   * Parse remaining arguments
1329   */
1330  for (argIndex = 1 ; argIndex < (argc - 1) ; argIndex++) {
1331    if (strcmp ("mtu", argv[argIndex]) == 0) {
1332      iface->mtu = strtoul (argv[++argIndex], NULL, 0);
1333    }
1334    else if (strcmp ("broadcast", argv[argIndex]) == 0) {
1335      if (*argv[++argIndex] == 'n')
1336        broadcastFlag = 0;
1337    }
1338    else if (strcmp ("rbuf", argv[argIndex]) == 0) {
1339      /*
1340       * The minimum RDA count is 2.  A single-entry RDA
1341       * would be difficult to use since the SONIC does
1342       * not release (in_use = 0) the RDA that has the
1343       * EOL bit set.
1344       */
1345      dp->rdaCount = strtoul (argv[++argIndex], NULL, 0);
1346      if ((dp->rdaCount <= 1) || (dp->rdaCount > 200)) {
1347        printf ("RDA option (%d) is invalid.\n", dp->rdaCount);
1348        return -1;
1349      }
1350    }
1351    else if (strcmp ("tbuf", argv[argIndex]) == 0) {
1352      dp->tdaCount = strtoul (argv[++argIndex], NULL, 0);
1353      if ((dp->tdaCount <= 1) || (dp->tdaCount > 200)) {
1354        printf ("TDA option (%d) is invalid.\n", dp->tdaCount);
1355        return -1;
1356      }
1357    }
1358    else if (strcmp ("ip", argv[argIndex]) == 0) {
1359      iface->addr = resolve (argv[++argIndex]);
1360    }
1361    else if (strcmp ("ether", argv[argIndex]) == 0) {
1362      gether (iface->hwaddr, argv[++argIndex]);
1363    }
1364    else if (strcmp ("reg", argv[argIndex]) == 0) {
1365      dp->sonic = (struct SonicRegisters *)strtoul (argv[++argIndex], NULL, 0);
1366    }
1367    else if (strcmp ("vector", argv[argIndex]) == 0) {
1368      dp->vector = strtoul (argv[++argIndex], NULL, 0);
1369    }
1370    else {
1371      printf ("Argument %d (%s) is invalid.\n", argIndex, argv[argIndex]);
1372      return -1;
1373    }
1374  }
1375  printf ("Ethernet address: %s\n", pether (cbuf, iface->hwaddr));
1376  iface->raw = sonic_raw;
1377  iface->stop = sonic_stop;
1378  iface->show = sonic_show;
1379  dp->iface = iface;
1380  setencap (iface, "Ethernet");
1381
1382  /*
1383   * Set up SONIC hardware
1384   */
1385  sonic_initialize_hardware (dp, broadcastFlag);
1386
1387  /*
1388   * Chain onto list of interfaces
1389   */
1390  iface->next = Ifaces;
1391  Ifaces = iface;
1392
1393  /*
1394   * Start I/O daemons
1395   */
1396  cp = if_name (iface, " tx");
1397  iface->txproc = newproc (cp, 2048, if_tx, iface->dev, iface, NULL, 0);
1398  free (cp);
1399  cp = if_name (iface, " rx");
1400  iface->rxproc = newproc (cp, 2048, sonic_rx, iface->dev, iface, dp, 0);
1401  free (cp);
1402  return 0;
1403}
1404
1405#if (SONIC_DEBUG & SONIC_DEBUG_PRINT_REGISTERS)
1406#include <stdio.h>
1407
1408char SONIC_Reg_name[64][6]= {
1409    "CR",         /* 0x00 */
1410    "DCR",        /* 0x01 */
1411    "RCR",        /* 0x02 */
1412    "TCR",        /* 0x03 */
1413    "IMR",        /* 0x04 */
1414    "ISR",        /* 0x05 */
1415    "UTDA",       /* 0x06 */
1416    "CTDA",       /* 0x07 */
1417    "0x08",       /* 0x08 */
1418    "0x09",       /* 0x09 */
1419    "0x0A",       /* 0x0A */
1420    "0x0B",       /* 0x0B */
1421    "0x0C",       /* 0x0C */
1422    "URDA",       /* 0x0D */
1423    "CRDA",       /* 0x0E */
1424    "0x0F",       /* 0x0F */
1425    "0x10",       /* 0x10 */
1426    "0x11",       /* 0x11 */
1427    "0x12",       /* 0x12 */
1428    "EOBC",       /* 0x13 */
1429    "URRA",       /* 0x14 */
1430    "RSA",        /* 0x15 */
1431    "REA",        /* 0x16 */
1432    "RRP",        /* 0x17 */
1433    "RWP",        /* 0x18 */
1434    "0x19",       /* 0x19 */
1435    "0x1A",       /* 0x1A */
1436    "0x1B",       /* 0x1B */
1437    "0x1C",       /* 0x1C */
1438    "0x0D",       /* 0x1D */
1439    "0x1E",       /* 0x1E */
1440    "0x1F",       /* 0x1F */
1441    "0x20",       /* 0x20 */
1442    "CEP",        /* 0x21 */
1443    "CAP2",       /* 0x22 */
1444    "CAP1",       /* 0x23 */
1445    "CAP0",       /* 0x24 */
1446    "CE",         /* 0x25 */
1447    "CDP",        /* 0x26 */
1448    "CDC",        /* 0x27 */
1449    "SR",         /* 0x28 */
1450    "WT0",        /* 0x29 */
1451    "WT1",        /* 0x2A */
1452    "RSC",        /* 0x2B */
1453    "CRCT",       /* 0x2C */
1454    "FAET",       /* 0x2D */
1455    "MPT",        /* 0x2E */
1456    "MDT",        /* 0x2F */
1457    "0x30",       /* 0x30 */
1458    "0x31",       /* 0x31 */
1459    "0x32",       /* 0x32 */
1460    "0x33",       /* 0x33 */
1461    "0x34",       /* 0x34 */
1462    "0x35",       /* 0x35 */
1463    "0x36",       /* 0x36 */
1464    "0x37",       /* 0x37 */
1465    "0x38",       /* 0x38 */
1466    "0x39",       /* 0x39 */
1467    "0x3A",       /* 0x3A */
1468    "0x3B",       /* 0x3B */
1469    "0x3C",       /* 0x3C */
1470    "0x3D",       /* 0x3D */
1471    "0x3E",       /* 0x3E */
1472    "DCR2"        /* 0x3F */
1473};
1474#endif
1475void sonic_write_register(
1476  void       *base,
1477  unsigned32  regno,
1478  unsigned32  value
1479)
1480{
1481  volatile unsigned32 *p = base;
1482
1483#if (SONIC_DEBUG & SONIC_DEBUG_PRINT_REGISTERS)
1484  printf( "%p Write 0x%04x to %s (0x%02x)\n",
1485      &p[regno], value, SONIC_Reg_name[regno], regno );
1486  fflush( stdout );
1487#endif
1488  p[regno] = value;
1489}
1490
1491unsigned32 sonic_read_register(
1492  void       *base,
1493  unsigned32  regno
1494)
1495{
1496  volatile unsigned32 *p = base;
1497  unsigned32           value;
1498
1499  value = p[regno];
1500#if (SONIC_DEBUG & SONIC_DEBUG_PRINT_REGISTERS)
1501  printf( "%p Read 0x%04x from %s (0x%02x)\n",
1502      &p[regno], value, SONIC_Reg_name[regno], regno );
1503  fflush( stdout );
1504#endif
1505  return value;
1506}
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