source: rtems/c/src/lib/libbsp/powerpc/dmv177/include/dmv170.h @ dc104a4

4.104.114.84.95
Last change on this file since dc104a4 was dc104a4, checked in by Joel Sherrill <joel.sherrill@…>, on May 30, 1998 at 11:46:21 AM

Updated to current source and removed warnings.

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File size: 9.1 KB
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1/*  dmv170.h
2 *
3 *  This include file contains information pertaining to the DMV170.
4 *
5 *  NOTE:  Other than where absolutely required, this version currently
6 *         supports only the peripherals and bits used by the basic board
7 *         support package. This includes at least significant pieces of
8 *         the following items:
9 *
10 *           + UART Channels A and B
11 *
12 *  COPYRIGHT (c) 1989-1997.
13 *  On-Line Applications Research Corporation (OAR).
14 *  Copyright assigned to U.S. Government, 1994.
15 *
16 *  The license and distribution terms for this file may in
17 *  the file LICENSE in this distribution or at
18 *  http://www.OARcorp.com/rtems/license.html.
19 *
20 *  $Id$
21 */
22 
23#ifndef _INCLUDE_DMV170_h
24#define _INCLUDE_DMV170_h
25
26
27/*
28 *  DY-4 is out of their mind and uses a non-standard clock.
29 */
30
31#undef  MC68681_BAUD_RATE_MASK_9600
32#define MC68681_BAUD_RATE_MASK_9600
33
34#define DMV17x_MC68681_BAUD_RATE_MASK_9600
35
36#if 0
37#define MC68681_OFFSET_MULTIPLIER 8
38#endif
39
40#ifdef __cplusplus
41extern "C" {
42#endif
43
44/* Note:  Move address defs to the linker files. XXX */
45
46/* Real Time Clock Base Address */
47#define  DMV170_RTC_ADDRESS   (unsigned char *)0xf2c00000
48
49/* base address of the DUART(68681) */
50#define  DUART_ADDR     0xf2800000
51
52/* base address for the SCC (85C30) */ 
53#define  SCC_ADDR       0xfb000000
54
55#define DMV170_LOCAL_CONTROL_STATUS_REG                   0xf2400000
56#define DMV170_TIMER0_COUNT_INTERVAL_REG                  0xf2400008
57#define DMV170_TIMER1_COUNT_INTERVAL_REG                  0xf2400010
58#define DMV170_TIMER2_COUNT_INTERVAL_REG                  0xf2400018
59#define DMV170_TIMER_CONTROL_REG                          0xf2400020
60#define DMV170_CARD_RESORCE_REG                           0xf2400040
61
62#define DMV170_WRITE( _reg, _data ) \
63   *((volatile rtems_unsigned16 *)(_reg)) = (_data)
64
65#define DMV170_READ( _reg, _data ) \
66   (_data) = *((volatile rtems_unsigned16 *)(_reg))
67
68/*
69 *  The following defines the bits in the Local Control and Status Register.
70 */
71#define DMV170_IPLx_MASK                                  0x0007
72#define DMV170_MAXPACK_SENSE_MASK                         0x0008
73#define DMV170_MAXPACK_NOT_INSTALLED                      0x0008
74#define DMV170_MAXPACK_INSTALLED                          0x0000
75
76#define DMV170_MAXPACK_RESET_MASK                         0x0010
77#define DMV170_MAXPACK_RESET_NEGATE                       0x0010
78#define DMV170_MAXPACK_RESET_ASSERT                       0x0000
79#define DMV170_EEPROM_READ_WRITE_MASK                     0x0020
80#define DMV170_EEPROM_READ                                0x0020
81#define DMV170_EEPROM_WRITE                               0x0000
82#define DMV170_EEPROM_CLOCK_CTRL_MASK                     0x0040
83#define DMV170_EEPROM_CLOCK_ASSERT                        0x0040
84#define DMV170_EEPROM_CLOCK_NEGATE                        0x0000
85#define DMV170_EEPROM_DATA_MASK                           0x0080
86#define DMV170_EEPROM_DATA_HIGH                           0x0080
87#define DMV170_EEPROM_DATA_LOW                            0x0000
88
89/* Bits 8-10: 68040 Transfer Modifer Codes represent the Transfer
90 *            Modifier to be used on MAXPack Accesses.
91 *
92 * Bit 11   : 68040 Transfer Type (TT) 0:TT are both low 1:TT are both high
93 */
94
95#define DMV170_USER_LINK0_STATUS_MASK                     0x1000
96#define DMV170_USER_LINK0_OPEN                            0x1000
97#define DMV170_USER_LINK0_INSTALLED                       0x0000
98#define DMV170_LOWER_STATUS_LED_CONTROL_MASK              0x2000
99#define DMV170_LOWER_STATUS_LED_IS_OFF                    0x2000
100#define DMV170_LOWER_STATUS_LED_IS_ON                     0x0000
101#ifdef DMV176                                             
102       /* The following are not available for the DMV171 */
103#define DMV170_RAM_TYPE_MASK                              0x4000
104#define DMV170_RAM_TYPE_IS_DRAM                           0x4000
105#define DMV170_RAM_TYPE_IS_SRAM                           0x0000
106#define DMV170_IACK_VECTOR_AUTOVECTOR_MASK                0x8000
107#define DMV170_IACK_VECTOR_AUTOVECTOR_IS_VECTOR           0x8000
108#define DMV170_IACK_VECTOR_AUTOVECTOR_IS_NOT_VECTOR       0x0000
109#endif
110 
111/*
112 *  The following defines the bits in the Timer Control Register.
113 */
114#define DMV170_TIMER0_ENABLE_MASK                         0x0001
115#define DMV170_TIMER0_IS_ENABLED                          0x0001
116#define DMV170_TIMER0_IS_DISABLED                         0x0000
117#define DMV170_TIMER1_ENABLE_MASK                         0x0002
118#define DMV170_TIMER1_IS_ENABLED                          0x0002
119#define DMV170_TIMER1_IS_DISABLED                         0x0000
120#define DMV170_TIMER2_ENABLE_MASK                         0x0004
121#define DMV170_TIMER2_IS_ENABLED                          0x0004
122#define DMV170_TIMER2_IS_DISABLED                         0x0000
123#define DMV170_TIMER1_CLOCK_MASK                          0x0008
124#define DMV170_TIMER1_CLOCK_AT_TIMER0                     0x0008
125#define DMV170_TIMER1_CLOCK_AT_1MHZ                       0x0000
126
127#define DMV170_TIMER2_CLOCK_MASK                          0x0010
128#define DMV170_TIMER2_CLOCK_AT_TIMER0                     0x0010
129#define DMV170_TIMER2_CLOCK_AT_1MHZ                       0x0000
130#define DMV170_TIMER0_INTERRUPT_MASK                      0x0020
131#define DMV170_TIMER0_INTERRUPT_ENABLE                    0x0020
132#define DMV170_TIMER0_INTERRUPT_CLEAR                     0x0000
133#define DMV170_TIMER1_INTERRUPT_MASK                      0x0040
134#define DMV170_TIMER1_INTERRUPT_ENABLE                    0x0040
135#define DMV170_TIMER1_INTERRUPT_CLEAR                     0x0000
136#define DMV170_TIMER2_INTERRUPT_MASK                      0x0080
137#define DMV170_TIMER2_INTERRUPT_ENABLE                    0x0080
138#define DMV170_TIMER2_INTERRUPT_CLEAR                     0x0000
139
140
141
142/* The Following definethe bits for the Card Resource Register      */
143#define DMV170_DUART_INTERRUPT_MASK    0x0001  /* DUART Interrupt Sense Bit  */
144#define DMV170_DUART_INTERRUPT_NEGATE  0x0001
145#define DMV170_DUART_INTERRUPT_ASSERT  0x0000
146#define DMV170_SONIC_INTERRUPT_MASK    0x0002  /* SONIC Interrupt Sense Bit  */
147#define DMV170_SONIC_INTERRUPT_NEGATE  0x0002
148#define DMV170_SONIC_INTERRUPT_ASSERT  0x0000
149#define DMV170_SCSI_INTERRUPT_MASK     0x0004  /* SCSI Interrupt Sense Bit   */
150#define DMV170_SCSI_INTERRUPT_NEGATE   0x0004
151#define DMV170_SCSI_INTERRUPT_ASSERT   0x0000
152#define DMV170_SCC_INTERRUPT_MASK      0x0008  /* SCC Interrupt Sense Bit    */
153#define DMV170_SCC_INTERRUPT_NEGATE    0x0008
154#define DMV170_SCC_INTERRUPT_ASSERT    0x0000
155#define DMV170_SNOOP_ENABLE_MASK       0x0010  /* CPU Snoop Enable Bit       */
156#define DMV170_SNOOP_DISABLE           0x0010
157#define DMV170_SNOOP_ENABLE            0x0000
158#define DMV170_SONIC_RESET_MASK        0x0020  /* SONIC RESET Control        */
159#define DMV170_SONIC_RESET_CLEAR       0x0020
160#define DMV170_SONIC_RESET_HOLD        0x0000
161#define DMV170_NV64_WE_MASK            0x0040  /* 64-bit Non-Volital Memory  */
162#define DMV170_NV64_WRITE_ENABLE       0x0040  /* Write Enable               */
163#define DMV170_NV64_WRITE_DISABLE      0x0000
164#define DMV170_BOOT_NV16_MASK          0x0080  /* BOOT Device Type           */
165#define DMV170_BOOT_64_BIT             0x0080
166#define DMV170_BOOT_16_BIT             0x0000
167#define DMV170_DUART_INST_MASK         0x0100  /* DUART Sense Bit            */
168#define DMV170_DUART_INSTALLED         0x0100
169#define DMV170_DUART_NOT_INSTALLED     0x0000
170#define DMV170_SONIC_INST_MASK         0x0200  /* SONIC Sense Bit            */
171#define DMV170_SONIC_INSTALLED         0x0200
172#define DMV170_SONIC_NOT_INSTALLED     0x0000
173#define DMV170_16M_NV64_MASK           0x0400  /* 16 Mb of 64bit Flash Sense */
174#define DMV170_16Mb_FLASH_INSTALLED    0x0400
175#define DMV170_8Mb_FLASH_INSTALLED     0x0000
176#define DMV170_SCC_INST_MASK           0x0800  /* SCC Sense Bit              */
177#define DMV170_SCC_INSTALLED           0x0800
178#define DMV170_SCC_NOT_INSTALLED       0x0000
179#define DMV170_RTC_INST_MASK           0x1000  /* RTC Sense Bit              */
180#define DMV170_RTC_INSTALLED           0x1000
181#define DMV170_RTC_NOT_INSTALLED       0x0000
182#define DMV170_NV64_INST_MASK          0x2000  /* 64bit Non-Volital Mem Sense*/
183
184#define DMV170_64_BIT_NON_VOLITAL_MEM_INSTALLED           0x2000
185#define DMV170_64_BIT_NON_VOLITAL_MEM_NOT_INSTALLED       0x0000
186
187
188/*
189 * DUART Baud Rate Definations.
190 */
191#define DMV170_DUART_9621     MC68681_BAUD_RATE_MASK_600 /* close to 9600 */ 
192
193#define DMV170_RTC_FREQUENCY             0x0000
194
195
196/*
197 * CPU General Purpose Interrupt definations (PPC_IRQ_EXTERNAL).
198 * Note: For the interrupt level read the lower 3 bits of the
199 *       Local Control and Status Register.
200 */
201#define DMV170_IRQ_FIRST                       ( PPC_IRQ_LAST +  1 )
202
203#define DMV170_LIRQ0                           ( DMV170_IRQ_FIRST + 0 )
204#define DMV170_LIRQ1                           ( DMV170_IRQ_FIRST + 1 )
205#define DMV170_LIRQ2                           ( DMV170_IRQ_FIRST + 2 )
206#define DMV170_LIRQ3                           ( DMV170_IRQ_FIRST + 3 )
207#define DMV170_LIRQ4                           ( DMV170_IRQ_FIRST + 4 )
208#define DMV170_LIRQ5                           ( DMV170_IRQ_FIRST + 5 )
209
210#define MAX_BOARD_IRQS                         DMV170_LIRQ5
211#ifdef __cplusplus
212}
213#endif
214 
215#endif /* !_INCLUDE_DMV170_h */
216/* end of include file */
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