source: rtems/c/src/lib/libbsp/powerpc/dmv177/include/dmv170.h @ c932d85

4.104.114.84.95
Last change on this file since c932d85 was c932d85, checked in by Joel Sherrill <joel.sherrill@…>, on May 30, 1998 at 10:09:14 AM

New files -- from rtems-LM-980406 which was based on an RTEMS from 12/97.
This was called the dmv170 BSP in that source tree but since the DMV171
is now obsolete, we have transitioned to the DMV177 and have no intention
of checking compatibility with any other models.

  • Property mode set to 100644
File size: 9.1 KB
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1/*  dmv170.h
2 *
3 *  This include file contains information pertaining to the DMV170.
4 *
5 *  NOTE:  Other than where absolutely required, this version currently
6 *         supports only the peripherals and bits used by the basic board
7 *         support package. This includes at least significant pieces of
8 *         the following items:
9 *
10 *           + UART Channels A and B
11 *
12 *  COPYRIGHT (c) 1989-1997.
13 *  On-Line Applications Research Corporation (OAR).
14 *  Copyright assigned to U.S. Government, 1994.
15 *
16 *  The license and distribution terms for this file may in
17 *  the file LICENSE in this distribution or at
18 *  http://www.OARcorp.com/rtems/license.html.
19 *
20 *  $Id$
21 */
22 
23#ifndef _INCLUDE_DMV170_h
24#define _INCLUDE_DMV170_h
25
26
27/*
28 *  DY-4 is out of their mind and uses a non-standard clock.
29 */
30
31#undef  MC68681_BAUD_RATE_MASK_9600
32#define MC68681_BAUD_RATE_MASK_9600
33
34#define DMV17x_MC68681_BAUD_RATE_MASK_9600
35
36#if 0
37#define MC68681_OFFSET_MULTIPLIER 8
38#endif
39
40#ifdef __cplusplus
41extern "C" {
42#endif
43
44/* Note:  Move address defs to the linker files.                            */
45#define  DMV170_RTC_ADDRESS   0xf2c00000 /* Real Time clock Base Address*/
46#define  DUART_ADDR     0xf2800000  /* base address of the DUART(68681)     */
47#define  SCC_ADDR       0xfb000000  /* base address for the SCC (85C30)     */ 
48
49#define DMV170_LOCAL_CONTROL_STATUS_REG                   0xf2400000
50#define DMV170_TIMER0_COUNT_INTERVAL_REG                  0xf2400008
51#define DMV170_TIMER1_COUNT_INTERVAL_REG                  0xf2400010
52#define DMV170_TIMER2_COUNT_INTERVAL_REG                  0xf2400018
53#define DMV170_TIMER_CONTROL_REG                          0xf2400020
54#define DMV170_CARD_RESORCE_REG                           0xf2400040
55
56
57#define DMV170_WRITE( reg,data) \
58   *((volatile rtems_unsigned16 *)(reg)) = (data)
59
60#define DMV170_READ( reg, data ) \
61   (data) = *((volatile rtems_unsigned16 *)(reg))
62
63/*
64 *  The following defines the bits in the Local Control and Status Register.
65 */
66#define DMV170_IPLx_MASK                                  0x0007
67#define DMV170_MAXPACK_SENSE_MASK                         0x0008
68#define DMV170_MAXPACK_NOT_INSTALLED                      0x0008
69#define DMV170_MAXPACK_INSTALLED                          0x0000
70
71#define DMV170_MAXPACK_RESET_MASK                         0x0010
72#define DMV170_MAXPACK_RESET_NEGATE                       0x0010
73#define DMV170_MAXPACK_RESET_ASSERT                       0x0000
74#define DMV170_EEPROM_READ_WRITE_MASK                     0x0020
75#define DMV170_EEPROM_READ                                0x0020
76#define DMV170_EEPROM_WRITE                               0x0000
77#define DMV170_EEPROM_CLOCK_CTRL_MASK                     0x0040
78#define DMV170_EEPROM_CLOCK_ASSERT                        0x0040
79#define DMV170_EEPROM_CLOCK_NEGATE                        0x0000
80#define DMV170_EEPROM_DATA_MASK                           0x0080
81#define DMV170_EEPROM_DATA_HIGH                           0x0080
82#define DMV170_EEPROM_DATA_LOW                            0x0000
83
84/* Bits 8:10 68040 Transfer Modifer Codes represent the Transfer Modifier to be used on MAXPack Accesses. */
85/* Bit  11 68040 Transfer Type (TT) 0:TT are both low 1:TT are both high                                  */
86
87#define DMV170_USER_LINK0_STATUS_MASK                     0x1000
88#define DMV170_USER_LINK0_OPEN                            0x1000
89#define DMV170_USER_LINK0_INSTALLED                       0x0000
90#define DMV170_LOWER_STATUS_LED_CONTROL_MASK              0x2000
91#define DMV170_LOWER_STATUS_LED_IS_OFF                    0x2000
92#define DMV170_LOWER_STATUS_LED_IS_ON                     0x0000
93#ifdef DMV176                                             
94       /* The following are not available for the DMV171 */
95#define DMV170_RAM_TYPE_MASK                              0x4000
96#define DMV170_RAM_TYPE_IS_DRAM                           0x4000
97#define DMV170_RAM_TYPE_IS_SRAM                           0x0000
98#define DMV170_IACK_VECTOR_AUTOVECTOR_MASK                0x8000
99#define DMV170_IACK_VECTOR_AUTOVECTOR_IS_VECTOR           0x8000
100#define DMV170_IACK_VECTOR_AUTOVECTOR_IS_NOT_VECTOR       0x0000
101#endif
102 
103/*
104 *  The following defines the bits in the Timer Control Register.
105 */
106#define DMV170_TIMER0_ENABLE_MASK                         0x0001
107#define DMV170_TIMER0_IS_ENABLED                          0x0001
108#define DMV170_TIMER0_IS_DISABLED                         0x0000
109#define DMV170_TIMER1_ENABLE_MASK                         0x0002
110#define DMV170_TIMER1_IS_ENABLED                          0x0002
111#define DMV170_TIMER1_IS_DISABLED                         0x0000
112#define DMV170_TIMER2_ENABLE_MASK                         0x0004
113#define DMV170_TIMER2_IS_ENABLED                          0x0004
114#define DMV170_TIMER2_IS_DISABLED                         0x0000
115#define DMV170_TIMER1_CLOCK_MASK                          0x0008
116#define DMV170_TIMER1_CLOCK_AT_TIMER0                     0x0008
117#define DMV170_TIMER1_CLOCK_AT_1MHZ                       0x0000
118
119#define DMV170_TIMER2_CLOCK_MASK                          0x0010
120#define DMV170_TIMER2_CLOCK_AT_TIMER0                     0x0010
121#define DMV170_TIMER2_CLOCK_AT_1MHZ                       0x0000
122#define DMV170_TIMER0_INTERRUPT_MASK                      0x0020
123#define DMV170_TIMER0_INTERRUPT_ENABLE                    0x0020
124#define DMV170_TIMER0_INTERRUPT_CLEAR                     0x0000
125#define DMV170_TIMER1_INTERRUPT_MASK                      0x0040
126#define DMV170_TIMER1_INTERRUPT_ENABLE                    0x0040
127#define DMV170_TIMER1_INTERRUPT_CLEAR                     0x0000
128#define DMV170_TIMER2_INTERRUPT_MASK                      0x0080
129#define DMV170_TIMER2_INTERRUPT_ENABLE                    0x0080
130#define DMV170_TIMER2_INTERRUPT_CLEAR                     0x0000
131
132
133
134/* The Following definethe bits for the Card Resource Register      */
135#define DMV170_DUART_INTERRUPT_MASK    0x0001  /* DUART Interrupt Sense Bit  */
136#define DMV170_DUART_INTERRUPT_NEGATE  0x0001
137#define DMV170_DUART_INTERRUPT_ASSERT  0x0000
138#define DMV170_SONIC_INTERRUPT_MASK    0x0002  /* SONIC Interrupt Sense Bit  */
139#define DMV170_SONIC_INTERRUPT_NEGATE  0x0002
140#define DMV170_SONIC_INTERRUPT_ASSERT  0x0000
141#define DMV170_SCSI_INTERRUPT_MASK     0x0004  /* SCSI Interrupt Sense Bit   */
142#define DMV170_SCSI_INTERRUPT_NEGATE   0x0004
143#define DMV170_SCSI_INTERRUPT_ASSERT   0x0000
144#define DMV170_SCC_INTERRUPT_MASK      0x0008  /* SCC Interrupt Sense Bit    */
145#define DMV170_SCC_INTERRUPT_NEGATE    0x0008
146#define DMV170_SCC_INTERRUPT_ASSERT    0x0000
147#define DMV170_SNOOP_ENABLE_MASK       0x0010  /* CPU Snoop Enable Bit       */
148#define DMV170_SNOOP_DISABLE           0x0010
149#define DMV170_SNOOP_ENABLE            0x0000
150#define DMV170_SONIC_RESET_MASK        0x0020  /* SONIC RESET Control        */
151#define DMV170_SONIC_RESET_CLEAR       0x0020
152#define DMV170_SONIC_RESET_HOLD        0x0000
153#define DMV170_NV64_WE_MASK            0x0040  /* 64-bit Non-Volital Memory  */
154#define DMV170_NV64_WRITE_ENABLE       0x0040  /* Write Enable               */
155#define DMV170_NV64_WRITE_DISABLE      0x0000
156#define DMV170_BOOT_NV16_MASK          0x0080  /* BOOT Device Type           */
157#define DMV170_BOOT_64_BIT             0x0080
158#define DMV170_BOOT_16_BIT             0x0000
159#define DMV170_DUART_INST_MASK         0x0100  /* DUART Sense Bit            */
160#define DMV170_DUART_INSTALLED         0x0100
161#define DMV170_DUART_NOT_INSTALLED     0x0000
162#define DMV170_SONIC_INST_MASK         0x0200  /* SONIC Sense Bit            */
163#define DMV170_SONIC_INSTALLED         0x0200
164#define DMV170_SONIC_NOT_INSTALLED     0x0000
165#define DMV170_16M_NV64_MASK           0x0400  /* 16 Mb of 64bit Flash Sense */
166#define DMV170_16Mb_FLASH_INSTALLED    0x0400
167#define DMV170_8Mb_FLASH_INSTALLED     0x0000
168#define DMV170_SCC_INST_MASK           0x0800  /* SCC Sense Bit              */
169#define DMV170_SCC_INSTALLED           0x0800
170#define DMV170_SCC_NOT_INSTALLED       0x0000
171#define DMV170_RTC_INST_MASK           0x1000  /* RTC Sense Bit              */
172#define DMV170_RTC_INSTALLED           0x1000
173#define DMV170_RTC_NOT_INSTALLED       0x0000
174#define DMV170_NV64_INST_MASK          0x2000  /* 64bit Non-Volital Mem Sense*/
175
176#define DMV170_64_BIT_NON_VOLITAL_MEM_INSTALLED           0x2000
177#define DMV170_64_BIT_NON_VOLITAL_MEM_NOT_INSTALLED       0x0000
178
179
180/*
181 * DUART Baud Rate Definations.
182 */
183#define DMV170_DUART_9621     MC68681_BAUD_RATE_MASK_600 /* close to 9600 */ 
184
185#define DMV170_RTC_FREQUENCY             0x0000
186
187
188/*
189 * CPU General Purpose Interrupt definations (PPC_IRQ_EXTERNAL).
190 * Note: For the interrupt level read the lower 3 bits of the
191 *       Local Control and Status Register.
192 */
193#define DMV170_IRQ_FIRST                       ( PPC_IRQ_LAST +  1 )
194
195#define DMV170_LIRQ0                           ( DMV170_IRQ_FIRST + 0 )
196#define DMV170_LIRQ1                           ( DMV170_IRQ_FIRST + 1 )
197#define DMV170_LIRQ2                           ( DMV170_IRQ_FIRST + 2 )
198#define DMV170_LIRQ3                           ( DMV170_IRQ_FIRST + 3 )
199#define DMV170_LIRQ4                           ( DMV170_IRQ_FIRST + 4 )
200#define DMV170_LIRQ5                           ( DMV170_IRQ_FIRST + 5 )
201
202#define MAX_BOARD_IRQS                         DMV170_LIRQ5
203#ifdef __cplusplus
204}
205#endif
206 
207#endif /* !_INCLUDE_DMV170_h */
208/* end of include file */
209
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