1 | /* dmv170.h |
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2 | * |
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3 | * This include file contains information pertaining to the DMV170. |
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4 | * |
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5 | * NOTE: Other than where absolutely required, this version currently |
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6 | * supports only the peripherals and bits used by the basic board |
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7 | * support package. This includes at least significant pieces of |
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8 | * the following items: |
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9 | * |
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10 | * + UART Channels A and B |
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11 | * |
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12 | * COPYRIGHT (c) 1989-1997. |
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13 | * On-Line Applications Research Corporation (OAR). |
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14 | * Copyright assigned to U.S. Government, 1994. |
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15 | * |
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16 | * The license and distribution terms for this file may in |
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17 | * the file LICENSE in this distribution or at |
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18 | * http://www.OARcorp.com/rtems/license.html. |
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19 | * |
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20 | * $Id$ |
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21 | */ |
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22 | |
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23 | #ifndef _INCLUDE_DMV170_h |
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24 | #define _INCLUDE_DMV170_h |
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25 | |
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26 | |
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27 | /* |
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28 | * DY-4 uses a non-standard clock for the Exar 88681. |
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29 | */ |
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30 | |
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31 | #undef MC68681_BAUD_RATE_MASK_9600 |
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32 | #define MC68681_BAUD_RATE_MASK_9600 |
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33 | |
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34 | #define DMV17x_MC68681_BAUD_RATE_MASK_9600 |
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35 | |
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36 | #if 0 |
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37 | #define MC68681_OFFSET_MULTIPLIER 8 |
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38 | #endif |
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39 | |
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40 | #ifdef __cplusplus |
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41 | extern "C" { |
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42 | #endif |
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43 | |
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44 | /* Note: Move address defs to the linker files. XXX */ |
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45 | |
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46 | /* Real Time Clock Base Address */ |
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47 | #define DMV170_RTC_ADDRESS 0xf2c00000 |
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48 | |
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49 | /* base address of the DUART (68681) */ |
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50 | #define MC68681_ADDR 0xf2800000 |
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51 | #define MC68681_PORT1_ADDR 0xf2800000 |
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52 | #define MC68681_PORT2_ADDR 0xf2800040 |
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53 | |
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54 | /* |
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55 | * SONIC Information |
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56 | */ |
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57 | |
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58 | #define DMV170_SONIC_ADDR 0xf3000000 |
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59 | |
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60 | #define SONIC_BASE_ADDRESS DMV170_SONIC_ADDR |
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61 | #define SONIC_VECTOR DMV170_ETHERNET_IRQ |
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62 | |
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63 | /* base address for the SCC (85C30) */ |
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64 | #define Z85C30_ADDR 0xfb000010 |
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65 | #define Z85C30_CTRL_A 0xfb000010 |
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66 | #define Z85C30_DATA_A 0xfb000018 |
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67 | #define Z85C30_CTRL_B 0xfb000000 |
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68 | #define Z85C30_DATA_B 0xfb000008 |
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69 | #define Z85C30_CLOCK_10 (10485760) /* 10 Mhz */ |
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70 | #define Z85C30_CLOCK_2 (2581175) /* 2.4616 Mhz */ |
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71 | |
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72 | /* base address for the SCV64 */ |
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73 | #define DMV170_SCV64_BASE_ADDRESS 0xf2000000 |
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74 | |
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75 | #define DMV170_LOCAL_CONTROL_STATUS_REG 0xf2400000 |
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76 | #define DMV170_TIMER0_COUNT_INTERVAL_REG 0xf2400008 |
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77 | #define DMV170_TIMER1_COUNT_INTERVAL_REG 0xf2400010 |
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78 | #define DMV170_TIMER2_COUNT_INTERVAL_REG 0xf2400018 |
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79 | #define DMV170_TIMER_CONTROL_REG 0xf2400020 |
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80 | #define DMV170_CARD_RESORCE_REG 0xf2400040 |
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81 | |
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82 | #define DMV170_WRITE( _reg, _data ) \ |
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83 | *((volatile rtems_unsigned16 *)(_reg)) = (_data) |
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84 | |
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85 | #define DMV170_READ( _reg, _data ) \ |
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86 | (_data) = *((volatile rtems_unsigned16 *)(_reg)) |
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87 | |
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88 | /* |
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89 | * The following defines the bits in the DMA Control and Status Register |
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90 | */ |
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91 | |
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92 | /* XXX fill in the other bits */ |
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93 | |
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94 | #define DMV170_DMA_CONTROL_STATUS_REG 0xfc000090 |
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95 | |
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96 | #define DMV170_SCC_10MHZ 0x00010000 |
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97 | |
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98 | /* |
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99 | * The following defines the bits in the Local Control and Status Register. |
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100 | */ |
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101 | #define DMV170_IPLx_MASK 0x0007 |
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102 | #define DMV170_MAXPACK_SENSE_MASK 0x0008 |
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103 | #define DMV170_MAXPACK_NOT_INSTALLED 0x0008 |
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104 | #define DMV170_MAXPACK_INSTALLED 0x0000 |
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105 | |
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106 | #define DMV170_MAXPACK_RESET_MASK 0x0010 |
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107 | #define DMV170_MAXPACK_RESET_NEGATE 0x0010 |
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108 | #define DMV170_MAXPACK_RESET_ASSERT 0x0000 |
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109 | #define DMV170_EEPROM_READ_WRITE_MASK 0x0020 |
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110 | #define DMV170_EEPROM_READ 0x0020 |
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111 | #define DMV170_EEPROM_WRITE 0x0000 |
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112 | #define DMV170_EEPROM_CLOCK_CTRL_MASK 0x0040 |
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113 | #define DMV170_EEPROM_CLOCK_ASSERT 0x0040 |
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114 | #define DMV170_EEPROM_CLOCK_NEGATE 0x0000 |
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115 | #define DMV170_EEPROM_DATA_MASK 0x0080 |
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116 | #define DMV170_EEPROM_DATA_HIGH 0x0080 |
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117 | #define DMV170_EEPROM_DATA_LOW 0x0000 |
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118 | |
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119 | /* Bits 8-10: 68040 Transfer Modifer Codes represent the Transfer |
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120 | * Modifier to be used on MAXPack Accesses. |
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121 | * |
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122 | * Bit 11 : 68040 Transfer Type (TT) 0:TT are both low 1:TT are both high |
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123 | */ |
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124 | |
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125 | #define DMV170_USER_LINK0_STATUS_MASK 0x1000 |
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126 | #define DMV170_USER_LINK0_OPEN 0x1000 |
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127 | #define DMV170_USER_LINK0_INSTALLED 0x0000 |
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128 | #define DMV170_LOWER_STATUS_LED_CONTROL_MASK 0x2000 |
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129 | #define DMV170_LOWER_STATUS_LED_IS_OFF 0x2000 |
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130 | #define DMV170_LOWER_STATUS_LED_IS_ON 0x0000 |
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131 | #ifdef DMV176 |
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132 | /* The following are not available for the DMV171 */ |
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133 | #define DMV170_RAM_TYPE_MASK 0x4000 |
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134 | #define DMV170_RAM_TYPE_IS_DRAM 0x4000 |
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135 | #define DMV170_RAM_TYPE_IS_SRAM 0x0000 |
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136 | #define DMV170_IACK_VECTOR_AUTOVECTOR_MASK 0x8000 |
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137 | #define DMV170_IACK_VECTOR_AUTOVECTOR_IS_VECTOR 0x8000 |
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138 | #define DMV170_IACK_VECTOR_AUTOVECTOR_IS_NOT_VECTOR 0x0000 |
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139 | #endif |
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140 | |
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141 | /* |
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142 | * The following defines the bits in the Timer Control Register. |
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143 | */ |
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144 | |
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145 | #define DMV170_TIMER0_ENABLE_MASK 0x0001 |
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146 | #define DMV170_TIMER0_IS_ENABLED 0x0001 |
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147 | #define DMV170_TIMER0_IS_DISABLED 0x0000 |
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148 | #define DMV170_TIMER1_ENABLE_MASK 0x0002 |
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149 | #define DMV170_TIMER1_IS_ENABLED 0x0002 |
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150 | #define DMV170_TIMER1_IS_DISABLED 0x0000 |
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151 | #define DMV170_TIMER2_ENABLE_MASK 0x0004 |
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152 | #define DMV170_TIMER2_IS_ENABLED 0x0004 |
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153 | #define DMV170_TIMER2_IS_DISABLED 0x0000 |
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154 | #define DMV170_TIMER1_CLOCK_MASK 0x0008 |
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155 | #define DMV170_TIMER1_CLOCK_AT_TIMER0 0x0008 |
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156 | #define DMV170_TIMER1_CLOCK_AT_1MHZ 0x0000 |
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157 | |
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158 | #define DMV170_TIMER2_CLOCK_MASK 0x0010 |
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159 | #define DMV170_TIMER2_CLOCK_AT_TIMER0 0x0010 |
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160 | #define DMV170_TIMER2_CLOCK_AT_1MHZ 0x0000 |
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161 | #define DMV170_TIMER0_INTERRUPT_MASK 0x0020 |
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162 | #define DMV170_TIMER0_INTERRUPT_ENABLE 0x0020 |
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163 | #define DMV170_TIMER0_INTERRUPT_CLEAR 0x0000 |
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164 | #define DMV170_TIMER1_INTERRUPT_MASK 0x0040 |
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165 | #define DMV170_TIMER1_INTERRUPT_ENABLE 0x0040 |
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166 | #define DMV170_TIMER1_INTERRUPT_CLEAR 0x0000 |
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167 | #define DMV170_TIMER2_INTERRUPT_MASK 0x0080 |
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168 | #define DMV170_TIMER2_INTERRUPT_ENABLE 0x0080 |
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169 | #define DMV170_TIMER2_INTERRUPT_CLEAR 0x0000 |
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170 | |
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171 | /* |
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172 | * The Following define the bits for the Card Resource Register. |
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173 | */ |
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174 | |
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175 | #define DMV170_DUART_INTERRUPT_MASK 0x0001 /* DUART Interrupt Sense Bit */ |
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176 | #define DMV170_DUART_INTERRUPT_NEGATE 0x0001 |
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177 | #define DMV170_DUART_INTERRUPT_ASSERT 0x0000 |
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178 | #define DMV170_SONIC_INTERRUPT_MASK 0x0002 /* SONIC Interrupt Sense Bit */ |
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179 | #define DMV170_SONIC_INTERRUPT_NEGATE 0x0002 |
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180 | #define DMV170_SONIC_INTERRUPT_ASSERT 0x0000 |
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181 | #define DMV170_SCSI_INTERRUPT_MASK 0x0004 /* SCSI Interrupt Sense Bit */ |
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182 | #define DMV170_SCSI_INTERRUPT_NEGATE 0x0004 |
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183 | #define DMV170_SCSI_INTERRUPT_ASSERT 0x0000 |
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184 | #define DMV170_SCC_INTERRUPT_MASK 0x0008 /* SCC Interrupt Sense Bit */ |
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185 | #define DMV170_SCC_INTERRUPT_NEGATE 0x0008 |
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186 | #define DMV170_SCC_INTERRUPT_ASSERT 0x0000 |
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187 | #define DMV170_SNOOP_ENABLE_MASK 0x0010 /* CPU Snoop Enable Bit */ |
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188 | #define DMV170_SNOOP_DISABLE 0x0010 |
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189 | #define DMV170_SNOOP_ENABLE 0x0000 |
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190 | #define DMV170_SONIC_RESET_MASK 0x0020 /* SONIC RESET Control */ |
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191 | #define DMV170_SONIC_RESET_CLEAR 0x0020 |
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192 | #define DMV170_SONIC_RESET_HOLD 0x0000 |
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193 | #define DMV170_NV64_WE_MASK 0x0040 /* 64-bit Non-Volital Memory */ |
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194 | #define DMV170_NV64_WRITE_ENABLE 0x0040 /* Write Enable */ |
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195 | #define DMV170_NV64_WRITE_DISABLE 0x0000 |
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196 | #define DMV170_BOOT_NV16_MASK 0x0080 /* BOOT Device Type */ |
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197 | #define DMV170_BOOT_64_BIT 0x0080 |
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198 | #define DMV170_BOOT_16_BIT 0x0000 |
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199 | #define DMV170_DUART_INST_MASK 0x0100 /* DUART Sense Bit */ |
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200 | #define DMV170_DUART_INSTALLED 0x0100 |
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201 | #define DMV170_DUART_NOT_INSTALLED 0x0000 |
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202 | #define DMV170_SONIC_INST_MASK 0x0200 /* SONIC Sense Bit */ |
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203 | #define DMV170_SONIC_INSTALLED 0x0200 |
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204 | #define DMV170_SONIC_NOT_INSTALLED 0x0000 |
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205 | #define DMV170_16M_NV64_MASK 0x0400 /* 16 Mb of 64bit Flash Sense */ |
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206 | #define DMV170_16Mb_FLASH_INSTALLED 0x0400 |
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207 | #define DMV170_8Mb_FLASH_INSTALLED 0x0000 |
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208 | #define DMV170_SCC_INST_MASK 0x0800 /* SCC Sense Bit */ |
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209 | #define DMV170_SCC_INSTALLED 0x0800 |
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210 | #define DMV170_SCC_NOT_INSTALLED 0x0000 |
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211 | #define DMV170_RTC_INST_MASK 0x1000 /* RTC Sense Bit */ |
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212 | #define DMV170_RTC_INSTALLED 0x1000 |
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213 | #define DMV170_RTC_NOT_INSTALLED 0x0000 |
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214 | #define DMV170_NV64_INST_MASK 0x2000 /* 64bit Non-Volital Mem Sense*/ |
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215 | |
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216 | #define DMV170_64_BIT_NON_VOLITAL_MEM_INSTALLED 0x2000 |
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217 | #define DMV170_64_BIT_NON_VOLITAL_MEM_NOT_INSTALLED 0x0000 |
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218 | |
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219 | |
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220 | /* |
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221 | * DUART Baud Rate Definitions. |
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222 | */ |
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223 | |
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224 | #define DMV170_DUART_9621 MC68681_BAUD_RATE_MASK_600 /* close to 9600 */ |
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225 | |
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226 | #define DMV170_RTC_FREQUENCY 0x0000 |
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227 | |
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228 | |
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229 | /* |
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230 | * CPU General Purpose Interrupt definations (PPC_IRQ_EXTERNAL). |
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231 | * Note: For the interrupt level read the lower 3 bits of the |
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232 | * Local Control and Status Register. |
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233 | */ |
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234 | |
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235 | #define DMV170_IRQ_FIRST ( PPC_IRQ_LAST + 1 ) |
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236 | |
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237 | #define DMV170_LIRQ0 ( DMV170_IRQ_FIRST + 0 ) |
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238 | #define DMV170_LIRQ1 ( DMV170_IRQ_FIRST + 1 ) |
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239 | #define DMV170_LIRQ2 ( DMV170_IRQ_FIRST + 2 ) |
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240 | #define DMV170_LIRQ3 ( DMV170_IRQ_FIRST + 3 ) |
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241 | #define DMV170_LIRQ4 ( DMV170_IRQ_FIRST + 4 ) |
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242 | #define DMV170_LIRQ5 ( DMV170_IRQ_FIRST + 5 ) |
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243 | #define DMV170_L7IACF ( DMV170_IRQ_FIRST + 6 ) |
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244 | #define DMV170_L7ISYS ( DMV170_IRQ_FIRST + 7 ) |
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245 | #define DMV170_L7IMNI ( DMV170_IRQ_FIRST + 8 ) |
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246 | #define DMV170_BIMODE ( DMV170_IRQ_FIRST + 9 ) |
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247 | |
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248 | #define DMV170_DUART_IRQ DMV170_LIRQ5 |
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249 | #define DMV170_ETHERNET_IRQ DMV170_LIRQ5 |
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250 | #define DMV170_SCSI_IRQ DMV170_LIRQ5 |
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251 | #define DMV170_SCC_IRQ DMV170_LIRQ5 |
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252 | #define DMV170_MEZZANINE_IRQ_0 DMV170_LIRQ4 |
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253 | #define DMV170_TICK_IRQ DMV170_LIRQ3 |
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254 | #define DMV170_LOCATION_MON_IRQ DMV170_LIRQ2 |
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255 | #define DMV170_SCV64_IRQ DMV170_LIRQ1 |
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256 | #define DMV170_RTC_IRQ DMV170_LIRQ0 |
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257 | |
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258 | #define DMV170_ACFAIL_IRQ DMV170_L7IACF |
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259 | #define DMV170_SYSFAIL_IRQ DMV170_L7ISYS |
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260 | #define DMV170_WATCHDOG_IRQ DMV170_L7IMNI |
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261 | #define DMV170_BI_IRQ DMV170_BIMODE |
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262 | #define DMV170_RAM_PARITY_IRQ ( DMV170_IRQ_FIRST + 10) |
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263 | #define DMV170_DARF_BUS_ERROR_IRQ ( DMV170_IRQ_FIRST + 11) |
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264 | #define DMV170_PERIPHERAL_IRQ ( DMV170_IRQ_FIRST + 12) |
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265 | |
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266 | #define MAX_BOARD_IRQS DMV170_PERIPHERAL_IRQ |
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267 | |
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268 | #define SCV64_Is_IRQ0( _status ) (_status&0x01) |
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269 | #define SCV64_Is_IRQ1( _status ) (_status&0x02) |
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270 | #define SCV64_Is_IRQ2( _status ) (_status&0x04) |
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271 | #define SCV64_Is_IRQ3( _status ) (_status&0x08) |
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272 | #define SCV64_Is_IRQ4( _status ) (_status&0x10) |
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273 | #define SCV64_Is_IRQ5( _status ) (_status&0x20) |
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274 | |
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275 | |
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276 | /* |
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277 | * Card Resource Register Constants |
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278 | */ |
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279 | |
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280 | #define DMV170_DUART_PRESENT_BIT 0x0100 |
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281 | #define DMV170_SONIC_PRESENT_BIT 0x0200 |
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282 | #define DMV170_16MBYTES_FLASH_BIT 0x0400 |
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283 | #define DMV170_SCC_PRESENT_BIT 0x0800 |
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284 | #define DMV170_RTC_PRESENT_BIT 0x1000 |
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285 | |
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286 | /* |
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287 | * scv64.c |
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288 | */ |
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289 | |
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290 | void SCV64_Generate_DUART_Interrupts(); |
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291 | rtems_unsigned32 SCV64_Get_Interrupt(); |
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292 | rtems_unsigned32 SCV64_Get_Interrupt_Enable(); |
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293 | |
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294 | #ifdef __cplusplus |
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295 | } |
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296 | #endif |
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297 | |
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298 | #endif /* !_INCLUDE_DMV170_h */ |
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299 | /* end of include file */ |
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300 | |
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