source: rtems/c/src/lib/libbsp/powerpc/dmv177/include/dmv170.h @ 0b48b35

4.104.114.84.95
Last change on this file since 0b48b35 was 0b48b35, checked in by Joel Sherrill <joel.sherrill@…>, on Oct 12, 2001 at 9:07:26 PM

2001-10-12 Joel Sherrill <joel@…>

  • clock/clock.c, console/debugio.c, include/dmv170.h, startup/setvec.c, startup/vmeintr.c: Fixed typo.
  • Property mode set to 100644
File size: 11.6 KB
Line 
1/*  dmv170.h
2 *
3 *  This include file contains information pertaining to the DMV170.
4 *
5 *  NOTE:  Other than where absolutely required, this version currently
6 *         supports only the peripherals and bits used by the basic board
7 *         support package. This includes at least significant pieces of
8 *         the following items:
9 *
10 *           + UART Channels A and B
11 *
12 *  COPYRIGHT (c) 1989-1997.
13 *  On-Line Applications Research Corporation (OAR).
14 *
15 *  The license and distribution terms for this file may in
16 *  the file LICENSE in this distribution or at
17 *  http://www.OARcorp.com/rtems/license.html.
18 *
19 *  $Id$
20 */
21 
22#ifndef _INCLUDE_DMV170_h
23#define _INCLUDE_DMV170_h
24
25
26/*
27 *  DY-4 uses a non-standard clock for the Exar 88681.
28 */
29
30#undef  MC68681_BAUD_RATE_MASK_9600
31#define MC68681_BAUD_RATE_MASK_9600
32
33#define DMV17x_MC68681_BAUD_RATE_MASK_9600
34
35#if 0
36#define MC68681_OFFSET_MULTIPLIER 8
37#endif
38
39#ifdef __cplusplus
40extern "C" {
41#endif
42
43/* Note:  Move address defs to the linker files. XXX */
44
45/* Real Time Clock Base Address */
46#define DMV170_RTC_ADDRESS   0xf2c00000
47
48/* base address of the DUART (68681) */
49#define MC68681_ADDR         0xf2800000
50#define MC68681_PORT1_ADDR   0xf2800000
51#define MC68681_PORT2_ADDR   0xf2800040
52
53/*
54 *  SONIC Information
55 */
56
57#define DMV170_SONIC_ADDR 0xf3000000
58
59#define SONIC_BASE_ADDRESS DMV170_SONIC_ADDR
60#define SONIC_VECTOR       DMV170_ETHERNET_IRQ
61
62/* base address for the SCC (85C30) */ 
63#define Z85C30_ADDR       0xfb000010
64#define Z85C30_CTRL_A     0xfb000010
65#define Z85C30_DATA_A     0xfb000018
66#define Z85C30_CTRL_B     0xfb000000
67#define Z85C30_DATA_B     0xfb000008
68#define Z85C30_CLOCK_10   (10485760)      /* 10 Mhz */
69#define Z85C30_CLOCK_2    (2581175)       /* 2.4616 Mhz */
70
71/* base address for the SCV64 */
72#define DMV170_SCV64_BASE_ADDRESS                        0xf2000000
73
74#define DMV170_LOCAL_CONTROL_STATUS_REG                   0xf2400000
75#define DMV170_TIMER0_COUNT_INTERVAL_REG                  0xf2400008
76#define DMV170_TIMER1_COUNT_INTERVAL_REG                  0xf2400010
77#define DMV170_TIMER2_COUNT_INTERVAL_REG                  0xf2400018
78#define DMV170_TIMER_CONTROL_REG                          0xf2400020
79#define DMV170_CARD_RESORCE_REG                           0xf2400040
80
81#define DMV170_WRITE( _reg, _data ) \
82   *((volatile rtems_unsigned16 *)(_reg)) = (_data)
83
84#define DMV170_READ( _reg, _data ) \
85   (_data) = *((volatile rtems_unsigned16 *)(_reg))
86
87/*
88 *  The following defines the bits in the DMA Control and Status Register
89 */
90
91/* XXX fill in the other bits */
92
93#define DMV170_DMA_CONTROL_STATUS_REG                     0xfc000090
94
95#define DMV170_SCC_10MHZ                                  0x00010000
96
97/*
98 *  The following defines the bits in the Local Control and Status Register.
99 */
100#define DMV170_IPLx_MASK                                  0x0007
101#define DMV170_MAXPACK_SENSE_MASK                         0x0008
102#define DMV170_MAXPACK_NOT_INSTALLED                      0x0008
103#define DMV170_MAXPACK_INSTALLED                          0x0000
104
105#define DMV170_MAXPACK_RESET_MASK                         0x0010
106#define DMV170_MAXPACK_RESET_NEGATE                       0x0010
107#define DMV170_MAXPACK_RESET_ASSERT                       0x0000
108#define DMV170_EEPROM_READ_WRITE_MASK                     0x0020
109#define DMV170_EEPROM_READ                                0x0020
110#define DMV170_EEPROM_WRITE                               0x0000
111#define DMV170_EEPROM_CLOCK_CTRL_MASK                     0x0040
112#define DMV170_EEPROM_CLOCK_ASSERT                        0x0040
113#define DMV170_EEPROM_CLOCK_NEGATE                        0x0000
114#define DMV170_EEPROM_DATA_MASK                           0x0080
115#define DMV170_EEPROM_DATA_HIGH                           0x0080
116#define DMV170_EEPROM_DATA_LOW                            0x0000
117
118/* Bits 8-10: 68040 Transfer Modifer Codes represent the Transfer
119 *            Modifier to be used on MAXPack Accesses.
120 *
121 * Bit 11   : 68040 Transfer Type (TT) 0:TT are both low 1:TT are both high
122 */
123
124#define DMV170_USER_LINK0_STATUS_MASK                     0x1000
125#define DMV170_USER_LINK0_OPEN                            0x1000
126#define DMV170_USER_LINK0_INSTALLED                       0x0000
127#define DMV170_LOWER_STATUS_LED_CONTROL_MASK              0x2000
128#define DMV170_LOWER_STATUS_LED_IS_OFF                    0x2000
129#define DMV170_LOWER_STATUS_LED_IS_ON                     0x0000
130#ifdef DMV176                                             
131       /* The following are not available for the DMV171 */
132#define DMV170_RAM_TYPE_MASK                              0x4000
133#define DMV170_RAM_TYPE_IS_DRAM                           0x4000
134#define DMV170_RAM_TYPE_IS_SRAM                           0x0000
135#define DMV170_IACK_VECTOR_AUTOVECTOR_MASK                0x8000
136#define DMV170_IACK_VECTOR_AUTOVECTOR_IS_VECTOR           0x8000
137#define DMV170_IACK_VECTOR_AUTOVECTOR_IS_NOT_VECTOR       0x0000
138#endif
139 
140/*
141 *  The following defines the bits in the Timer Control Register.
142 */
143
144#define DMV170_TIMER0_ENABLE_MASK                         0x0001
145#define DMV170_TIMER0_IS_ENABLED                          0x0001
146#define DMV170_TIMER0_IS_DISABLED                         0x0000
147#define DMV170_TIMER1_ENABLE_MASK                         0x0002
148#define DMV170_TIMER1_IS_ENABLED                          0x0002
149#define DMV170_TIMER1_IS_DISABLED                         0x0000
150#define DMV170_TIMER2_ENABLE_MASK                         0x0004
151#define DMV170_TIMER2_IS_ENABLED                          0x0004
152#define DMV170_TIMER2_IS_DISABLED                         0x0000
153#define DMV170_TIMER1_CLOCK_MASK                          0x0008
154#define DMV170_TIMER1_CLOCK_AT_TIMER0                     0x0008
155#define DMV170_TIMER1_CLOCK_AT_1MHZ                       0x0000
156
157#define DMV170_TIMER2_CLOCK_MASK                          0x0010
158#define DMV170_TIMER2_CLOCK_AT_TIMER0                     0x0010
159#define DMV170_TIMER2_CLOCK_AT_1MHZ                       0x0000
160#define DMV170_TIMER0_INTERRUPT_MASK                      0x0020
161#define DMV170_TIMER0_INTERRUPT_ENABLE                    0x0020
162#define DMV170_TIMER0_INTERRUPT_CLEAR                     0x0000
163#define DMV170_TIMER1_INTERRUPT_MASK                      0x0040
164#define DMV170_TIMER1_INTERRUPT_ENABLE                    0x0040
165#define DMV170_TIMER1_INTERRUPT_CLEAR                     0x0000
166#define DMV170_TIMER2_INTERRUPT_MASK                      0x0080
167#define DMV170_TIMER2_INTERRUPT_ENABLE                    0x0080
168#define DMV170_TIMER2_INTERRUPT_CLEAR                     0x0000
169
170/*
171 *  The Following define the bits for the Card Resource Register.
172 */
173
174#define DMV170_DUART_INTERRUPT_MASK    0x0001  /* DUART Interrupt Sense Bit  */
175#define DMV170_DUART_INTERRUPT_NEGATE  0x0001
176#define DMV170_DUART_INTERRUPT_ASSERT  0x0000
177#define DMV170_SONIC_INTERRUPT_MASK    0x0002  /* SONIC Interrupt Sense Bit  */
178#define DMV170_SONIC_INTERRUPT_NEGATE  0x0002
179#define DMV170_SONIC_INTERRUPT_ASSERT  0x0000
180#define DMV170_SCSI_INTERRUPT_MASK     0x0004  /* SCSI Interrupt Sense Bit   */
181#define DMV170_SCSI_INTERRUPT_NEGATE   0x0004
182#define DMV170_SCSI_INTERRUPT_ASSERT   0x0000
183#define DMV170_SCC_INTERRUPT_MASK      0x0008  /* SCC Interrupt Sense Bit    */
184#define DMV170_SCC_INTERRUPT_NEGATE    0x0008
185#define DMV170_SCC_INTERRUPT_ASSERT    0x0000
186#define DMV170_SNOOP_ENABLE_MASK       0x0010  /* CPU Snoop Enable Bit       */
187#define DMV170_SNOOP_DISABLE           0x0010
188#define DMV170_SNOOP_ENABLE            0x0000
189#define DMV170_SONIC_RESET_MASK        0x0020  /* SONIC RESET Control        */
190#define DMV170_SONIC_RESET_CLEAR       0x0020
191#define DMV170_SONIC_RESET_HOLD        0x0000
192#define DMV170_NV64_WE_MASK            0x0040  /* 64-bit Non-Volital Memory  */
193#define DMV170_NV64_WRITE_ENABLE       0x0040  /* Write Enable               */
194#define DMV170_NV64_WRITE_DISABLE      0x0000
195#define DMV170_BOOT_NV16_MASK          0x0080  /* BOOT Device Type           */
196#define DMV170_BOOT_64_BIT             0x0080
197#define DMV170_BOOT_16_BIT             0x0000
198#define DMV170_DUART_INST_MASK         0x0100  /* DUART Sense Bit            */
199#define DMV170_DUART_INSTALLED         0x0100
200#define DMV170_DUART_NOT_INSTALLED     0x0000
201#define DMV170_SONIC_INST_MASK         0x0200  /* SONIC Sense Bit            */
202#define DMV170_SONIC_INSTALLED         0x0200
203#define DMV170_SONIC_NOT_INSTALLED     0x0000
204#define DMV170_16M_NV64_MASK           0x0400  /* 16 Mb of 64bit Flash Sense */
205#define DMV170_16Mb_FLASH_INSTALLED    0x0400
206#define DMV170_8Mb_FLASH_INSTALLED     0x0000
207#define DMV170_SCC_INST_MASK           0x0800  /* SCC Sense Bit              */
208#define DMV170_SCC_INSTALLED           0x0800
209#define DMV170_SCC_NOT_INSTALLED       0x0000
210#define DMV170_RTC_INST_MASK           0x1000  /* RTC Sense Bit              */
211#define DMV170_RTC_INSTALLED           0x1000
212#define DMV170_RTC_NOT_INSTALLED       0x0000
213#define DMV170_NV64_INST_MASK          0x2000  /* 64bit Non-Volital Mem Sense*/
214
215#define DMV170_64_BIT_NON_VOLITAL_MEM_INSTALLED           0x2000
216#define DMV170_64_BIT_NON_VOLITAL_MEM_NOT_INSTALLED       0x0000
217
218
219/*
220 * DUART Baud Rate Definitions.
221 */
222
223#define DMV170_DUART_9621     MC68681_BAUD_RATE_MASK_600 /* close to 9600 */ 
224
225#define DMV170_RTC_FREQUENCY             0x0000
226
227
228/*
229 * CPU General Purpose Interrupt definations (PPC_IRQ_EXTERNAL).
230 * Note: For the interrupt level read the lower 3 bits of the
231 *       Local Control and Status Register.
232 */
233
234#define DMV170_IRQ_FIRST                       ( PPC_IRQ_LAST +  1 )
235
236#define DMV170_LIRQ0                           ( DMV170_IRQ_FIRST + 0 )
237#define DMV170_LIRQ1                           ( DMV170_IRQ_FIRST + 1 )
238#define DMV170_LIRQ2                           ( DMV170_IRQ_FIRST + 2 )
239#define DMV170_LIRQ3                           ( DMV170_IRQ_FIRST + 3 )
240#define DMV170_LIRQ4                           ( DMV170_IRQ_FIRST + 4 )
241#define DMV170_LIRQ5                           ( DMV170_IRQ_FIRST + 5 )
242#define DMV170_L7IACF                          ( DMV170_IRQ_FIRST + 6 )
243#define DMV170_L7ISYS                          ( DMV170_IRQ_FIRST + 7 )
244#define DMV170_L7IMNI                          ( DMV170_IRQ_FIRST + 8 )
245#define DMV170_BIMODE                          ( DMV170_IRQ_FIRST + 9 )
246
247#define DMV170_DUART_IRQ                       DMV170_LIRQ5
248#define DMV170_ETHERNET_IRQ                    DMV170_LIRQ5
249#define DMV170_SCSI_IRQ                        DMV170_LIRQ5
250#define DMV170_SCC_IRQ                         DMV170_LIRQ5
251#define DMV170_MEZZANINE_IRQ_0                 DMV170_LIRQ4       
252#define DMV170_TICK_IRQ                        DMV170_LIRQ3
253#define DMV170_LOCATION_MON_IRQ                DMV170_LIRQ2       
254#define DMV170_SCV64_IRQ                       DMV170_LIRQ1
255#define DMV170_RTC_IRQ                         DMV170_LIRQ0
256
257#define DMV170_ACFAIL_IRQ                      DMV170_L7IACF
258#define DMV170_SYSFAIL_IRQ                     DMV170_L7ISYS
259#define DMV170_WATCHDOG_IRQ                    DMV170_L7IMNI
260#define DMV170_BI_IRQ                          DMV170_BIMODE
261#define DMV170_RAM_PARITY_IRQ                  ( DMV170_IRQ_FIRST + 10)
262#define DMV170_DARF_BUS_ERROR_IRQ              ( DMV170_IRQ_FIRST + 11)
263#define DMV170_PERIPHERAL_IRQ                  ( DMV170_IRQ_FIRST + 12)
264
265#define MAX_BOARD_IRQS                         DMV170_PERIPHERAL_IRQ
266
267#define SCV64_Is_IRQ0( _status ) (_status&0x01)
268#define SCV64_Is_IRQ1( _status ) (_status&0x02)
269#define SCV64_Is_IRQ2( _status ) (_status&0x04)
270#define SCV64_Is_IRQ3( _status ) (_status&0x08)
271#define SCV64_Is_IRQ4( _status ) (_status&0x10)
272#define SCV64_Is_IRQ5( _status ) (_status&0x20)
273
274
275/*
276 *  scv64.c
277 */
278
279void SCV64_Generate_DUART_Interrupts();
280rtems_unsigned32 SCV64_Get_Interrupt();
281rtems_unsigned32 SCV64_Get_Interrupt_Enable();
282
283#ifdef __cplusplus
284}
285#endif
286 
287#endif /* !_INCLUDE_DMV170_h */
288/* end of include file */
289
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