source: rtems/c/src/lib/libbsp/powerpc/dmv177/QUIRKS @ db8e8a8b

4.104.114.84.95
Last change on this file since db8e8a8b was db8e8a8b, checked in by Joel Sherrill <joel.sherrill@…>, on Aug 14, 1998 at 3:23:33 PM

Added information on caching.

  • Property mode set to 100644
File size: 2.6 KB
Line 
1#
2#  Quirks in the DY-4 DMV177
3#
4#  $Id$
5#
6
7JTAG and Caching
8================
9If data or code caching is enabled on certain revisions of the PPC603e,
10then the JTAG emulator interface become disfunctional.  You can not
11debug using the emulator on these chip revisions.  On certain revisions,
12it is so bad that when code caching is enabled, you can not even
13download code reliably to the board.
14
15Caching and Peripherals
16=======================
17When caching is enabled, care must be exercised to insure that all
18peripheral addresses are still uncached.
19
20Exar 88681 Clock
21================
22This board uses a different clock for the Exar 88681 DUART than is
23documented in the Exar manual or the original MC68681 manual.  This
24resulted in the need for the the mc68681 libchip driver to support
25BSP specific baud rate tables and the development of a DMV177
26specific baud rate table.
27
28In the end, this all works but you have a very limited range of
29useful baud rates on the 88681 ports compared to what would have
30been supported had DY-4 just followed the Exar or Motorola manual.
31
32
33SCC Addresses
34=============
35The full set of SCC addresses is not documented in the DY-4 manual
36and they are not ordered as one would expect.  Normally the four
37SCC registers are ordered Control A, Data A, Control B, and Data B.
38DY-4 orders them with B first.
39
40This required extra time to debug.
41
42
43SCV64 and the Foundation Firmware
44=================================
45DY-4 technical support did not offer code to determine which interrupt
46sources were pending at the SCV64.  They recommended calling into the
47Foundation Firmware ROM monitor to figure this out.  The Foundation
48Firmware did not recognize enough interrupts on this board to be useful.
49
50In the end, we gave up on their technical support's recommendation
51and directly manipulated the SVC64.  This is what we wanted to do in
52the first place but we got no information from them to aid in this.
53Luckily, the manual does document enough of DY-4's mapping of the specific
54interrupt sources to make this work.
55
56
57Z85C30 SCC Clock Speed
58======================
59
60The Z85C30 SCC can be factory configured for 10 Mhz or 2.4616 Mhz.  Code
61had to be added to dynamically determine which clock was installed.
62
63The board we had used a 10 Mhz clock.  No testing was done with a 2.4616 Mhz
64clock.
65
66
67P2 Octopus Cable
68================
69
70DY-4's P2 breakout is large and a bit unwieldy.  It was difficult to
71fight into the VME cage we used.  The SCSI connector comes off the
72side and is very stiff thus making it difficult to route around
73anything in the back of the cage.  We gave up on trying to use
74it in the first few slots of OAR's cage.
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